Introduction Why Full adders are important? Modern portable electronics require: Smaller silicon...
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Introduction Why Full adders are important? Modern portable electronics require: Smaller silicon area, Higher speeds, Longer battery life, and More reliability
Introduction Why Full adders are important? Modern portable
electronics require: Smaller silicon area, Higher speeds, Longer
battery life, and More reliability Adders are an extensively used
component in datapaths.
Slide 3
Different Logic Styles Static CMOS Existence of pMOS which has
low mobility compared to nMOS High Input capacitance. Complementary
Pass Transistor (CPL) Large power consumption. Layout is not easy
due to irregular transistor arrangement. Transmission-function full
adder (TFA) Transmission-gate full adder (TGA) Lack driving
capability. Dynamic CMOS Higher switching activity and lower noise
immunity. Large portion of the power in driving the clock lines
More susceptible to leakage
Slide 4
Hybrid Logic Styles Use more than one logic style for their
implementation.
Slide 5
Categorization of Full-Adder The outputs of a 1-b full adder
can be generally expressed as The three broad categories are as
follows A. XORXOR-Based Full Adder B. XNORXNOR-Based Full Adder C.
Centralized Full Adder
Slide 6
XORXOR-Based Full Adder The general form of this category is
expressed as follows, Where H is and is the complement of H.
Slide 7
XONRXONR-Based Full Adder The general form of this category is
expressed as follows,
Slide 8
Centralized Full Adder The general form of this category is
expressed as follows,
Slide 9
Module I Proposed XOR-XNOR circuit Based on CPL logic using
only one inverter. Cross-coupled pMOS transistors guarantees Full
swing operation and reduce short circuit current
Slide 10
Module I Comparison
Slide 11
Module II Different circuits are compared The circuit shown in
figure is one of the best performance and has Good driving
capabilities No Short Circuit currents
Slide 12
Module III The output can be expressed as TG logic style is
used as they consume very low power. Static-CMOS logic style also
used because of its robustness and good noise margins The carry is
evaluated using the following logic expression
Slide 13
Module III Comparison
Slide 14
Full Adder Module I Module II Module III
Slide 15
Simulation Setup Circuit layout is extracted using TSMC 0.18m
technology. All the possible input combinations are considered for
all the test circuits All the simulated circuits are prototyped at
optimum transistor sizing The circuits are tested for a range of
supply voltages (0.81.8 V) at 50-MHz frequency Different loading
conditions to evaluate the performance of the test circuits (5.6200
fF) Each adder is embedded in a 4- and 8-b 4-operand carrysave
array adder (CSA) with final carrypropagate adder (CPA).
Slide 16
Simulation Results: Delay TFA and TGA have the smallest delays
CMOS is ahead of the CPL adder. HPSC and NEW14T adders perform
poorly at low voltages Speed degrades significantly at higher loads
for TGA and TFA. CMOS shows the least speed degradation.
Slide 17
Simulation Results: Power The CPL adder dissipates the most
power TGA and TFA dissipate least power. The proposed full adder
and NEW-HPSC adder have the least power dissipation. TFA and TGA
show more degradation than others.
Slide 18
Simulation Results: Summary Simulation results for the proposed
full adder in 0.18m technology at 50-MHz frequency and 1.8V V
DD
Slide 19
4-operand CSA with final CPA.
Slide 20
Simulation Results for Four-Operand CSA As the number of bits
of the operands increase, the power dissipated in the CSA increases
proportionally. The adders without driving capability (TGA and TFA)
show the poorest performance
Slide 21
Conclusion Hybrid-CMOS design style gives flexibility for the
designer. The proposed hybrid-CMOS full adder performs well with
supply voltage scaling and under different load conditions
Hybrid-CMOS design style is recommended for the design of
high-performance circuits.
