Introduction to SRAM

Jasur Hanbaba

Outline

� Memory Arrays

� SRAM Architecture– SRAM Cell

– Decoders

– Column Circuitry

� Non-volatile Memory

� Manufacturing Flow

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Memory Arrays

Memory Arrays

Random Access Memory Serial Access Memory Content Addressable Memory

(CAM)

Read/Write Memory

(RAM)

(Volatile)

Read Only Memory

(ROM)

(Nonvolatile)

Static RAM

(SRAM)

Dynamic RAM

(DRAM)

Shift Registers Queues

First In

First Out

(FIFO)

Last In

First Out

(LIFO)

Serial In

Parallel Out

(SIPO)

Parallel In

Serial Out

(PISO)

Mask ROM Programmable

ROM

(PROM)

Erasable

Programmable

ROM

(EPROM)

Electrically

Erasable

Programmable

ROM

(EEPROM)

Flash ROM

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Memory Types:

�Volatile:–Random Access Memory (RAM):

• SRAM "static"

• DRAM "dynamic"

�Non-volatile:– Read Only Memory (ROM):

• Mask ROM "mask programmable"

• EPROM "electrically programmable"

• EEPROM "erasable electrically programmable"

• FLASH memory - similar to EEPROM with programmer integrated

on chip

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� Memory arrays often account for the majority of transistors

in modern microprocessor designs. So it is critical to have

a memory design that is efficient in terms of area and fast.

� SRAM (static random access memory) is the most widely

used in processor design.

–Simplicity: internal feedback loop that retain its value as long

as power is applied.

–Compatible with standard CMOS processes.

–Faster than DRAM.

Why is memory design important

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6T SRAM Cell

� Cell size accounts for most of array size

– Reduce cell size at expense of complexity

� 6T SRAM Cell

– Used in most commercial chips

– Data stored in cross-coupled inverters

� Read:

– Precharge bit, bit_b

– Raise wordline

� Write:

– Drive data onto bit, bit_b

– Raise wordline

bit bit_b

word

1-bit cell of the SRAM

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SRAM Read

� Precharge both bitlines high

� Then turn on wordline

� One of the two bitlines will be pulled down by the cell

� Ex: A = 0, A_b = 1

– bit discharges, bit_b stays high

– But A bumps up slightly

� Read stability

– A must not flip

bit bit_b

N1

N2P1

A

P2

N3

N4

A_b

word

0.0

0.5

1.0

1.5

0 100 200 300 400 500 600

time (ps)

word bit

A

A_b bit_b

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SRAM Write

� Drive one bitline high, the other low

� Then turn on wordline

� Bitlines overpower cell with new value

� Ex: A = 0, A_b = 1, bit = 1, bit_b = 0

– Force A_b low, then A rises high

� Writability

– Must overpower feedback inverter

– N2 >> P1

time (ps)

word

A

A_b

bit_b

0.0

0.5

1.0

1.5

0 100 200 300 400 500 600 700

bit bit_b

N1

N2P1

A

P2

N3

N4

A_b

word

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SRAM Column Example

Read Write

H H

S R A M C e ll

w o rd _ q 1

bit_

v1f

bit_

b_v1f

o u t_ v 1 ro u t_ b _ v 1 r

φ1

φ2

w o rd _ q 1

b it_ v 1 f

o u t_ v 1 r

φ2

M o re

C e lls

B it l in e C o n d it io n in g

φ2

More

Cells

SRAM Cell

word_q1bit_

v1f

bit_

b_v1f

data_s1

write_q1

Bitline Conditioning

SRAM Layout� Tile cells sharing VDD, GND, bitline contacts

VDD

GND GNDBIT BIT_B

WORD

Cell boundary

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Decoders� n:2n decoder consists of 2n n-input AND gates

– One needed for each row of memory

– Build AND from NAND or NOR gates

Static CMOS Pseudo-nMOS

word0

word1

word2

word3

A0A1

A1

word

A01 1

1/2

2

4

8

16word

A0

A1

1

1

11

4

8

word0

word1

word2

word3

A0A1

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Large Decoders

� For n > 4, NAND gates become slow

– Break large gates into multiple smaller gates

word0

word1

word2

word3

word15

A0A1A2A3

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Predecoding

� Many of these gates are redundant

– Factor out common

gates into predecoder

– Saves area

– Same path effort

A0

A1

A2

A3

word1

word2

word3

word15

word0

1 of 4 hot

predecoded lines

predecoders

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Column Circuitry

� Some circuitry is required for each column

– Bitline conditioning

– Sense amplifiers

– Column multiplexing

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Bitline Conditioning

� Precharge bitlines high before reads

� Equalize bitlines to minimize voltage difference when using sense

amplifiers

φ

bit bit_b

φ

bit bit_b

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Sense Amplifiers

� Bitlines have many cells attached

– Ex: 32-kbit SRAM has 256 rows x 128 cols

– 128 cells on each bitline

� tpd ∝ (C/I) ∆V

– Even with shared diffusion contacts, 64C of diffusion capacitance (big C)

– Discharged slowly through small transistors (small I)

� Sense amplifiers are triggered on small voltage swing (reduce ∆V)

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Differential Pair Amp

� Differential pair requires no clock

� But always dissipates static power

bit bit_b

sense_b sense

N1 N2

N3

P1 P2

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Clocked Sense Amp

� Clocked sense amp saves power

� Requires sense_clk after enough bitline swing

� Isolation transistors cut off large bitline capacitance

bit_bbit

sense sense_b

sense_clk isolation

transistors

regenerative

feedback

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Column Multiplexing

� 2n words of 2m bits each. If n >> m, fold by 2k into fewer rows of more

columns

� Ex: 2 kword x 16 folded into 256 rows x 128 columns

– Must select 16 output bits from the 128 columns

– Requires 16 8:1 column multiplexers

� Good regularity – easy to design

� Very high density if good cells are used

row

decoder

column

decoder

n

n-kk

2m bits

column

circuitry

bitline conditioning

memory cells:

2n-k rows x

2m+k columns

bitlines

wordlines

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Tree Decoder Mux

� Column mux can use pass transistors

– Use nMOS only, precharge outputs

� One design is to use k series transistors for 2k:1 mux

– No external decoder logic needed

B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7

A0

A0

A1

A1

A2

A2

Y Yto sense amps and write circuits

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Single Pass-Gate Mux

� Or eliminate series transistors with separate decoder

A0A1

B0 B1 B2 B3

Y

SRAM Layout

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Non-volatile Memory

� Mask ROM

– Used with logic circuits for tables etc.

– Contents fixed at IC fab time (truly write once!)

� EPROM (erasable programmable)

& FLASH

– requires special IC process

(floating gate technology)

– writing is slower than RAM. EPROM uses special programming system to provide

special voltages and timing.

– reading can be made fairly fast.

– rewriting is very slow.

• erasure is first required , EPROM - UV light exposure, EEPROM – electrically

erasable

Used to hold fixed code (ex. BIOS), tables of data (ex. FSM next state/output

logic), slowly changing values that persist over power off (date/time)

Manufacturing Flow

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Wafer fab E-Test Sort Assembly Burn-inClass

Structural FunctionalPPV Customer

The The ““front endfront end”” = wafer fab, E= wafer fab, E--test, and sort. Etest, and sort. E--test and sort are also test and sort are also

called called ““wafer testwafer test””..

In assembly, wafers are cut into dice and the dice are assembledIn assembly, wafers are cut into dice and the dice are assembled into into

packages.packages.

The The ““back endback end”” = assembly, burn= assembly, burn--in, class test and PPV.in, class test and PPV.

““FrontFront

endend””““Back Back

endend””