Introduction to Chapter 7 - Computer Engineeringjgallaher/download/ETEM212/Chapter7-Coun… · Introduction to Chapter 7 ... frequency divided by the MOD of the counter. 7-1 Asynchronous

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Introduction to Chapter 7

• FFs and logic gates will be combined to form various counters and registers.

• Part 1 will cover counter principles, various counter circuits, and IC counters.

• Part 2 will cover several types of IC registers and shift register counter troubleshooting.

• It may be necessary to review previous information to fully understand the information presented.

Ronald Tocci/Neal Widmer/Gregory MossDigital Systems: Principles and Applications, 9e

Copyright ©2004 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458

All rights reserved.

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7-1 Asynchronous (Ripple) Counters

• Review of four bit counter operation (refer to figure 7-1 See next page.)– Clock is applied only to FF A. J and K are high

in all FFs.– Output of FF A is CLK of FF B and so forth.– FF outputs D, C, B, and A are a 4 bit binary

number with D as the MSB.– After the NT (negative transition) of the 15th

clock pulse the counter recycles to 0000.




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• This is an asynchronous counter because state is not changed in exact synchronism with the clock.

• Schematics are normally drawn from left to right, but counters will be drawn from right to left so that the MSB and LSB appear in the appropriate positions.

• MOD number is equal to the number of states that the counter goes through before recycling. Adding FFs will increase the MOD number.




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• Frequency division – each FF will have an output frequency of ½ the input. The output frequency of the last FF of any counter will be the clock frequency divided by the MOD of the counter.


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7-2 Counters with MOD Number <2N

• The MOD of a counter can be changed by designing the counter to normal parts of the counting sequence.

• Refer to figure 7-4 on the next page. When outputs B and C are high the counter will be reset.

• Notice the “glitch” in the waveform when the count reaches 6. This represents the brief time required to reset the counter.




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• Displaying counter states – The arrangement below will result in an LED on when the output is high.




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• Changing the MOD number.– Find the smallest MOD required so that 2N is less than

or equal to the requirement.– Connect a NAND gate to the asynchronous CLEAR

inputs of all FFs.– Determine which FFs are HIGH at the desired count

and connect the outputs of these FFs to the NAND gate inputs.




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• Decade counters/BCD counters– A decade counter is any counter with 10

distinct states, regardless of the sequence. Any MOD-10 counter is a decade counter.

– A BCD counter is a decade counter that counts from binary 0000 to 1001.

• Decade counters are widely used for counting events and displaying results in decimal form.




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7-3 IC Asynchronous Counters




• TTL 74LS293– 4 JK FFs– Each FF has NGT CP input– Each FF has active low

asynchronous CLEAR inputs.

– FFs Q1, Q2, and Q3 are connected as a 3 bit ripple counter. Q0 is not connected internally, which allows flexibility in design.

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7-3 IC Asynchronous Counters• IEEE/ANSI symbol for a 74LS293 counter

– Common control block– Divide by 2 block– Divide by 8 block




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7-3 IC Asynchronous Counters• 74HC4024 CMOS asynchronous counter

– Does not have a TTL counterpart– Seven bit counter– One asynchronous active high MR– All seven FFs are connected internally to form a MOD

128 ripple counter




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7-4 Asynchronous Down Counter• Counting down rather than up simply requires

cascading the clocks using the inverted outputs.• Figure 7-15 illustrates the connection for a down

counter.




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7-5 Propagation Delay in Ripple Counters




• Ripple counters are simple, but the cumulative propagation delay can cause problems at high frequencies.

• For proper operation the following apply:– Tclock≥N x tpd

– Fmax=1/N x tpd

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7-6 Synchronous (Parallel) Counters

• All FFs are triggered by CPs simultaneously• Figure 7-17 on the next page illustrates operation

of a synchronous counter.• Each FF has J and K inputs connected so they are

HIGH only when the outputs of all lower-order FFs are HIGH.

• The total propagation delay will be the same for any number of FFs.

• Synchronous counters can operate at much higher frequencies than asynchronous counters.




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7-6 Synchronous (Parallel) Counters

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7-7 Synchronous Down and Up/Down Counters

• The synchronous counter can be converted to a down counter by using the inverted FF outputs to drive the JK inputs.

• A synchronous counter can be made an up/down counter by connecting as illustrated in figure 7-18 on the next page.




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7-7 Synchronous Down and Up/Down Counters

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7-8 Presettable Counters

• A presettable counter can be set to any desired starting point either asynchronously or synchronously.

• The preset operation is also called parallel loading the counter.

• Figure 7-19 on the next page illustrates an asynchronous preset.

• There are several TTL and CMOS devices that provide both synchronous and asynchronous presetting.




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7-8 Presettable Counters

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7-9 The 74ALS193/HC193

• Refer to figure 7-20 on the next page– MOD-16– Presettable up/down counter– Synchronous counting– Asynchronous preset– Asynchronous master reset

• Function of inputs and output




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7-9 The 74ALS193/HC193

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7-9 The 74ALS193/HC193

• Variable MOD using the 74ALS193/HC193– Variable frequency division can be done by

manipulating the levels on the parallel data inputs.

• Multistage arrangement– Figure 7-25 describes a 2 stage arrangement

that provides a range of 0-255. See next page.




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7-9 The 74ALS193/HC193

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7-10 More on the IEEE/ANSI Dependency Notation

• Control dependency (C)26• Counting direction (+ or -)• AND dependency (G)




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7-11 Decoding a Counter

• Decoding is the conversion of a binary output to a decimal value.

• The active high decoder shown in figure 7-27 could be used to light an LED representing each decimal number 0 to 7

• Active low decoding is obtained by replacing the AND gates with NAND gates.




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7-11 Decoding a Counter

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7-12 Decoding Glitches

• Glitches are caused by delays between FF transitions.

• Figure 7-30 on the next page describes the problem.

• The spikes may not cause problems in many applications due to the short duration.

• If glitches cannot be tolerated a parallel counter can be used.

• Strobing uses a strobe signal to keep decoding AND gates disabled until all FFs have reached a stable state. Refer to figure 7-31 after next page.




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7-13 Cascading BCD Counters

• Operation of a decimal 000 to 999 BCD counter (refer to figure 7-32 on next page)– Initially all counters are reset to 0– Each input pulse advances the first counter once.– The 10th input pulse causes the counter to recycle,

which advances the second counter 1.– This continues until the second counter (10’s digit)

recycles, which advances the third counter 1.– The cycle repeat until 999 is reached and all three

counters start again at zero.




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7-13 Cascading BCD Counters

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7-14 Synchronous Counter Design

• Determine desired number of bits and desired counting sequence

• Draw the state transition diagram showing all possible states

• Use the diagram to create a table listing all PRESENT states and their NEXT states

• Add a column for each JK input. Indicate the level required at each J and K in order to produce transition to the NEXT state.

• Design the logic circuits to generate levels required at each JK input.

• Implement the final expressions




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7-15 Basic Counters Using HDL

• Overview• Synchronous counter design with D FF• State Transition Description Methods• State descriptions in AHDL• State descriptions in VHDL• Behavioral Descriptions

– AHDL– VHDL




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7-16 Full Featured Counters in HDL

• Overview– How to make it count up and down– How to clear it asynchronously– How to load it synchronously– How to include synchronous cascade controls

• AHDL full-featured counter• VHDL full-featured counter




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7-17 LPM Counters

• An LPM can be used to create a counter of any width and modulus. The Altera library controls allow counting up or down, synchronous parallel loads asynchronous clear and synchronous cascading.

• AHDL• VHDL




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7-18 State Machines

• Counter circuits used to generate a sequence of states without regard to their binary value are often called state machines. The washing machine states of idle, fill, agitate, and spin will be used in the examples.– AHDL state machines– VHDL state machines

• Each method of describing logic circuits has advantages.




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7-19 Integrated-Circuit Registers

• Registers can be classified by the way data is entered for storage, and by the way data is outputted from the register.– Parallel in/parallel out (PIPO)– Serial in/serial out (SISO)– Parallel in/serial out (PISO)– Serial in/parallel out (SIPO)




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7-20 PIPO – The 74ALS174/74HC174

• Refer to figure 7-52 on the next page.• Six bit register• Parallel inputs D5 through D0• Parallel outputs Q5 through Q0• Parallel data loaded to the register on the

PGT of CP• Master reset can reset all FFs

asynchronously




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7-20 PIPO – The 74ALS174/74HC174

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7-21 SISO – The 4731B

• Refer to figure 7-54 on the next page• 4 64 bit shift registers on one chip• Serial input DS

• Clock input responds to NGT• Serial output Q63

• A buffer is used for greater output current• No means for parallel data entry into register FFs




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7-21 SISO – The 4731B

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7-22 PISO – The 74ALS165/74HC165

• Refer to figure 7-56 on the next page• 8 bit register• Serial data entry via DS• Asynchronous parallel data entry P0 through P7• FFs Q0 through Q7• Only the outputs of Q7 are accessible• CP is clock input for shifting• Clock inhibit input• Shift load input




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7-22 PISO – The 74ALS165/74HC165

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7-23 SIPO – The 74ALS164/74HC164

• Refer to figure 7-57 on the next page• 8 bit shift register• Each FF output is externally accessible• A and B inputs are combined in an AND

gate for serial input.• Shift occurs on PGT of the clock input.




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7-22 PISO – The 74ALS165/74HC165

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7-23 SIPO – The 74ALS164/74HC164

• Other similar devices– 74194/ASL194/HC194

• 4 bit bi-directional universal shift register• Performs shift left, shift right, parallel in and parallel out.

– 74373/ALS373/HC373/HCT373• 8 bit PIPO with 8 D latches• Tristate outputs

– 74374/ALS374/HC374• 8 bit PIPO with 8 edge triggered D FFs• Tristate outputs




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7-24 IEEE/ANSI Register Symbols

• Two examples




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7-25 Shift Register Counters

• Ring Counter– Refer to figure 7-60 on the next page– Last FF shifts its value to first FF– Uses D FFs– JK FFs can also be used– Must start with only one FF in the 1 state and

all others in the 0 state.




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• Johnson counter– Refer to figure 7-62 on the next page– Also called a twisted ring counter– Same as ring counter but the inverted output of

the last FF is connected to input of the first FF




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7-26 Troubleshooting

• Sequential logic systems are more complex, but basic troubleshooting procedures still apply.– Observe system operation– Use analytical reasoning to determine possible

causes– Use test equipment to isolate the exact fault




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7-27 HDL Registers

• Using bit arrays to describe register data– Example 7-26 involves the design of a

universal 4 bit shit register. Requirements are:• 4 synchronous modes of operation: hold, shift left,

shift right, and parallel load• 2 input bits select operation to be performed on PGT

of the clock– AHDL solution– VHDL solution




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7-28 HDL Ring Counters

• Recall that a ring counter is a shift register that circulates a single active logic level through all its FFs.– AHDL solution (figure 7-71)– VHDL solution (figure 7-72)




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7-29 HDL One-Shots

• Non-retriggerable, level sensitive one-shot– AHDL solution– VHDL solution

• Retriggerable edge-triggered one-shot– AHDL solution– VHDL solution




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Introduction to Chapter 7 - Computer Engineeringjgallaher/download/ETEM212/Chapter7-Coun… · Introduction to Chapter 7 ... frequency divided by the MOD of the counter. 7-1 Asynchronous