Introduction to 8086 Assembly Language Programming

Introduction to 8086 Assembly Language Programming

Prepared by: Prof. Ajaykumar T. Shah

Blog: aforajayshahnirma.wordpress.com

Program Statements

name operation operand(s) comment

• Operation is a predefined or reserved word› mnemonic - symbolic operation code› directive - pseudo-operation code

• Space or tab separates initial fields

• Comments begin with semicolon

• Most assemblers are not case sensitive


8086 Instruction - Example Label Operator Operand[s] ;Comment

INIT: mov ax, bx ; Copy contents of bx into ax

Label - INIT:Operator - movOperands - ax and bxComment - alphanumeric string between ; and \n

• Not case sensitive• Unlike other assemblers, destination operand is first• mov is the mnemonic that the assembler translates into an

opcode


Program Data and Storage Allocation directive

• Pseudo-ops to define data or reserve storage› DB - byte(s)

› DW - word(s)

› DD - doubleword(s)

› DQ - quadword(s)

› DT - tenbyte(s)

• These directives require one or more operands› define memory

contents

› specify amount of storage to reserve for run-time data


Defining Data

• Numeric data values› 100 - decimal

› 100B - binary

› 100H - hexadecimal

› '100' - ASCII

› "100" - ASCII

• Use the appropriate DEFINE directive (byte, word, etc.)

• A list of values may be used - the following creates 4 consecutive wordsDW 40CH,10B,-13,0

• A ? represents an uninitialized storage locationDB 255,?,-128,'X'


Naming Storage Locations

• Names can be associated with storage locationsANum DB -4 DW 17ONEUNO DW 1X DD ?

• These names are called variables

• ANum refers to a byte storage location, initialized to FCh

• The next word has no associated name

• ONE and UNO refer to the same word

• X is an unitialized doubleword


Arrays

• Any consecutive storage locations of the same size can be called an arrayX DW 40CH,10B,-13,0

Y DB 'This is an array'

Z DD -109236, FFFFFFFFH, -1, 100B• Components of X are at X, X+2, X+4, X+8• Components of Y are at Y, Y+1, …, Y+15• Components of Z are at Z, Z+4, Z+8, Z+12


DUP

• Allows a sequence of storage locations to be defined or reserved

• Only used as an operand of a define directive

DB 40 DUP (?)

DW 10h DUP (0)

DB 3 dup ("ABC")

db 4 dup(3 dup (0,1), 2 dup('$'))Blog:

aforajayshahnirma.wordpress.com

Word Storage

• Word, doubleword, and quadword data are stored in reverse byte order (in memory)

Directive Bytes in Storage

DW 256 00 01

DD 1234567H 67 45 23 01

DQ 10 0A 00 00 00 00 00 00 00

X DW 35DAh DA 35Low byte of X is at X, high byte of X is at X+1


Named Constants

• Symbolic names associated with storage locations represent addresses

• Named constants are symbols created to represent specific values determined by an expression

• Named constants can be numeric or string• Some named constants can be redefined• No storage is allocated for these values


Program Skeleton

.model small

.stack 100H

.data ;declarations.codemain proc ;codemain endp ;other procsend main

• Select a memory model• Define the stack size• Declare variables• Write code

› organize into procedures

• Mark the end of the source file› optionally, define the

entry point


SEGMENT and ENDS Directives

• a logical segment is a group of instruction statements or data statements contained between SEGMENT and ENDS directives› similar to the block concept in C++

DATA_HERE SEGMENT

DATA_HERE ENDS


Program Segment Structure

• Data Segments› Storage for variables

› Variable addresses are computed as offsets from start of this segment

• Code Segment› contains executable

instructions

• Stack Segment› used to set aside

storage for the stack

› Stack addresses are computed as offsets into this segment

• Segment directives.data

.code

.stack size

Used to indicate the beginning of logical segment.


Other Directives• ASSUME

› tells the assembler which logical segment to use for each physical segment

• remember that just because I named my data segment DATA_HERE, doesn’t tell the assembler that that’s my data segment!

ASSUME DS:DATA_HERE, CS:CODE_HERE

› segment registers other than the code segment must still be initialized mov ax, DATA_HERE mov ds, ax

Segment value is not directly loaded into segment register bcoz of mov instruction limitation.


GROUP

• Informs the assembler to group the logical statement named in the directive into one logical group statement.

• Linker is informed to link all grouped segments into single segment.

• Groupname GROUP: Seg name1,….,SegnameN

• Example:

Small_model GROUP _code,_data,_stack,_extra

ASSUME cs:Small_model, ds:Small_model, ss:Smallmodel


MASM Directives• .TITLE

› give the title of the program

• .DOSSEG› use the MSDOS segment order

• .MODEL small› use a small memory model

• .8086› 8086/88 instructions only

• .STACK 0100h› start stack segment and specify size

• .DATA› start data segment

• .CODE› start code segment

• END› tells the assembler to STOP reading…any instructions after this will be ignored

› an optional label/address tells the assembler what to use as the program entry pointBlog: aforajayshahnirma.wordpress.com

DOS INT 21H instruction

• int 21h ; interrupt program execution • 21h specifies that this is a DOS interrupt

› value contained in ax can determine behavior of interrupt

mov ah, 9 ;specify print to stdout

mov dx, offset greeting

;specify what to print in dx

int 21h

mov ax, 4c00h ;return to DOS

int 21h


Masking• Masking a bit

› if we AND a bit with 0, the result is always 0• we have hidden(masked) the previous state of the bit

• Masking a nibble› the smallest data we can AND is a byte

• if we AND a bit with a 1, we have no effect on the bit• to mask the high nibble

AND AL, 0FH ; AND AL with

; 00001111 to mask upper nibble

• For the BCD Packing algorithm, we can also use a SHL

- the source operand can be either CL or 1

- the destination operand can be either a register or memory


Value returning directive

• SIZE

SIZE variable name, Returns no. of bytes

Name DB/DW 50 DUP(?) ;BX=100

Exa: Mov Ax, SIZE Name

• LENGTH

Same as SIZE, Returns no. of element

Name DB/DW 50 DUP(?) :BX=50

Exa: Mov Ax, LENGTH Name

• OFFSET

To determine displacement of specified variable wrt base of segment.


Equal Sign Directive

• name = expression› expression must be numeric

› these symbols may be redefined at any timemaxint = 7FFFhcount = 1DW countcount = count * 2DW count


EQU Directive

• name EQU expression› expression can be string or numeric

› Use < and > to specify a string EQU

› these symbols cannot be redefined later in the programExample:

sample EQU 7Fh

aString EQU <1.234>

message EQU <This is a message>

Mov AX, sample


Types of Assembly Instructions• Data Transfer

› MOV, LEA, PUSH, POP, IN, OUT

• Arithmetic› ADD, SUB, MUL, DIV

• Bit Manipulation› NOT, AND, OR, ROL, SHR

• String Instructions› LODS, STOS, INS


• Program Execution› LOOP, JNS, CALL, RET, JMP

• Processor Control› HLT, NOP, STI

• Interrupt Control


1] MOV dest, srcNote that source and destination cannot be memory location. Also source and destination must be same type.2] PUSH Src: Copies word on stack.3] POP dest: Copies word from stack into dest. Reg.4]IN acc, port : Copies 8 or 16 bit data from port to accumulator. 5] OUT port, acc 6] LES Reg, Mem: Load register and extra segment register with words from memory.7] LDS Reg, Mem: Load register and data segment register with words from memory.8] LEA Reg, Src: load Effective address.(Offset is loaded in specified register)9] LAHF: Copy lower byte of flag register into AH register.10] SAHF: Copy AH register to lower byte of flag register.11] XCHG dest, src: Exchange contains of source and destination.12] XLAT: Translate a byte in AL.This instruction replaces the byte in AL with byte pointed by BX.To point desired byte in look up table instruction adds contains of BX with AL ( BX+ AL). Goes to this location and loads into AL.

Data Transfer Instructions


Mnemonic Meaning Format Operation Flags affected

MOV Move Mov D,S (S) (D) None

Data Transfer Instructions - MOVData Transfer Instructions - MOV

Destination Source

Memory Accumulator

Accumulator Memory

Register Register

Register Memory

Memory Register

Register Immediate

Memory Immediate

Seg reg Reg 16

Seg reg Mem 16

Reg 16 Seg reg

Memory Seg reg

NO MOV

MemoryImmediateSegment Register

MemorySegment RegisterSegment Register

EX: MOV AL, BLBlog:


Data Transfer Instructions - XCHGData Transfer Instructions - XCHG


XCHG Exchange XCHG D,S (S) (D) None

Destination Source

Accumulator Reg 16

Memory Register

Register Register

Register Memory

Example: XCHG [1234h], BX

NO XCHG MEMsSEG REGs


Data Transfer Instructions – LEA, LDS, LES

Mnemonic

Meaning Format Operation Flags affecte

d

LEA Load Effective Address

LEA Reg16,EA EA (Reg16) None

LDS Load Register And DS

LDS Reg16,MEM16

(MEM16) (Reg16)

(Mem16+2) (DS)

None

LES Load Register and ES

LES Reg16,MEM16

(MEM16) (Reg16)

(Mem16+2) (DS)

None

• LEA BX,AMOUNT LEA AX,[BX][DI]

• LDS/LES SI,STR_PTR LDS/LES BX,[5300H]Blog: aforajayshahnirma.wordpress.com

The XLAT InstructionThe XLAT InstructionMnemonic Meaning Format Operation Flags

XLAT Translate XLAT ((AL)+(BX)+(DS)0) (AL) None

Example: Assume (DS) = 0300H, (BX)=0100H, and (AL)=0DHXLAT replaces contents of AL by contents of memory location with PA=(DS)0 +(BX) +(AL) = 03000H + 0100H + 0DH = 0310DHThus(0310DH) (AL)

Replaces a byte in the AL register with a byte from the look up table. Before execution , BX should be loaded with offset address of lookup table in DS and AL.


Example of XLAT

Hex_table DB ‘0123456789ABCDEF’

CODE DB 12

;conversion of code in decimal to hexadecimal

Mov AL,CODE

Mov BX,OFFSET Hex_table

XLAT

;The value in AL is 0CH


Mnemonic Meaning Format Operation Flags Affected

AND

OR

XOR

NOT

Logical AND

Logical Inclusive OR

Logical Exclusive OR

LOGICAL NOT

AND D,S

OR D,S

XOR D,S

NOT D

(S) · (D) → (D)

(S)+(D) → (D)

(S) (D)→(D)

_ (D) → (D)

OF, SF, ZF, PF, CF

AF undefinedOF, SF, ZF, PF,

CFAF undefined

OF, SF, ZF, PF, CF

AF undefinedNone

+

Logical Instructions

Destination Source

RegisterRegisterMemoryRegisterMemory

Accumulator

RegisterMemoryRegister

ImmediateImmediateImmediate

Destination

Register Memory


LOGICAL Instructions

• AND– Uses any addressing mode except memory-to-memory and

segment registers– Especially used in clearing certain bits (masking) xxxx xxxx AND 0000 1111 = 0000 xxxx

(clear the first four bits)– Examples: AND BL, 0FH

AND AL, [345H]

• OR– Used in setting certain bits

xxxx xxxx OR 0000 1111 = xxxx 1111(Set the upper four bits)


• XOR– Used in Inverting bits

xxxx xxxx XOR 0000 1111 = xxxxx’x’x’x’

-Example: Clear bits 0 and 1, set bits 6 and 7, invert bit 5 of register CL:

AND CL, OFCH ; 1111 1100B

OR CL, 0C0H ; 1100 0000B

XOR CL, 020H ; 0010 0000B


Arithmetic instruction1] AAA : ASCII adjust after addition.We can add two ASCII numbers directly and use AAA after addition so as to get result directly in BCD. (Works with AL only)2] DAA : Decimal adjust accumulator. ( Works with AL only)3] AAS: ASCII adjust for subtraction ( Same as AAA and works with AL only)4] DAS : Decimal adjust after Subtraction. ( Works with AL only)5] MUL src6 ] IMUL src: Multiplication of signed byte.7] AAM: BCD adjust after multiply. ( Works with AL only)8]DIV src If any one attempts to divide by 0 , then ?9] IDIV: Division of signed numbers10]AAD: BCD to Binary convert before Division.11] CWD: Convert signed word to signed double word.12] CBW : Convert signed byte to signed word.( CBW and CWD works only with AL,AX and DX registers.)


Arithmetic Instructions: ADD, ADC, INC, AAA, DAA


ADD Addition ADD D,S (S)+(D) (D)

carry (CF)

ALL

ADC Add with carry

ADC D,S (S)+(D)+(CF) (D)

carry (CF)

ALL

INC Increment by one

INC D (D)+1 (D) ALL but CY

AAA ASCII adjust for addition

AAA If the sum is >9, AH

is incremented by 1

AF,CF

DAA Decimal adjust for addition

DAA Adjust AL for decimalPacked BCD

ALL


Examples:

Ex.1 ADD AX,2 ADC AX,2 Ex.2 INC BX INC WORD PTR [BX]

Ex.3 ASCII CODE 0-9 = 30-39h

MOV AX,38H ; (ASCII code for number 8) ADD AL,39H ; (ASCII code for number 9) AL=71h AAA ; used for addition AH=01, AL=07 ADD AX,3030H ; answer to ASCII 0107 AX=3137Ex.4 AL contains 25 (packed

BCD) BL contains 56 (packed

BCD)

ADD AL, BL DAA

25+ 56

--------7B 81


Arithmetic Instructions – SUB, SBB, DEC, AAS, DAS, NEG


SUB Subtract SUB D,S (D) - (S) (D) Borrow (CF)

All

SBB Subtract with

borrow

SBB D,S (D) - (S) - (CF) (D)

All

DEC Decrement by one

DEC D (D) - 1 (D) All but CF

NEG Negate NEG D All

DAS Decimal adjust for

subtraction

DAS Convert the result in AL to packed decimal format

All

AAS ASCII adjust for

subtraction

AAS (AL) difference

(AH) dec by 1 if borrow

CY,AC


Examples: DAS

MOV BL, 28H

MOV AL, 83H

SUB AL,BL ; AL=5BH

DAS ; adjust as AL=55H

MOV AX, 38H

SUB AL,39H; AX=00FF

AAS ; AX=FF09 ten’s complement of -1 (Borrow one from AH )

OR AL,30H ; AL=39


Multiplication and Division


Multiplication(MUL or IMUL)

Multiplicand Operand(Multiplier)

Result

Byte*Byte AL Register or memory AX

Word*Word AX Register or memory DX :AX

Dword*Dword EAX Register or memory EAX :EDX

Division (DIV or IDIV)

Dividend Operand (Divisor)

Quotient: Remainder

Word/Byte AX Register or Memory AL : AH

Dword/Word DX:AX Register or Memory AX : DX

Qword/Dword EDX: EAX Register or Memory EAX : EDX

Multiplication and Division


Multiplication and Division Examples

Ex1: Assume that each instruction starts from these values:AL = 85H, BL = 35H, AH = 0H

1. MUL BL → AL . BL = 85H * 35H = 1B89H → AX = 1B89H 2. IMUL BL → AL . BL = 2’S AL * BL = 2’S (85H) * 35H = 7BH * 35H = 1977H→ 2’s comp → E689H → AX.

• DIV BL → = = 02 (85-02*35=1B) →

4. IDIV BL → = =

1BH

H

35

008502

AH AL

BL

AX

BL

AX

H

H

35

00851B 02

AH AL


Ex2: AL = F3H, BL = 91H, AH = 00H

1. MUL BL → AL * BL = F3H * 91H = 89A3H → AX = 89A3H

2. IMUL BL → AL * BL = 2’S AL * 2’S BL = 2’S (F3H) * 2’S(91H) = 0DH * 6FH = 05A3H → AX.

3.IDIV BL → = = = 2→ (00F3 – 2*6F=15H)BL

AX

)91('2

300

HS

HF

FH

HF

6

300

AH AL15 02 R Q

NEGNEG

POS → 2’s(02) = FEH→

AH AL

15 FE→

4. DIV BL → = = 01→(F3-1*91=62) → BL

AXH

HF

91

300

AH AL62 01 R Q


Ex3: AX= F000H, BX= 9015H, DX= 0000H

1. MUL BX = F000H * 9015H =

DX AX

8713 B000

2. IMUL BX = 2’S(F000H) * 2’S(9015H) = 1000 * 6FEB =

DX AX06FE B000

3. DIV BL = = B6DH → More than FFH → Divide Error. H

HF

15

000

4. IDIV BL → = = C3H > 7F → Divide Error. H

HFS

15

)000('2

H

H

15

1000


Ex4: AX= 1250H, BL= 90H

1. IDIV BL → = = = = = BL

AX

H

H

90

1250

NEG

POS

sNEG

POS

'2 )90('2

1250

Hs

HH

H

70

1250

= 29H (Q) → (1250 – 29 * 70) = 60H (REM)

29H ( POS) → 2’S (29H) = D7H → R Q

60H D7H

2. DIV BL → = = 20H→1250-20*90 =50H → BL

AXH

H

90

1250

R Q50H 20H AH AL


• Used to define subroutines, offers modular programming.• Call to procedure will be a transfer of control to called procedure

during run time.

PROC: indicates beginning of procedure.

Procedure type helps assembler to decide weather to code return as near/far.

Near/Far term follows PROC indicates type of procedure.[Near by default]

ENDP: indicates assembler the end of procedureExample: Procedure Name PROC

…

;do procedure code stuuff

…

RET

Procedure Name ENDP

Procedure definition directive


• Used to define macro constants.

• Call to macro will be replaced by its body during assembly time.

• EQU: macro symbol

• MACRO: informs assembler the beginning of macro. It is a open subroutines. It gets expanded when call is made to it.

• MacroName MACRO [arg1,arg2…argn]

• Advantage: save great amount of effort and time by avoiding overhead of writing repeated pattern of code.

• ENDM: informs assembler the end of macro.

MACRO definition directive



Processor control instruction1] CLC: Clear Carry flag. To check whether call is successful or not.2] STC :Set carry Flag3] CMC :Complement Carry Flag4] CLD: Clear Direction Flag. SI & DI will be automatically incremented to point to next element of instruction.5] STD: Set Direction Flag Auto decrement mode6] CLI :Clear Interrupt Flag. Disable maskable hardware interrupt7] STI : Set Interrupt Flag.8] HLT: Halt Processing.9] NOP : No Operation10] ESC: EscapeExecuted by Co-processors and actions are performed according to 6 bit coding in the instruction.11] LOCK : Assert bus lock SignalThis is prefix instruction.12] WAIT :Wait for test or Interrupt Signal.Assert wait states. Blog:


HLT instruction – HALT processingthe HLT instruction will cause the 8086 to stop fetching and executing

instructions. The 8086 will enter a halt state. The only way to get the processor out of the halt state are with an interrupt signal on the INTR pin or an interrupt signal on NMI pin or a reset signal on the RESET input.

NOP instructionthis instruction simply takes up three clock cycles and does no processing.

After this, it will execute the next instruction. This instruction is normally used to provide delays in between instructions.

ESC instructionwhenever this instruction executes, the microprocessor does NOP or access a

data from memory for coprocessor. This instruction passes the information to 8087 math processor. Six bits of ESC instruction provide the opcode to coprocessor.

when 8086 fetches instruction bytes, co-processor also picks up these bytes and puts in its queue. The co-processor will treat normal 8086 instructions as NOP. Floating point instructions are executed by 8087 and during this 8086 will be in WAIT.


LOCK instructionthis is a prefix to an instruction. This prefix makes sure that during

execution of the instruction, control of system bus is not taken by other microprocessor.

in multiprocessor systems, individual microprocessors are connected together by a system bus. This is to share the common resources. Each processor will take control of this bus only when it needs to use common resource.

the lock prefix will ensure that in the middle of an instruction, system bus is not taken by other processors. This is achieved by hardware signal ‘LOCK’ available on one of the CPU pin. This signal will be made active during this instruction and it is used by the bus control logic to prevent others from taking the bus.

once this instruction is completed, lock signal becomes inactive and microprocessors can take the system bus.

WAIT instructionthis instruction takes 8086 to an idle condition. The CPU will not do any

processing during this. It will continue to be in idle state until TEST pin of 8086 becomes low or an interrupt signal is received on INTR or NMI. On valid interrupt, ISR is executed and processor enters the idle state again.


Jumps• Unconditional

› always jumps to the specified jump destination

• Conditional › need to look at the register to evaluate the state

of particular flags• the instruction specifies which flags to look at

• this determines whether to fetch the next instruction from the jump destination or from the next sequential memory location


JMP - unconditional jump• Near vs. far

› near: if the jump destination is in the same code segment…intrasegment

› far: if the jump destination is in a different code segment…intersegment

• direct vs. indirect› direct: if the jump destination address is

specified directly in the instruction › indirect: if the jump destination address is

contained in a register or memory


Unconditional JumpUnconditional Jump

Part 1

JMP AAUnconditional JMPSkipped part

Part 3

AA XXXX

Part 2

Next instruction

Control flow and JUMP instructionsControl flow and JUMP instructions

JMP unconditional jump

JMP Operand


Unconditional JumpUnconditional Jump

Unconditional Jump Instruction

Near Jump or Far Jump or

Intra segment Jump Inter segment Jump

(Jump within the segment) (Jump to a different segment)

Is limited to the address with in the current segment. It is achieved by modifying value in IP

Permits jumps from one code segment to another. It is achieved by modifying CS and IP OperandsOperands

Short label

Near label

Far label

Memptr16

Regptr16

memptr32

Inter Segment Jump

Inter Segment JumpBlog:


Conditional JumpConditional Jump

Part 1

Jcc AA Conditional Jump

Skipped part

Part 2

XXXX

Part 3

AA XXXX

condition

YES

NO

Next instruction


Conditional Jump instructionsConditional Jump instructions

Conditional Jump instructions in 8086 are just 2 bytes long. 1-byte opcode followed by 1-byte signed displacement (range of –128 to +127).

Conditional Jump Instructions

Jumps based on

a single flag

Jumps based on

more than one flag


Conditional Jump InstructionsConditional Jump Instructions

Mnemonic : Jcc

Meaning : Conditional Jump

Format : Jcc operand

Operation : If condition is true jump to the address specified by operand. Otherwise the next instruction is executed.

Flags affected : None


Mnemonic meaning condition

JA Above CF=0 and ZF=0

JAE Above or Equal CF=0

JB Below CF=1

JBE Below or Equal CF=1 or ZF=1

JC Carry CF=1

JCXZ CX register is Zero (CF or ZF)=0

JE Equal ZF=1

JG Greater ZF=0 and SF=OF

JGE Greater or Equal SF=OF

JL Less (SF XOR OF) = 1

TYPESTYPES



JLE Less or Equal ((SF XOR OF) or ZF) = 1

JNA Not Above CF =1 or Zf=1

JNAE Not Above nor Equal CF = 1

JNB Not Below CF = 0

JNBE Not Below nor Equal CF = 0 and ZF = 0

JNC Not Carry CF = 0

JNE Not Equal ZF = 0

JNG Not Greater ((SF XOR OF) or ZF)=1

JNGE Not Greater nor Equal

(SF XOR OF) = 1

JNL Not Less SF = OF



JNLE Not Less nor Equal ZF = 0 and SF = OF

JNO Not Overflow OF = 0

JNP Not Parity PF = 0

JNZ Not Zero ZF = 0

JNS Not Sign SF = 0

JO Overflow OF = 1

JP Parity PF = 1

JPE Parity Even PF = 1

JPO Parity Odd PF = 0

JS Sign SF = 1

JZ Zero ZF = 1


Jumps Based on a single flagJumps Based on a single flag

JZ r8 ;Jump if zero flag set to 1 (Jump if result is zero)

JNZ r8 ;Jump if Not Zero (Z flag = 0 i.e. result is nonzero)

JS r8 ;Jump if Sign flag set to 1 (result is negative)

JNS r8 ;Jump if Not Sign (result is positive)

JC r8 ;Jump if Carry flag set to 1

JNC r8 ;Jump if No Carry

JP r8 ;Jump if Parity flag set to 1 (Parity is even)

JNP r8 ;Jump if No Parity (Parity is odd)

JO r8 ;Jump if Overflow flag set to 1 (result is wrong)

JNO r8 ;Jump if No Overflow (result is correct)

There is no jump based on AC flag


JZ r8 ; JE (Jump if Equal) also means same.

JNZ r8 ; JNE (Jump if Not Equal) also means same.

JC r8 ;JB (Jump if below) and JNAE (Jump if Not Above or Equal) also mean same.

JNC r8 ;JAE (Jump if Above or Equal) and JNB (Jump if Not Above) also mean same.

JZ, JNZ, JC and JNC used after arithmetic operation

JE, JNE, JB, JNAE, JAE and JNB are used after a compare operation.

JP r8 ; JPE (Jump if Parity Even) also means same.

JNP r8 ; JPO (Jump if Parity Odd) also means same.


Examples for JE or JZ instruction

Ex. for forward jump (Only examples for JE given)

CMP SI, DI

JE SAME

Should be <=127 bytes

ADD CX, DX ;Executed if Z = 0

: (if SI not equal to DI)

:

SAME: SUB BX, AX ;Executed if Z = 1

(if SI = DI)


Examples for JE or JZ instruction

Ex. for backward jump

BACK: SUB BX, AX ; executed if Z = 1

Should be

<= 128 bytes

: (if SI = DI)

:

CMP SI, DI

JE BACK

ADD CX, DX ;executed if Z = 0

(if SI not equal to DI)


Jumping beyond -128 to +127?

Requirement Then do this!

CMP SI, DI CMP SI, DI

JE SAME JNE NEXT

What if >127 bytes

ADD CX, DX JMP SAME

: NEXT: ADD CX, DX

: :

SAME: SUB BX, AX :

SAME: SUB BX, AX

Range for JMP (unconditional jump) can be +215 = + 32K


Terms used in comparison

Above and Below used for comparing Unsigned nos.

Greater than and less than used with signed numbers.

All Intel microprocessors use this convention.

95H is above 65H Unsigned comparison - True

95H is less than 65H Signed comparison - True

95H is negative, 65H is positive

65H is below 95H Unsigned comparison - True

65H is greater than 95H Signed comparison - True


Jump on multiple flagsJump on multiple flags

Conditional Jumps based on more than one flag are used after a CMP (compare) instruction.

JBE or

JNA

Jump if Below or Equal

Jump if Not Above

Jump if No Jump if Ex.

Cy = 1 OR Z= 1 Cy = 0 AND Z = 0 CMP BX, CX

Below OR Equal Surely Above JBE BX_BE

BX_BE (BX is Below or Equal) is a symbolic locationBlog:


Jump on multiple flags contdJump on multiple flags contd..

JNBE or

JA

Jump if Not (Below or Equal)

Jump if Above

Jump if No Jump if Ex.

Cy = 0 AND Z= 0 Cy = 1 OR Z = 1 CMP BX, CX

Surely Above Below OR Equal JA BXabove

BXabove (BX is above) is a symbolic location


Jump on multiple flags contdJump on multiple flags contd.

JLE or

JNG

Jump if Less than OR Equal

Jump if Not Greater than

Jump if No Jump if

S = 1 AND V = 0

(surely negative)

OR (S = 0 AND V = 1)

(wrong answer positive!)

OR Z = 1 (equal)

i.e. S XOR V = 1 OR Z = 1

S = 0 AND V = 0

(surely positive)

OR (S = 1 AND V = 1)

(wrong answer negative!)

AND Z = 0 (not equal)

i.e. S XOR V = 0 AND Z = 0


Jump on multiple flags contd.Jump on multiple flags contd.

JNLE or

JG

Jump if Not (Less than OR Equal)

Jump if Greater than

Jump if No Jump if

S = 0 AND V = 0

(surely positive)

OR (S = 1 AND V = 1)


AND Z = 0 (not equal)

i.e. S XOR V = 0 AND Z = 0

S = 1 AND V = 0

(surely negative)

OR (S = 0 AND V = 1)


OR Z = 1 (equal)

i.e. S XOR V = 1 OR Z = 1


Jump on multiple flags Jump on multiple flags contd.contd.

JL or

JNGE

Jump if Less than

Jump if Not (Greater than OR Equal)

Jump if No Jump if

S = 1 AND V = 0

(surely negative)

OR (S = 0 AND V = 1)


i.e. S XOR V = 1When S = 1, result cannot be 0

S = 0 AND V = 0

(surely positive)

OR (S = 1 AND V = 1)


i.e. S XOR V = 0When S = 0, result can be 0


Jump on multiple flags Jump on multiple flags contd.contd.

JNL or

JGE

Jump if Not Less than

Jump if Greater than OR Equal

Jump if No Jump if

S = 0 AND V = 0

(surely positive)

OR (S = 1 AND V = 1)


i.e. S XOR V = 0When S = 0, result can be 0

S = 1 AND V = 0

(surely negative)

OR (S = 0 AND V = 1)


i.e. S XOR V = 1When S = 1, result cannot be 0


Near JumpNear Jump

Near Jump

Direct Jump

(common)

Indirect Jump

(uncommon)

Short Jump Long Jump

2 or more bytes

Starting with FFH

Range: complete segment

2 bytes 3 bytes

EB r8 E9 r16

range + 27 range +215

3 Near Jump and 2 Far Jump instructions have the same mnemonic JMP but different opcodes


Short JumpShort Jump

2 byte (EB r8) instruction Range: -128 to +127 bytes

Backward jump: Assembler knows the quantum of jump.

Generates Short Jump code if <=128 bytes is the required jump

Generates code for Long Jump if >128 bytes is the required jump

Forward jump: Assembler doesn’t know jump quantum in pass 1.

Assembler reserves 3 bytes for the forward jump instruction.

If jump distance turns out to be >128 bytes, the instruction is coded as E9 r16 (E9H = Long jump code).

If jump distance becomes <=128 bytes, the instruction is coded as EB r8 followed by code for NOP (E8H = Short jump code).


Short Jump contd.Short Jump contd.

SHORT Assembler Directive

Assembler generates only 2 byte Short Jump code for forward jump, if the SHORT assembler directive is used.

JMP SHORT SAME

Programmer should ensure that the Jump distance is <=127 bytes

:

:

SAME: MOV CX, DX


Long JumpLong Jump

3-byte (E9 r16) instruction Range: -32768 to +32767 bytes

Long Jump can cover entire 64K bytes of Code segment

CS:0000H

Long Jump can handle it as jump quantum is <=32767

CS:8000H JMP FRWD

:

:

FRWD = CS:FFFFH


Long Jump contd.Long Jump contd.

It can cover entire 64K bytes of Code segment

Long Jump can handle it as jump quantum is <=32768

BKWD = CS:0000H

CS:8000H JMP BKWD

:

:

CS:FFFFH


Long Jump or Short Jump?Long Jump or Short Jump?

Can be treated as a small (20H) backward branch!

CS:0000H :

: Jump distance =FFE0H. Too

very long

forward jump

CS:000DH JMP FRWD

CS:0010H :

:

FRWD= CS:FFF0H

CS:FFFFH


Long Jump or Short Jump?Long Jump or Short Jump?

Can be treated as a small (20H) forward branch!

CS:0000H :

: Jump distance =FFE0H. Too

very long

backward jump

BKWD= CS:0010H :

:

JMP BKWD

CS:FFF0H

CS:FFFFH


Intra segment indirect JumpIntra segment indirect Jump

Near Indirect Jump is uncommon.

Instruction length: 2 or more bytes

Range: complete segment

Ex.1: JMP DX

If DX = 1234H, branches to CS:1234H

1234H is not signed relative displacement

Ex. 2: JMP wordptr 2000H[BX]

BX 1234H DS:3234H 5678H Branches to

DS:3236H AB22H CS:5678H


Far JumpFar Jump

Far Jump

Direct Jump

(common)

Indirect Jump

(uncommon)

5 bytes

2 or more bytes

Starting with FFH

Range: anywhere

EA,2 byte offset, 2 byte segment

Range: anywhere

3 Near Jump and 2 Far Jump instructions have the same mnemonic JMP but different opcodes


Inter segment Direct JumpInter segment Direct Jump

Also called Far Direct Jump

It is the common inter segment jump scheme

It is a 5 byte instruction

1 byte opcode (EAH)

2 byte offset value

2 byte segment value

Ex. JMP Far ptr LOC


Inter segment Indirect JumpInter segment Indirect Jump

Instruction length depends on the way jump location is specified

It can be a minimum of 2 bytes

Ex. JMP DWORD PTR 2000H[BX]


Inter segment Indirect JumpInter segment Indirect Jump

Also called Far Indirect Jump

It is not commonly used

Instruction length is a minimum of 2 bytes.

It depends on the way jump location is specified

Ex. JMP DWORD PTR 2000H[BX]

BX 1234H Branches to

ABCDH:5678H

DS:3234H 5678H It is a 4-byte instruction

DS:3236H ABCDH


Conditional Jump Examples; Implementation A CMP AX, BX ; compare ax to bx to ; set flags JE THERE ; if equal, then skip ; correction stmt ADD AX, 0002H ; correction stmtTHERE: MOV CL, 07H ; load count

; Implementation B CMP AX, BX ; compare ax to bx to ; set flags JNE FIX ; if not equal, then ; correct JMP THERE ; unconditional jump to ; thereFIX: ADD AX, 0002H ; correction stmtTHERE: MOV CL, 07H ; load count


Rotate• This is how we can move the lower nibble to the upper

nibble MOV CL, 04H ;store value in register ROL BL, CL ;rotate left 4 bits

• Rotate instructions› ROL, ROR

• rotates each bit 1 position to the left/right

• MSB is moved into LSB, and into CF

› RCL, RCR • rotates each bit 1 position to the left/right

• MSB is moved into CF, CF is moved into LSB

› the source operand can be either CL or 1› the destination operand can be either a register or memory


Shift and Rotate Instructions

SHR/SAL: shift logical left/shift arithmetic left SHR: shift logical right SAR: shift arithmetic right ROL: rotate left ROR: rotate right RCL: rotate left through carry RCR: rotate right through carry


Logical vs Arithmetic Shifts

• A logical shift fills the newly created bit position with zero:

• An arithmetic shift fills the newly created bit position with a copy of the number’s sign bit:


Mnemo-nic

Meaning Format Operation Flags Affected

SAL/SHL

SHR

SAR

Shift arithmeticLeft/shiftLogical left

Shift logical right

Shift arithmeticright

SAL/SHL D, Count

SHR D, Count

SAR D, Count

Shift the (D) left by the number of bit positions equal to count and fill the vacated bits positions on the right with zeros

Shift the (D) right by the number of bit positions equal to count and fill the vacated bits positions on the left with zeros

Shift the (D) right by the number of bit positions equal to count and fill the vacated bits positions on the left with the original most significant bit

CF,PF,SF,ZFAF undefinedOF undefined if count ≠1



Shift Instructions


Allowed operands

Destination Count

Register

Register Memory Memory

1

CL

1

CL


Blog:


SHL Instruction

• The SHL (shift left) instruction performs a logical left shift on the destination operand, filling the lowest bit with 0.

• Operand types:SHL reg,imm8SHL mem,imm8SHL reg,CLSHL mem,CL Blog:


Fast Multiplication

mov dl,5

shl dl,1

Shifting left 1 bit multiplies a number by 2

mov dl,5shl dl,2 ; DL = 20

Shifting left n bits multiplies the operand by

2n

For example, 5 * 22 = 20


Ex.; Multiply

AX by 10SHL AX, 1MOV BX, AXMOV CL,2SHL AX,CLADD AX, BX


SHR Instruction

• The SHR (shift right) instruction performs a logical right shift on the destination operand. The highest bit position is filled with a zero.

MOV DL,80SHR DL,1 ; DL = 40SHR DL,2 ; DL = 10

Shifting right n bits divides the operand by 2n


SAR Instruction

• SAR (shift arithmetic right) performs a right arithmetic shift on the destination operand.

An arithmetic shift preserves the number's sign.

MOV DL,-80SAR DL,1 ; DL = -40SAR DL,2 ; DL = -10


Rotate InstructionsRotate InstructionsMnem-onic

Meaning Format Operation Flags Affected

ROL Rotate Left

ROL D,Count Rotate the (D) left by the number of bit positions equal to Count. Each bit shifted out from the left most bit goes back into the rightmost bit position.

CF OF undefined if count ≠ 1

ROR Rotate Right

ROR D,Count Rotate the (D) right by the number of bit positions equal to Count. Each bit shifted out from the rightmost bit goes back into the leftmost bit position.


RCL Rotate Left through Carry

RCL D,Count Same as ROL except carry is attached to (D) for rotation.


RCR Rotate right through Carry

RCR D,Count Same as ROR except carry is attached to (D) for rotation.

CF OF undefined if count ≠ 1Blog:


ROL Instruction• ROL (rotate) shifts each bit to the left• The highest bit is copied into both the Carry flag

and into the lowest bit• No bits are lost

MOV Al,11110000bROL Al,1 ; AL = 11100001b

MOV Dl,3FhROL Dl,4 ; DL = F3h


ROR Instruction• ROR (rotate right) shifts each bit to the right• The lowest bit is copied into both the Carry flag and

into the highest bit• No bits are lost

MOV AL,11110000bROR AL,1 ; AL = 01111000b

MOV DL,3FhROR DL,4 ; DL = F3h


RCL Instruction• RCL (rotate carry left) shifts each bit to the left• Copies the Carry flag to the least significant bit• Copies the most significant bit to the Carry flag

CF

CLC ; CF = 0MOV BL,88H ; CF,BL = 0 10001000bRCL BL,1 ; CF,BL = 1 00010000bRCL BL,1 ; CF,BL = 0 00100001b


RCR Instruction• RCR (rotate carry right) shifts each bit to the right

• Copies the Carry flag to the most significant bit

• Copies the least significant bit to the Carry flag

STC ; CF = 1MOV AH,10H ; CF,AH = 00010000 1RCR AH,1 ; CF,AH = 10001000 0


Destination Count

Register

Register Memory Memory

1

CL

1

CL

Rotate Instructions


Comparison InstructionsComparisons can be performed using the CMP instruction:CMP op1, op2

CMP performs the subtraction op1 - op2 and sets the appropriate flags in the ST register. It does not store the result of the subtraction.

if op1 > op2, CF = 0, ZF = 0if op1 < op2, CF = 1, ZF = 0if op1 = op2, CF = 0, ZF = 1

CMP may taking the following forms of arguments:CMP reg, regCMP mem, regCMP reg, memCMP reg, immedCMP immed, regCMP accum, immed


The TEST instruction also performs comparisons of its operands by performing a bitwise AND.TEST op1, op2

TEST performs the bitwise AND op1 & op2 and sets the appropriate flags in the ST register. It does not store the result of the AND.

It will always reset the Overflow and Carry flags and will set the Sign, Zero, and Parity flags based on the result of the AND operation.

TEST may taking the following forms of arguments:TEST reg, regTEST mem, regTEST reg, memTEST reg, immedTEST immed, regTEST accum, immed


String control instruction1] MOVS/ MOVSB/ MOVSWDest string name, src string nameThis inst moves data byte or word from location in DS to location in ES.2] REP / REPE / REPZ / REPNE / REPNZRepeat string instructions until specified conditions exsist.This is prefix instruction.3] CMPS / CMPSB / CMPSWCompare string bytes or string words.4] SCAS / SCASB / SCASWScan a string byte or string word.Compares byte in AL or word in AX.String address is to be loaded in ES:DI.5] STOS / STOSB / STOSWStore byte or word in a string.Copies a byte or word in AL or AX to memory location pointed by DI.6] LODS / LODSB /LODSW Load a byte or word in AL or AX Copies byte or word from memory location pointed by SI into AL or AX register.


Interrupt control instruction

1]INT type2] INTO Interrupt on overflow3] IRET Interrupt return


8086 Addressing Modes

• There are 24 different addressing modes!› Fortunately, they break down into a smaller

number of distinctive categories

• Addressing Mode means how the address information in the instruction is used to select a physical address› Common modes specify one or more of Base

register, Index register, and Displacement


Direct Addressing

• Instruction contains a displacement into a segment› Segment may be implied or specified using the

segment override operator

mov ax,abc

mov cl,ss:12

mov dl,es:200


Register Indirect

• Offset is contained in a register - it is a pointer to a memory location› BP, BX, SI, DI only› JMP and CALL allow any GP register to be

used

• The segment register is implied or may be specified


Register Indirect Examples

mov ax,[bp]

mov cl,ss:[bx]

mov dl,es:[si]

mov [di],ax• DS is assumed for BX, SI, and DI

• SS is assumed for BP


Base and Indexed Addressing

mov ax,numbers[SI]

mov cl,[BP+4]

mov ES:6[DI],AX• This is the same as Register Indirect, except

a displacement is added into the mixture

• Based: BP or BX are used

• Indexed: SI or DI are used


Base-Index Addressing

mov cl,[BX][SI]

mov ax,numbers[SI+BP]

mov ES:6[SI+BX],dh• One base register and one index register

• If a displacement is specified, the addressing mode is called Base-Index with Displacement


PTR and LABEL

• Ambiguous size operands› Use PTR to resolve

mov [bx],1

mov word ptr [bx],1

mov [si], 'A'

mov [si],byte ptr 'A'

X label byte

M label word

DW 100• X and M refer to

the same address

mov AH,X

mov AH,byte ptr M

mov AX,MBlog:


Access to the Stack

• mov bp,sp ;BP points to stack top

• mov ax,[bp+0] ;top of stack

• mov bx,[bp+2] ;next to top of stack

• mov [bp+3],ah ;byte at offset 3 in stack

• mov [bp-1],ch ;byte above top of stack ... A3 17FF20 5F

003ASP

...


Operand TypesOperands are generally considered to be of 3 different types:immediateregistermemory

An immediate operand is a constant.A register operand is one of the CPU registers.A memory operand is a reference to a location in memory.

The 8086 architecture provides 6 possible ways for specifying a memory operand:directdirect-offsetregister-indirectindexedbase-indexedbase-indexed with displacement


direct is the offset of a variable.count db 20mov al, countmov bx, offset count direct-offset is the sum of a variable’s offset and a displacementarrayB db 12, 14, 16, 18arrayW dw 1000H, 2000H, 3000Hmov al, arrayB + 1mov ah, arrayB + 2mov ax, arrayW + 2mov bx, arrayW + 4

register-indirecta register that contains the offset of data in memory. Only the SI, DI, BX, and BP registers can be used as indirect operands.astring db “abcdef”mov bx, offset astringadd bx, 5mov dl, [bx] Blog:


indexed is the sum of a base or index register and a displacementmov ax, arrayW[si]mov ax, arrayW[bx]

base-indexed is the sum of a base register and an index registermov ax, [bx+si]mov ax, [bx][si]

base-indexed with displacement is the sum of a base register, and index register, and a displacementmov ax, [bx+si+2]mov ax, arrayW[bx][si]


8086 Displacement Only Addressing Mode

• Most common and easiest to understand

• Consists of a 16 bit constant that specifies the address of the target location

› Instruction mov al,ds:[8088h] loads al register with a copy of the byte at memory location 8088h


8086 Register Indirect Addressing Modes

• Access memory indirectly through a register › For example, mov al, ds:[bx] or mov al, ss:[si]


8086 Indexed Addressing Modes

• Use the following syntax: mov al, disp[bx] or mov al, cs:disp[si]

• For examples› If bx contains 1000h, instruction mov cl,20h[bx] will load cl from

memory location ds:1020h

› Likewise, if bp contains 2020h, mov dh,1000h[bp] will load dh from location ss:3020


8086 Based Indexed Addressing Modes

• Combinations of register indirect addressing modes

• Form offset by adding a base register (bx or bp) and an index register (si or di) in form of

mov al, [bx][si]Let bx contains 1000h and si contains 880h, the above instruction

willload al from location DS:1880h


8086 Based Indexed Plus Displacement Addressing Mode

• Slight modification of base/indexed addressing modes with addition of an 8 bit or 16 bit constant


Documents

Introduction to 8086 Assembly Language Programming