Intro to Micr0wind Sofware

Lab No. 08

Introduction To Micro wind SoftwareOr

Introduction To Layout & Fabrication

Aim:

Fabrication of nmos & pmos transistors. Making 2 or 3 transistor (nmos or pmos) of different sizes & then define different rise/fall

time and high/low for each of the transistor and analyze the transistor characteristics. By considering high/low time limit the frequency.

Software Background:

The software includes the following portions:

Main Menu: In Main menu we have

From file menu we can select new file, insert layout, save as, colors etc From view menu we can select refresh, select all, zoom in , zoom out etc From view menu we can select copy, paste, protect all, unprotect all etc. From simulate menu we can select run simulation, simulation parameters etc From compile menu we can select compile one line, compile verilog file. From analysis menu we can select design rule checker, parametric analysis etc In help we can get help about rules, micro wind etc.

File View Edit Simulate

Icon Menu:

1Micro-Electronics Technologies

In icon menu we have number of useful operations:

Open file , Save , Draw Box , Delete , Copy , Paste , Zoom in , Zoom out

, 2D view , 3D view etc

Layout Window:

Use to create layouts:

Palette Bar:

We have number of components for making the layouts:

Metal Layers.

Diffusion Layers.

Polysilicon Layers.

Connectors.

Clock Signals.

Vdd.

Cmos Technology:


In cmos technology the combination of P-mosfets & N-mosfets is used for the better results. As it is understood that n-mosfets completely transmits logic 0 but partially logic 1 while p-mosfets completely transmits logic 1 but transmit logic 0 with error. So to overcome this problem p & n mosfets are used in combination called Complementary Mosfets (cmos)

There are certain advantages of cmos technology.

o High noise immunity property is possessed by cmos.

o CMOS has relatively less number of transistors where as TTL has a number of transistors and a number of resistors to perform the same function. Therefore CMOS has low static power consumption.

o Due to less number of components CMOS devices are also cheaper & affordable.

o It enables chips that are small in size to have features like high operating speeds and

efficient usage of energy.

Apparatus:

Microwindv2-7 installed PC.

Procedure:

First of all open the software by clicking on-to the icon . For the specific gate select the required components by clicking the icon palette

. Microwind software includes a comprehensive library, from this library (palette), from

palette we can select Metal Layers, Diffusion Layers, Polysilicon Layers, Connectors, Clock Signals, Vdd for making the device layouts.

Draw different layers by selecting the layer & then drawing by click & drag. We can also see the 2D look & 3D look of the layout by clicking the required icon from

icon menu. The components attributes can be changed by double clicking on-to the component there

by changing the required field.

After completing the circuit diagram simulate the circuit by clicking & the figures window will appear.


http://en.wikipedia.org/wiki/Electronic_noise

Gate 1: nmos

Components:

Polysilicon layer for gate.o Gate Length = 2.100 um Gate Width = 0.300 um

Layer for nmoso N+ Layer Length = 1.500 um N+ Layer Width = 1.500 um

Metal 1 for connections.

Connectors to connect N+ & metal 1 Clock Signal as gate signal & as input at source.

o Clock Parameters For Gate:

Rise Time: 0.025 ns Fall Time: 0.025 ns Time Low: 0.225 ns Time High: 0.225 ns

o Clock Parameters For Input:

Rise Time: 0.025 ns Fall Time: 0.025 ns Time Low: 0.475ns Time High: 0.475ns

Layout Diagram:


Analog Simulation Window:

Fig (a): For gate1 (nmos) Simulation window

Conclusion from the Figure (a):

As nmos is strong logic zero transmitters that is why in figure the zero is transmiting to output accurately but 1 is not transmitting accurately & providing some undetermined state.

As the gate on/off time is 0.225 ns so frequency will be 1

0.225ns=3.9∗109Hz.

So for this transistor the signal at source must have frequency less than or equal to

3.9∗109Hz.

o Input frequency to transistor must be ≤3.9∗109Hz.

Any input to this transistor with frequency higher than this range will make the output faulty and cannot transfer to output exactly.

Gate 2: nmos

Components:


Layer for nmoso N+ Layer Length = 2.400 um N+ Layer Width = 1.500 um


Connectors to connect N+ & metal 1


Clock Signal as gate signal & as input at source.o Clock Parameters For Gate:




Layout Diagram:



Fig (b): For gate2 (nmos) Simulation window

Conclusion from the Figure (b):

Again nmos is strong logic zero transmitters that is why in figure the zero is transmitting to output accurately but 1 is not transmitting accurately & providing some undetermined state.

As the gate on/off time is 0.442 ns so frequency will be 1

0.442ns=2.6∗109Hz.


2.6∗109Hz.



Gate 3: pmos

Components:


Layer for pmoso P+ Layer Length = 1.200 um P+ Layer Width = 0.900 um


Connectors to connect P+ & metal 1


Clock Signal as gate signal & as input at source.o Clock Parameters For Gate:

Rise Time: 0.225ns Fall Time: 0.225ns Time Low: 0.225ns Time High: 0.225ns


Rise Time: 0.025 ns Fall Time: 0.025 ns Time Low 0.375ns Time High: 0.375ns

Layout Diagram:



Fig (c): For gate3 (pmos) Simulation window

Conclusion from the Figure ©:

As pmos is strong logic one transmitters that is why in figure the one(i-e 0.5 in this case) is transmitting to output accurately but 0 is not transmitting accurately & providing some undetermined state.

As the gate on/off time is 0.225 ns so frequency will be1

0.225ns=3.9∗109Hz.


3.9∗109Hz.




Documents

Intro to Micr0wind Sofware