Interrupts& Busses

COMP375 Computer Architecture and Organization

“Lots of people want to ride with you

in the limo, but what you want is

someone who will take the bus with

you when the limo breaks down.”Oprah Winfrey

Immediate Attention

• Interrupts are a way that a running program can be stopped to allow the operating system to do something immediately

• Some activities require the CPU to respond quickly. A very short program may be all that is necessary to handle a situation, but that program has to be run very quickly after the situation occurs

• When a program does something wrong (divide by zero or bad pointer), the operating system needs to take over

Interrupts and Exceptions

• An interrupt is a change in program defined flow of execution

• When an interrupt occurs, the hardware executes the instructions at a specified address instead of following the normal program flow

• User programs are interrupted all the time

Transfer of Control via Interrupt

graphic from Stallings textbook

Types of Interrupts

• External – Generated by an I/O device

• Internal – Exception within a program

• Program Generated – Used to transfer control to the operating system

Interrupt Action

• When an interrupt occurs, the program counter and status flags are saved in a special location

• New program counter and status flags are loaded. These values could be determined by the type of interrupt

Interrupt Service Routines (ISR)Entry Point

• It is possible for all interrupt service routines to start at the same location. The software can determine what kind of interrupt

• The hardware can assist by using the interrupt type as an index into a table of ISR addresses

• Each interrupt may have a different ISR entry point or classes of interrupts may have a common entry point

Interrupt Vector Points to ISRs// Divide error

… Interrupt Service Routine …

// Page Fault

… Interrupt Service Routine …

// Floating Point overflow…

… Interrupt Service Routine …

// Bad Address

… Interrupt Service Routine …

// Incorrect opcode

… Interrupt Service Routine …

Interrupt

Vector

1: 1234

2: 2341

3: 5634

4: 4327

5: 4644

etc.

Interrupt Vector

• In the Intel Pentium each interrupt type has a number associated with it, called the interrupt request queue (IRQ) number

• When a device interrupts, the IRQ is used as an index into a table of ISR addresses

• The operand of the int instruction provides an index into a table of ISR addresses

After handling an interrupt, the OS returns control to

A. The instruction that caused the interrupt

B. The instruction after the one that caused the interrupt

C. Does not return to the program

D. All of the above

E. None of the above

Multiple Interrupts

• An interrupt event can occur while the processor is handling a previous interrupt

• If the return address is always stored at a fixed location, the occurrence of an interrupt while handling a previous interrupt will overwrite the previous return address

• Most interrupt service routines start with interrupts disabled. This prevents an interrupt service routine from being interrupted

Masking Interrupts

• Some interrupts can be temporarily disabled. Most processors can disable external interrupts

• Most internal interrupts cannot be disabled

• It is generally problematic to disable interrupts for a lengthy period of time

Intel EFLAGS Register

Definition Of A Bus

• Digital interconnection mechanism

• A set of parallel wires with rules for putting and retrieving information on the wires

• A digital communication mechanism that allows two or more functional units to transfer control signals or data

• The connection medium allowing the CPU, memory and I/O controllers to communicate

Basic Computer Components

CPU

cache I/O Controller

I/O Device

MemoryBus

More Complex Modern Bus

Many Busses

• The Bus we are talking about today is different from the bus that connects the registers in the CPU

• The system bus is on the motherboard and is up to 30 cm in length

• The internal CPU bus is on the chip and is less than a millimeter in length

Physical Connections

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Physical Bus Interface

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External and Internal• Internal buses

– connect the primary computer components

– transfer data at up to 20 GB/sec

– about 30 – 40 cm maximum length

• External buses

– USB, IEEE-1394 and Firewire

– USB 2.0 runs at 280 Mb/sec

– USB 3.0 runs at 5 Gb/sec and USB 3.1 at 10 Gb/sec

– USB cables can be 5m in length

– Allow hot swapping of devices

Bus Design Issues

• Dedicated or Multiplexed

• Width

• Access Protocol

• Arbitration

• Timing

• Operation

Bus Lines

• Transfer of data

• Address information

• Control of the bus

– Memory fetch or store

– Ready

– Bus Request and Bus Grant

– Interrupt and Interrupt Acknowledge

– Clock

Bus Width

• The width of a bus is the number of lines.

• The more data lines, the more data that can be transferred simultaneously

• A “32 bit bus” has 32 data lines

• The more address lines, the larger the maximum amount of memory that can be accessed

• The greater the width, the more hardware required to implement the bus

Address Limits

• Each wire can be grounded or attached to a voltage source

• Each wire can be 1 or 0

• The number of wires determines the maximum number of bits in the address

• The maximum amount of addressable memory is

2number of address wires

• A 32 bit processor can address 4 GB

How much memory can you address with 24 bits?

1. 16 M bytes

2. 24 M bytes

3. 2 G bytes

4. 4 G bytes

Example Bus Width• 32-bit Pentium processor has a 64-bit data bus

• Itanium is a 64-bit processor with a 128-bit data bus

• Address bus width– Determines the system addressing capacity

– N address lines directly address 2N memory locations

• 8086: 20 address lines

– Can address 1 MB of memory

• Pentium: 32 address lines

– Can address 4 GB of memory

• Itanium: 64 address lines

– Can address 264 bytes of memory

• AMD Athlon™ 64: 40 address lines

– Can address 1 TB of memory

Dedicated or Multiplexed

• With a dedicated bus there are separate wires for data and addresses

• With a multiplexed bus, the same lines are used at different times to hold either data or addresses

Dedicated Bus

• A store operation can put both the address and the data on the bus at the same time

• Having separate data and address lines simplifies the bus protocol

Multiplexed Bus

• Multiplexed buses require fewer lines

• Chips can be limited in the number of pins that can be physically attached

• For a given number of pins, it is usually advantageous to transfer more data

• Data and addresses may appear on the bus at different times

Fetch-Store Paradigm

• A processor can fetch a value from memory or store a value to memory

• Fetch and store are also used to transfer data to an I/O device

• Only one device at a time can put a value on the bus data or address lines

Fetch

1. Use control lines to obtain access to bus

2. Place an address on the address lines

3. Use control lines to request a fetch operation

4. Wait until operation complete

5. Read the value from the data lines

6. Set controls line to allow another device to use the bus

Store

1. Use control lines to obtain access to bus

2. Place an address on the address lines

3. Place value on the data lines

4. Use control lines to specify a store function

5. Wait until operation complete

6. Set controls line to allow another device to use the bus

Block Transfers

• With cache systems, memory requests to the RAM are for a whole line of data

• The CPU requests an address and the RAM provides a series of data values

• I/O controllers may still communicate with the CPU or the memory with arbitrarily sized data

Wait States

• Some devices are not as fast as the CPU

• When the CPU requests data from RAM or an I/O device, it may not be able to get it the next clock cycle

• A wait state is created when the CPU must wait for a device to be ready

• The CPU needs to wait until a device signals it is ready to provide the data

Timing Diagrams - Clock• There is a horizontal line for each signal

• A synchronous bus has a clock signal that synchronizes operations

• Time goes from left to right

Timing Diagrams – Data Lines

• Multiple data or address lines are often shown as a block

• Data or address lines can be

– all one or all zero

– mixed with some zero and some one

– undetermined, value is unimportant

Memory read with no wait states

©S. Dandamudi

Memory read with a wait state

©S. Dandamudi

Block transfer of data

©S. Dandamudi

If the bus has a 2.0 GHz clock, how long is each clock cycle?

A. 500 microsecond

B. 2.0 millisecond

C. 2.0 nanosecond

D. 5.0 nanosecond

E. 0.5 nanosecond

Cycles and Bus Width

• If a bus is n bits wide, it can transfer n bits (or n/8 bytes) every cycle

• If you need to transfer more than n bits, it will take multiple cycles

• To transfer x bytes over an n bit wide bus, it takes 8x / n cycles plus any cycles previous to the data transfer

How many clock cycles does it take to transfer 96 bytes over a 128 bit wide

bus?

• A 128 bit wide bus can transfer 128/8 = 16 bytes each cycle

• 96 bytes / 16 bytes/cycle = 6 cycles

• If there was a 4 cycle delay before the data was available, the total time would be 6 + 4 = 10 cycles

How many clock cycles does it take to transfer 64 bytes over a 64 bit wide bus?

A. 1 cycle

B. 2 cycles

C. 4 cycles

D. 8 cycle

E. 16 cycles

How many bus clock cycles does it take from when the CPU first requests the data until 32 bytes have been read?

A. 2 cycles

B. 3 cycles

C. 4 cycles

D. 7 cycles

E. 8 cycles

A bus protocol requires the CPU to

put the address on the 64 bit wide

bus during the first clock period.

On the fourth clock period and

every clock period afterwards data

is retrieved from the RAM.

How much time does it take for7 cycles on a 1.0 GHz bus?

A. 7.0 nsec

B. 14.0 nsec

C. 3.5 nsec

D. 7.0 μsec

If every instruction requires two memory access of 7.0 nsec, what is the maximum execution speed in MIPS?

A. 71 MIPS

B. 11 MIPS

C. 45 MIPS

D. 22 MIPS

E. Cannot be determined

Synchronous or Asynchronous

• In a synchronous bus, a clock signal provides timing for all operations

• A device presents the address on a given clock pulse and expects the data during another predefined clock pulse

• In an asynchronous bus, a device waits for a ready signal to know when data is available

Asynchronous Bus

©S. Dandamudi

Arbitration• Only one device can put data on the bus at a time. Many

devices can sense the data, but only one can assert it

• The bus arbitration protocol determines which device gets to use the bus at any given time

• Bus arbitration can be centralized or distributed

Centralized Arbitration

Daisy Chain Bus

The devices determine who gets to use the bus

Multiple Buses• A single computer usually has several buses.

• Different devices have different requirements

• A 56K modem only needs about 7 KB/sec bandwidth while a graphics device may need 70 MB/sec or more

• Multiple buses allow devices using different technologies to connect to the same computer

Bridging Buses

• A bridge is a device that connects two buses

• A bridge converts the addresses and protocols of one bus to another

Bridge

Bus Hierarchy

Chipsets

• The chipset controls the bus

• Intel Pentium® processors are available with system bus speeds of 400, 533, 800, 1066 MHz and more

• The Intel X38 Express chipset operates at 1333 MHz and can transfer data at up to 21.2 GB/s

Extreme Processing Power

Choose from the latest Intel® processors, which use the

new Intel X38 Express chipset – state-of-the-art

processing designed to drive your system and digital

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Bus Standards

• To allow different equipment to connect together, devices need to follow standards

• Bus designs are often developed by individual companies and then standardized by industry organizations

ISA Bus• The Industry Standard Architecture (ISA) bus was used in

the first 8088 PCs

• It was originally a 8 bit data bus with 20 dedicated address lines

• Bus design similar to 8088 local bus

• The bus was updated to have 16 data lines and operate at 8.33 MHz providing 8 MB/second bandwidth

• Updated again to the Extended ISA (EISA)

PCI Bus

• The Peripheral Component Interconnection (PCI) bus was developed by Intel in the early 1990s

• PCI has 64 data lines running at 66 MHz providing up to 528 MB/sec bandwidth

• Data and address lines are multiplexed

• Centralized arbitration

PCI Express

• Now on version 3.0, PCIe is a high speed replacement for PCI that can transfer up to 16 GB/s

• Structured around point-to-point serial links instead of a shared bus

• Allows more than one pair of devices to communicate with each other at the same time

SCSI Bus

• Pronounced “scuzzy”

• Small Computer System Interface

– Supports both internal and external connection

• Comes in multiple bus widths

• Allows the connection of up to 16 devices. Each device has a bus ID

• Popular for hard drive

Fiber Optic SCSI Buses

• The original SCSI bus systems involved multiple parallel

wires

• Some newer SCSI standards run over fiber optic cables

• Fiber optics uses only one "wire"

• Data is transmitted serially

Beyond Buses• Although there are several devices that communicate

over the bus, only one device can send data at a time

• Other interconnection schemes allow multiple simultaneous connections

• There are many designs of switching fabrics to interconnect devices

• Most switching fabrics can be expensive to implement

Crossbar Switch

© D. Comer