1
1 2 3 4 5 6 A B C D 6 5 4 3 2 1 D C B A MCU ER-OLED096-1 C/D# CS# R/W# E_RD# RES# DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 The Parallel (8080 Series MCU)Reference Example SSD1306 AT89C52 Data/Instruction selected pin Chip selected when low Write signal Read signal Reset input Data Data Data Data Data Data Data Data 1 13 14 15 16 17 18 19 20 21 22 23 24 26 10 VDD P3.5 P3.4 P3.3 P3.1 P3.0 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 20 40 31 EA VCC GND P3.2 XTAL1 XTAL2 /RESET S1 SW-PB C15 10UF Y1 12MHZ C13 27PF C14 27PF S2 SW-PB R1 10K VDD 9 10 11 12 13 14 15 18 19 1 2 3 4 5 6 7 8 NC BS2 BS0 BS1 11 12 EASTRISING TECHNOLOGY CO.,LTD. ER-OLED096-1 A0 1 Javen Title Number Size A Date: 03-Feb-2010 Sheet of Revision File Drawn By The Parallel (6800 Series MCU)Series MCU)Reference Example The Serial (4line SPI)Reference Example S1 SW-PB S1 SW-PB R2 10K R3 10K VDD VDD PAUSE RESET CONTRAST + CONTRAST - 38 37 P0.1 P0.2 CAP1P CAP1N CAP2N CAP2P VCC Generated by Internal DC/DC Circuit C2 1uf C1 1uf 4 5 2 3 6 VBAT +3.6V C3 1uf 7 NC 8 VSS C4 1uf 9 VDD +3.3V NC 30 VLSS VCC VCOMH IREF C5 2.2uf C6 4.7uf R 390K 26 27 28 29 +3.3V MCU C/D# CS# R/W# E_RD# RES# DB0 DB1 DB2 DB3 DB4 DB5 SSD1306 AT89C52 Data/Instruction selected pin Chip selected when low Read/Write signal Enable signal Reset input Data Data Data Data Data Data Data Data 1 13 14 15 16 17 18 19 20 21 22 23 24 26 10 VDD P3.5 P3.4 P3.3 P3.1 P3.0 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 20 40 31 EA VCC GND P3.2 XTAL1 XTAL2 /RESET S1 SW-PB C15 10UF Y1 12MHZ C13 27PF C14 27PF S2 SW-PB R1 10K VDD 9 10 11 12 13 14 15 18 19 1 2 3 4 5 6 7 8 NC BS2 BS0 BS1 11 12 S1 SW-PB S1 SW-PB R2 10K R3 10K VDD VDD PAUSE RESET CONTRAST + CONTRAST - 38 37 P0.1 P0.2 CAP1P CAP1N CAP2N CAP2P VCC Generated by Internal DC/DC Circuit C2 1uf C1 1uf 4 5 2 3 6 VBAT +3.6V C3 1uf 7 NC 8 VSS C4 1uf 9 VDD +3.3V NC 30 VLSS VCC VCOMH IREF C5 2.2uf C6 4.7uf R 390K 26 27 28 29 +3.3V MCU C/D# CS# R/W# E_RD# RES# DB0 DB1 DB2 DB3 DB4 DB5 SSD1306 AT89C52 Data/Instruction selected pin Chip selected when low Reset input SDIN SCLK 1 13 14 15 16 17 18 19 20 21 22 23 24 25 10 VDD P3.5 P3.4 P3.3 P3.1 P3.0 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 20 40 31 EA VCC GND P3.2 XTAL1 XTAL2 /RESET S1 SW-PB C15 10UF Y1 12MHZ C13 27PF C14 27PF S2 SW-PB R1 10K VDD 9 10 11 12 13 14 15 18 19 1 2 3 4 5 6 7 8 NC BS2 BS0 BS1 11 12 S1 SW-PB S1 SW-PB R2 10K R3 10K VDD VDD PAUSE RESET CONTRAST + CONTRAST - 38 37 P0.1 P0.2 CAP1P CAP1N CAP2N CAP2P VCC Generated by Internal DC/DC Circuit C2 1uf C1 1uf 4 5 2 3 6 VBAT +3.6V C3 1uf 7 NC 8 VSS C4 1uf 9 VDD +3.3V NC 30 VLSS VCC VCOMH IREF C5 2.2uf C6 4.7uf R 390K 26 27 28 29 DB6 DB7 DB6 DB7 NC The Serial (3line SPI)Reference Example MCU C/D# CS# R/W# E_RD# RES# DB0 DB1 DB2 DB3 DB4 DB5 SSD1306 AT89C52 Chip selected when low Reset input SDIN SCLK 1 13 14 15 16 17 18 19 20 21 22 23 24 26 10 VDD P3.5 P3.4 P3.3 P3.1 P3.0 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 20 40 31 EA VCC GND P3.2 XTAL1 XTAL2 /RESET S1 SW-PB C15 10UF Y1 12MHZ C13 27PF C14 27PF S2 SW-PB R1 10K VDD 9 10 11 12 13 14 15 18 19 1 2 3 4 5 6 7 8 NC BS2 BS0 BS1 11 12 S1 SW-PB S1 SW-PB R2 10K R3 10K VDD VDD PAUSE RESET CONTRAST + CONTRAST - 38 37 P0.1 P0.2 CAP1P CAP1N CAP2N CAP2P VCC Generated by Internal DC/DC Circuit C2 1uf C1 1uf 4 5 2 3 6 VBAT +3.6V C3 1uf 7 NC 8 VSS C4 1uf 9 VDD +3.3V NC 30 VLSS VCC VCOMH IREF C5 2.2uf C6 4.7uf R 390K 26 27 28 29 DB6 DB7 NC +3.3V The Serial (I2C)Reference Example MCU C/D# CS# R/W# E_RD# RES# DB0 DB1 DB2 DB3 DB4 DB5 SSD1306 AT89C52 Reset input SDA SCL 1 13 14 15 16 17 18 19 20 21 22 23 24 26 10 VDD P3.5 P3.4 P3.3 P3.1 P3.0 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 20 40 31 EA VCC GND P3.2 XTAL1 XTAL2 /RESET S1 SW-PB C15 10UF Y1 12MHZ C13 27PF C14 27PF S2 SW-PB R1 10K 9 10 11 12 13 14 15 18 19 1 2 3 4 5 6 7 8 NC BS2 BS0 BS1 11 12 S1 SW-PB S1 SW-PB R2 10K R3 10K VDD VDD PAUSE RESET CONTRAST + CONTRAST - 38 37 P0.1 P0.2 CAP1P CAP1N CAP2N CAP2P VCC Generated by Internal DC/DC Circuit C2 1uf C1 1uf 4 5 2 3 6 VBAT +3.6V C3 1uf 7 NC 8 VSS C4 1uf 9 VDD +3.3V NC 30 VLSS VCC VCOMH IREF C5 2.2uf C6 4.7uf R 390K 26 27 28 29 DB6 DB7 +3.3V R 10K R 10K VDD SSD1306 1 NC CAP1P CAP1N CAP2N CAP2P 4 5 2 3 6 VBAT C2 2.2uf 7 NC 8 VSS C1 0.1uf 9 VDD +3.3V NC 30 VLSS VCC VCOMH IREF C4 2.2uf C5 4.7uf R 560K 26 27 28 29 VCC Supplied Externally SA0 C4 2.2uf +9.5V ER-OLED096-1 ER-OLED096-1 ER-OLED096-1 ER-OLED096-1 3 1 AUSE +3. C3 f C C4 1u BS2 BS0 BS ER-O OLED0 .3 V C 1 C 1u C3 CAP1P CA CA P2N N Reference nal DC/DC Cir C/D nce Examp uit R3 SW-PB S S1 SW-PB B K O C CO PB B PB O PB B PB 1 10 K VDD CONTRAST C CO O RESET Interfacing OLED Display to the AT89LV52 MCU buy-display.comEastRising

Interfacing OLED Display to the AT89LV52 MCU€¦ · S1 SW-PB S1 SW-PB R2 10K R3 10K VDD VDD PAUSE RESET CONTRAST + CONTRAST - 38 37 P0.1 P0.2 CAP1P CAP1N CAP2N CAP2P VCC Generated

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Page 1: Interfacing OLED Display to the AT89LV52 MCU€¦ · S1 SW-PB S1 SW-PB R2 10K R3 10K VDD VDD PAUSE RESET CONTRAST + CONTRAST - 38 37 P0.1 P0.2 CAP1P CAP1N CAP2N CAP2P VCC Generated

1 2 3 4 5 6

A

B

C

D

654321

D

C

B

A

MCU

ER-OLED096-1

C/D#

CS#

R/W#

E_RD#

RES#

DB0DB1DB2DB3DB4DB5DB6DB7

The Parallel (8080 Series MCU)Reference Example

SSD1306

AT89C52

Data/Instruction selected pin

Chip selected when low

Write signal

Read signal

Reset input

DataDataDataDataDataDataDataData

113

14

15

16

171819202122232426

10

VDD

P3.5

P3.4

P3.3

P3.1

P3.0P1.0P1.1P1.2P1.3P1.4P1.5P1.6P1.7

20

40 31 EA

VC

CG

ND

P3.2

XTAL1

XTAL2

/RESET

S1

SW-PB

C1510UF

Y112MHZ

C13

27PF

C14

27PFS2

SW-PB

R1

10K

VDD9

10

11

12

13

14

15

18

1912345678

NC

BS2

BS0

BS111

12

EASTRISING TECHNOLOGY CO.,LTD.ER-OLED096-1 A0

1Javen

Title

NumberSizeA

Date: 03-Feb-2010 Sheet of

Revision

File Drawn By

The Parallel (6800 Series MCU)Series MCU)Reference Example

The Serial (4line SPI)Reference Example

S1

SW-PBS1

SW-PB

R2 10K

R3 10KVDD

VDD

PAUSE

RESET

CONTRAST +

CONTRAST -

38

37

P0.1

P0.2

CAP1P

CAP1N

CAP2N

CAP2P

VCC Generated by Internal DC/DC Circuit

C21uf

C11uf

4

5

2

3

6 VBAT+3.6VC31uf

7 NC8 VSS

C41uf 9 VDD+3.3V

NC 30VLSS

VCC

VCOMH

IREF

C52.2uf

C64.7uf

R390K

26

27

28

29

+3.3V

MCU

C/D#

CS#

R/W#

E_RD#

RES#

DB0DB1DB2DB3DB4DB5

SSD1306

AT89C52

Data/Instruction selected pin

Chip selected when low

Read/Write signal

Enable signal

Reset input

DataDataDataDataDataDataDataData

113

14

15

16

171819202122232426

10

VDD

P3.5

P3.4

P3.3

P3.1

P3.0P1.0P1.1P1.2P1.3P1.4P1.5P1.6P1.7

20

40 31 EA

VC

CG

ND

P3.2

XTAL1

XTAL2

/RESET

S1

SW-PB

C1510UF

Y112MHZ

C13

27PF

C14

27PFS2

SW-PB

R1

10K

VDD9

10

11

12

13

14

15

18

1912345678

NC

BS2

BS0

BS111

12

S1

SW-PBS1

SW-PB

R2 10K

R3 10KVDD

VDD

PAUSE

RESET

CONTRAST +

CONTRAST -

38

37

P0.1

P0.2

CAP1P

CAP1N

CAP2N

CAP2P

VCC Generated by Internal DC/DC Circuit

C21uf

C11uf

4

5

2

3

6 VBAT+3.6VC31uf

7 NC8 VSS

C41uf 9 VDD+3.3V

NC 30VLSS

VCC

VCOMH

IREF

C52.2uf

C64.7uf

R390K

26

27

28

29

+3.3V

MCU

C/D#

CS#

R/W#

E_RD#

RES#

DB0DB1DB2DB3DB4DB5

SSD1306

AT89C52

Data/Instruction selected pin

Chip selected when low

Reset input

SDINSCLK

113

14

15

16

171819202122232425

10

VDD

P3.5

P3.4

P3.3

P3.1

P3.0P1.0P1.1P1.2P1.3P1.4P1.5P1.6P1.7

20

40 31 EA

VC

CG

ND

P3.2

XTAL1

XTAL2

/RESET

S1

SW-PB

C1510UF

Y112MHZ

C13

27PF

C14

27PFS2

SW-PB

R1

10K

VDD9

10

11

12

13

14

15

18

1912345678

NC

BS2

BS0

BS111

12

S1

SW-PBS1

SW-PB

R2 10K

R3 10KVDD

VDD

PAUSE

RESET

CONTRAST +

CONTRAST -

38

37

P0.1

P0.2

CAP1P

CAP1N

CAP2N

CAP2P

VCC Generated by Internal DC/DC Circuit

C21uf

C11uf

4

5

2

3

6 VBAT+3.6VC31uf

7 NC8 VSS

C41uf 9 VDD+3.3V

NC 30VLSS

VCC

VCOMH

IREF

C52.2uf

C64.7uf

R390K

26

27

28

29

DB6DB7

DB6DB7

NC

The Serial (3line SPI)Reference Example

MCU

C/D#

CS#

R/W#

E_RD#

RES#

DB0DB1DB2DB3DB4DB5

SSD1306

AT89C52

Chip selected when low

Reset input

SDINSCLK

113

14

15

16

171819202122232426

10

VDD

P3.5

P3.4

P3.3

P3.1

P3.0P1.0P1.1P1.2P1.3P1.4P1.5P1.6P1.7

20

40 31 EA

VC

CG

ND

P3.2

XTAL1

XTAL2

/RESET

S1

SW-PB

C1510UF

Y112MHZ

C13

27PF

C14

27PFS2

SW-PB

R1

10K

VDD9

10

11

12

13

14

15

18

1912345678

NC

BS2

BS0

BS111

12

S1

SW-PBS1

SW-PB

R2 10K

R3 10KVDD

VDD

PAUSE

RESET

CONTRAST +

CONTRAST -

38

37

P0.1

P0.2

CAP1P

CAP1N

CAP2N

CAP2P

VCC Generated by Internal DC/DC Circuit

C21uf

C11uf

4

5

2

3

6 VBAT+3.6VC31uf

7 NC8 VSS

C41uf 9 VDD+3.3V

NC 30VLSS

VCC

VCOMH

IREF

C52.2uf

C64.7uf

R390K

26

27

28

29

DB6DB7

NC

+3.3V

The Serial (I2C)Reference Example

MCU

C/D#

CS#

R/W#

E_RD#

RES#

DB0DB1DB2DB3DB4DB5

SSD1306

AT89C52

Reset input

SDASCL

113

14

15

16

171819202122232426

10

VDD

P3.5

P3.4

P3.3

P3.1

P3.0P1.0P1.1P1.2P1.3P1.4P1.5P1.6P1.7

20

40 31 EA

VC

CG

ND

P3.2

XTAL1

XTAL2

/RESET

S1

SW-PB

C1510UF

Y112MHZ

C13

27PF

C14

27PFS2

SW-PB

R1

10K

9

10

11

12

13

14

15

18

1912345678

NC

BS2

BS0

BS111

12

S1

SW-PBS1

SW-PB

R2 10K

R3 10KVDD

VDD

PAUSE

RESET

CONTRAST +

CONTRAST -

38

37

P0.1

P0.2

CAP1P

CAP1N

CAP2N

CAP2P

VCC Generated by Internal DC/DC Circuit

C21uf

C11uf

4

5

2

3

6 VBAT+3.6VC31uf

7 NC8 VSS

C41uf 9 VDD+3.3V

NC 30VLSS

VCC

VCOMH

IREF

C52.2uf

C64.7uf

R390K

26

27

28

29

DB6DB7

+3.3V

R10K R

10K

VDD

SSD1306

1 NC

CAP1P

CAP1N

CAP2N

CAP2P

4

5

2

3

6 VBAT

C22.2uf

7 NC8 VSS

C10.1uf 9 VDD+3.3V

NC 30VLSS

VCC

VCOMH

IREF

C4

2.2uf

C54.7uf

R560K

26

27

28

29

VCC Supplied Externally

SA0

C4

2.2uf

+9.5V

ER-OLED096-1

ER-OLED096-1 ER-OLED096-1

ER-OLED096-1

R3

R3R3

10K

10K10K

PAUSE

PAU

SEPA

USE

+3.6V

+3.6V+3.6V

C3

C3C3

1uf

1uf1uf

C4

C4C4

C4

C4C4

1uf

1uf1uf

BS2

BS2BS2

BS0

BS0BS0

BS1

BS1BS1

ER-OLED096-1

ER-O

LED096-1

ER-O

LED096-1

ER-OLED096-1

ER-O

LED096-1

ER-O

LED096-1

+3.3V

+3.3V+3.3V

+3.6V

+3.6V+3.6V

C3

C3C3

1uf

1uf1uf

C4

C4C4

1uf

1uf1uf

C3

C3C3

1uf

1uf1uf

CAP1P

CAP1P

CAP1P

CAP1N

CAP1N

CAP1N

CAP2N

CAP2N

CAP2N

CAP2N

CAP2N

CAP2N

CAP2N

CAP2N

CAP2N

The Serial (4line SPI)Reference Example

The Serial (4line SPI)Reference Example

The Serial (4line SPI)Reference Example

VCC Generated by Internal DC/DC Circuit

VCC G

enerated by Internal DC/D

C CircuitV

CC Generated by Internal D

C/DC Circuit

VCC Generated by Internal DC/DC Circuit

VCC G

enerated by Internal DC/D

C CircuitV

CC Generated by Internal D

C/DC Circuit

The Serial (4line SPI)Reference Example

The Serial (4line SPI)Reference Example

The Serial (4line SPI)Reference Example

VCC Generated by Internal DC/DC Circuit

VCC G

enerated by Internal DC/D

C CircuitV

CC Generated by Internal D

C/DC Circuit

R3

R3R3

SW-PB

SW-PB

SW-PB

SW-PB

SW-PB

SW-PB

S1

S1S1

SW-PB

SW-PB

SW-PB

SW-PB

SW-PB

SW-PB

10K

10K10K

CONTRAST -

CON

TRAST -

CON

TRAST -

CONTRAST +

CON

TRAST +

CON

TRAST +

CONTRAST +

CON

TRAST +

CON

TRAST +

SW-PB

SW-PB

SW-PB

SW-PB

SW-PB

SW-PB

SW-PB

SW-PB

SW-PB

CONTRAST +

CON

TRAST +

CON

TRAST +

SW-PB

SW-PB

SW-PB

SW-PB

SW-PB

SW-PB

SW-PB

SW-PB

SW-PB

R1

R1R1

10K

10K10K

10K

10K10K

VDD

VD

DV

DD

CONTRAST +

CON

TRAST +

CON

TRAST +

CONTRAST +

CON

TRAST +

CON

TRAST +

CONTRAST +

CON

TRAST +

CON

TRAST +

CONTRAST +

CON

TRAST +

CON

TRAST +

RESET

RESETRESET

Interfacing OLED Display to the AT89LV52 MCU

buy-display.comEastRising