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Interface traps and random dopants induced characteristic fluctuations in emerging MOSFETs Yiming Li a,b,, Hui-Wen Cheng b , Yung-Yueh Chiu b a Department of Electrical Engineering, National Chiao Tung University, Hsinchu 300, Taiwan b Institute of Communications Engineering, National Chiao Tung University, Hsinchu 300, Taiwan article info Article history: Received 24 February 2011 Received in revised form 20 March 2011 Accepted 23 March 2011 Available online 30 March 2011 Keywords: High-j/metal gate Interface trap Random dopant Threshold voltage fluctuation Interface trap fluctuation Random dopant fluctuation Combination of interface trap and random dopant fluctuations abstract In this work, we study the effect of interface traps (ITs) and random dopants (RDs) on characteristics of 16-nm MOSFETs. Totally random generated devices with 2D ITs between the interface of silicon and HfO 2 film as well as 3D RDs inside the silicon channel are simulated. Fluctuations of threshold voltage and on/ off state current for devices with different EOT of insulator film are analyzed and discussed. The results of this study indicate ITs and RDs statistically correlate to each other and RDs govern device variability, compared with the influence of ITs. Notably, the position of ITs and RDs induces rather different fluctu- ation in spite of the same number of ITs and RDs are investigated. Ó 2011 Elsevier B.V. All rights reserved. 1. Introduction Characteristic variability of nano-CMOS devices increases as de- vice dimension reduces [1–5], for example, the RD-induced thresh- old voltage fluctuation (rV th ) up to 40 mV for 20-nm planar CMOS has been experimentally quantified [3]. RD fluctuation (RDF) has been recognized as one of the major limitations in device scaling; recently, high-j/metal gate (HKMG) plays a key technology to re- duced intrinsic parameter fluctuation, and leakage current for sub-45-nm generations [3,4]. However, the generation of ITs on the interface of silicon and high-j introduces a new source of fluc- tuation for the degradation of device characteristics [6–10]. In this work, we intensively study the distributions of ITs and RDs induced characteristic fluctuation of 16-nm MOSFETs using an experimen- tally calibrated 3D device simulation. 2D ITs on the interface of sil- icon and HfO 2 film and 3D RDs inside the silicon channel are simultaneously considered in the 3D device simulation [3,4]. Phys- ical findings on rV th and variability of I on /I off versus the number and position of ITs and/or RDs are discussed. 2. Simulation methodology The validated performance of studied HKMG device, according to ITRS roadmap for low operating power, is experimentally quan- tified in our recent study [3]. Note that the threshold voltage of 16- nm N-MOSFET is equal to 250 mV. The devices we examined are the 16-nm planar MOSFETs (width: 16 nm) with amorphous-based TiN/HfO 2 gate stacks; an EOT of 0.8 and 1.2 nm are shown in Fig. 1(a). For the simulation of IT fluctuation (ITF), we first generate 753 acceptor-like traps in a large plane in Fig. 1(b), where the trap’s concentration in the large plane is around 1.5 10 12 cm 2 based upon experimental characterization, and the total number of gen- erated traps mainly follows the Poisson distribution. Then, the sta- tistically generated large plane is partitioned into many sub- planes, where the number of traps in the sub-planes may vary from one to eight and the average is four. The energy of each trap on each sub-plane is assigned according to the distribution of trap density [6–9]. We explore the density of ITs varying from 5 10 11 to 5 10 12 cm 2 . We repeat this process until all sub-re- gions are assigned. RDs’ number and position in the channel region are statistically generated discrete dopants, as shown in Fig. 1(c), which are also incorporated into the 3D device simulation and per- formed on our parallel computing system. The detail of RDF simu- lation technique was reported in our previous works [3,4]. Therefore, about 200 samples are generated for the 3D device 0167-9317/$ - see front matter Ó 2011 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2011.03.040 Corresponding author at: Deptartment of Electrical Engineering, National Chiao Tung University, Hsinchu 300, Taiwan. Tel.: +886 3 5712121x52974; fax: +886 3 5726639. E-mail address: [email protected] (Y. Li). Microelectronic Engineering 88 (2011) 1269–1271 Contents lists available at ScienceDirect Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee

Interface traps and random dopants induced characteristic fluctuations in emerging MOSFETs

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Microelectronic Engineering 88 (2011) 1269–1271

Contents lists available at ScienceDirect

Microelectronic Engineering

journal homepage: www.elsevier .com/locate /mee

Interface traps and random dopants induced characteristic fluctuationsin emerging MOSFETs

Yiming Li a,b,⇑, Hui-Wen Cheng b, Yung-Yueh Chiu b

a Department of Electrical Engineering, National Chiao Tung University, Hsinchu 300, Taiwanb Institute of Communications Engineering, National Chiao Tung University, Hsinchu 300, Taiwan

a r t i c l e i n f o a b s t r a c t

Article history:Received 24 February 2011Received in revised form 20 March 2011Accepted 23 March 2011Available online 30 March 2011

Keywords:High-j/metal gateInterface trapRandom dopantThreshold voltage fluctuationInterface trap fluctuationRandom dopant fluctuationCombination of interface trap and randomdopant fluctuations

0167-9317/$ - see front matter � 2011 Elsevier B.V. Adoi:10.1016/j.mee.2011.03.040

⇑ Corresponding author at: Deptartment of ElectricaTung University, Hsinchu 300, Taiwan. Tel.: +886 3 55726639.

E-mail address: [email protected] (Y. Li).

In this work, we study the effect of interface traps (ITs) and random dopants (RDs) on characteristics of16-nm MOSFETs. Totally random generated devices with 2D ITs between the interface of silicon and HfO2

film as well as 3D RDs inside the silicon channel are simulated. Fluctuations of threshold voltage and on/off state current for devices with different EOT of insulator film are analyzed and discussed. The results ofthis study indicate ITs and RDs statistically correlate to each other and RDs govern device variability,compared with the influence of ITs. Notably, the position of ITs and RDs induces rather different fluctu-ation in spite of the same number of ITs and RDs are investigated.

� 2011 Elsevier B.V. All rights reserved.

1. Introduction

Characteristic variability of nano-CMOS devices increases as de-vice dimension reduces [1–5], for example, the RD-induced thresh-old voltage fluctuation (rVth) up to 40 mV for 20-nm planar CMOShas been experimentally quantified [3]. RD fluctuation (RDF) hasbeen recognized as one of the major limitations in device scaling;recently, high-j/metal gate (HKMG) plays a key technology to re-duced intrinsic parameter fluctuation, and leakage current forsub-45-nm generations [3,4]. However, the generation of ITs onthe interface of silicon and high-j introduces a new source of fluc-tuation for the degradation of device characteristics [6–10]. In thiswork, we intensively study the distributions of ITs and RDs inducedcharacteristic fluctuation of 16-nm MOSFETs using an experimen-tally calibrated 3D device simulation. 2D ITs on the interface of sil-icon and HfO2 film and 3D RDs inside the silicon channel aresimultaneously considered in the 3D device simulation [3,4]. Phys-ical findings on rVth and variability of Ion/Ioff versus the number andposition of ITs and/or RDs are discussed.

ll rights reserved.

l Engineering, National Chiao712121x52974; fax: +886 3

2. Simulation methodology

The validated performance of studied HKMG device, accordingto ITRS roadmap for low operating power, is experimentally quan-tified in our recent study [3]. Note that the threshold voltage of 16-nm N-MOSFET is equal to 250 mV. The devices we examined arethe 16-nm planar MOSFETs (width: 16 nm) with amorphous-basedTiN/HfO2 gate stacks; an EOT of 0.8 and 1.2 nm are shown inFig. 1(a). For the simulation of IT fluctuation (ITF), we first generate753 acceptor-like traps in a large plane in Fig. 1(b), where the trap’sconcentration in the large plane is around 1.5 � 1012 cm�2 basedupon experimental characterization, and the total number of gen-erated traps mainly follows the Poisson distribution. Then, the sta-tistically generated large plane is partitioned into many sub-planes, where the number of traps in the sub-planes may vary fromone to eight and the average is four. The energy of each trap oneach sub-plane is assigned according to the distribution of trapdensity [6–9]. We explore the density of ITs varying from5 � 1011 to 5 � 1012 cm�2. We repeat this process until all sub-re-gions are assigned. RDs’ number and position in the channel regionare statistically generated discrete dopants, as shown in Fig. 1(c),which are also incorporated into the 3D device simulation and per-formed on our parallel computing system. The detail of RDF simu-lation technique was reported in our previous works [3,4].Therefore, about 200 samples are generated for the 3D device

16nm

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1 2 3 4 5 6 7 8His

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Fig. 1. (a) The source of randomness (pink dots are interface traps and blue dots are discrete dopants) and simulation settings for fluctuations of random ITs and RDs. (b) Wefirst generate 753 acceptor-like traps in a large plane, where the trap’s concentration in the plane is around 1.5 � 1012 cm�2 and the total number of generated traps followthe Poisson distribution. The energy of each trap on the plane is assigned according to distribution of trap’s density. Then the entire plane is partitioned into sub-planes (size:16 nm � 16 nm), where the number of traps in all sub-planes may vary from one to eight and the average number is four. (c) Discrete dopants randomly distributed in(96 nm)3 cube with the average concentration of 1.5 � 1018 cm�3. There will be 1327 dopants within the cube and dopants vary from 0 to 14 (the average number is six) for all216 sub-cubes. The size of each sub-cube is (16 nm)3. The total sub-cubes and sub-planes are then mapped into device’s 3D channel and 2D surface for RDs and ITs’ position/number-sensitive simulation (b). (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)

Fig. 2. The on-state (VG = VD = 0.8 V) electric field and potential distribution of thechannel surface extracted from one of simulated 16-nm transistors, whereEOT = 0.8 nm. The device fluctuated by two random ITs at Si/HfO2 oxide interface.The traps between the interface of Si and high-j oxide irregularly twist the localelectric field and the potential, where the barrier is affected by ITF clearly.

Fig. 3. The on-state (VG = VD = 0.8 V) potential distribution of the channel surfacefrom one of simulated 16-nm transistors, where EOT = 0.8 nm. The device fluctu-ated by six random ‘‘ITs + RDs’’ simultaneously. The interactions of two random ITs(at Si/HfO2 oxide interface) and four random RDs (locating inside the silicon channelbelow the channel surface) on the band profile is clearly shown in the right plot.

1270 Y. Li et al. / Microelectronic Engineering 88 (2011) 1269–1271

simulation to estimate the ITs and RDs induced characteristic fluc-tuation in MOSFETs.

3. Results and discussion

Fig. 2 shows the on-state (VG = 0.8 V and VD = 0.8 V) electric fieldand the potential distributions of the channel surface extractedfrom one of about 200 simulated transistors, where they are fluc-tuated by random ITs. The traps between the interface of Si andhigh-j irregularly twist the local electric field and the potential.

Notably, the barrier is affected by ITF clearly. The barrier inducedby RDs was discussed in our recent work [3]. Fig. 3 shows theon-state potential distribution of the channel surface extractedfrom one of about 200 simulated transistors fluctuated by random‘‘ITs + RDs’’ simultaneously. The interaction effect of ‘‘ITs + RDs’’ onthe band profile is clearly shown. Fig. 4(a) and (b) shows the totallyrandom ‘‘ITs + RDs’’ fluctuated ID–VG curves simultaneously for N-MOSFETs with EOT of 0.8 and 1.2 nm, respectively. The plot ofIon–Ioff characteristics for ‘‘ITs + RDs’’-induced fluctuations is shownin Fig. 4(c). For devices with similar Ion, the maximum difference ofIoff is declined from approximately 13.3 to 6.2 nA as the EOT isscaled from 1.2 to 0.8 nm. The result shows that the device with

Ion (A)2e-6 4e-6 6e-6 8e-6 1e-5

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Fig. 4. (a) and (b) The totally random ITs- and RDs-induced fluctuations of ID–VG

curves simultaneously for N-MOSFETs with EOT of 0.8 and 1.2 nm, respectively,where the red lines indicate the nominal cases (i.e., the 3D simulation without ITFand RDF). (c) The Ion–Ioff characteristics of about 200 simulated transistorsfluctuated by ITs and RDs. For devices with similar Ion, the maximum differenceof Ioff is declined from approximately 13.3 to 6.2 nA as the EOT is scaled from 1.2 to0.8 nm respectively.

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EOT 0.8 nmEOT 1.2 nmEOT 0.8 nmEOT 1.2 nm

Fig. 5. (a) and (b) The large-scale statistically computed Vth as a function of randomtraps’ and dopants’ number for the N-MOSFET devices with EOT of 0.8 and 1.2 nm,respectively. The random position effect of ITs- and RDs-induces rather differentfluctuation in spite of the same number of ITs and RDs, as marked in the inset.

Table 1Summary of the ITs-, RDs- and ‘‘ITs + RDs’’-induced threshold voltage fluctuation. Wenote that the rVth,ITs+RDs is smaller than the result of statistically independentidentical distribution

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffir2Vth;ITs þ r2Vth;RDs

pdue to a charges’ correlation between

random ITs and RDs in N-MOSFETs devices with EOT of 0.8 and 1.2 nm, respectively.

(nm) rVth,ITs (mV) rVth,RDs (mV) rVth,ITs+RDs (mV)

EOT = 0.8 26.3 43 45.4EOT = 1.2 31.4 47.6 56.2

Y. Li et al. / Microelectronic Engineering 88 (2011) 1269–1271 1271

EOT of 1.2 nm possesses sizeable ITF and RDF due to the weakenedmetal gate controllability. The large scale statistically simulatedthreshold voltage as a function of random interface traps’ and ran-dom dopants’ number for the 16-nm N-MOSFET devices is shownin Fig. 5(a) and (b). Compared with ITs-number-induced rVth, theresults imply that RDF influence rVth notably. From RDs-number

point of view, the equivalent channel doping concentration in-creases when the dopant number increases; this substantially al-ters the threshold voltage and the on/off state currents.Additionally, the position of ITs- and RDs-induces rather differentfluctuation in spite of the same number of traps and dopants, asmarked in inset of Fig. 5(a) and (b). Furthermore, the magnitudeof spreading distance increases as the number of dopants in-creases. Table 1 summarizes the ITs-, RDs- and ‘‘ITs + RDs’’-inducedthreshold voltage fluctuation; device with EOT of 0.8 nm exhibitsrVth,ITs=26.3 mV, rVth,RDs = 43 mV and rVth,ITs+RDs = 45.4 mV. Wenote that rVth,ITs+RDs = 45.4 mV is smaller than the result of statisti-cally independent identical distribution

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffir2Vth;ITs þ r2Vth;RDs

50:4 mV due to a charges’ correlation between ITF and RDF in N-MOSFETs. Physically, it implies that ITF and RDF should be consid-ered at the same time for simulating HKMG device. Similarly, fordevice with EOT = 1.2 nm they are 31.4, 47.6 and 56.2 mVrespectively.

4. Conclusions

In this study, we have explored the ITF and/or RDF with EOT of0.8 and 1.2 nm on 16-nm HKMG planar MOSFETs. We have esti-mated the Vth as a function of trap number and dopant numberfor the N-MOSFET devices and ITs and RDs position induced differ-ent fluctuations of characteristics in spite of the same number ofdopants and traps. The rVth induced by ITs is lower than that ofRDs owing to a low density of acceptor-like interface traps. RDFdominates the characteristic fluctuation when considers both theITF and RDF together. We currently calibrate the ranges of ITs’ den-sity and energy with experimentally measured results.

Acknowledgments

This work was supported in part by National Science Council(NSC), Taiwan under Contract No. NSC-99-2221-E-009-175 andby TSMC, Hsinchu, Taiwan under a 2010-2011 grant.

References

[1] T. Mizuno, J. Okamura, A. Toriumi, IEEE Trans. Electron Devices 41 (1994)2216–2221.

[2] G. Roy, A.R. Brown, F. Adamu-Lema, S. Roy, A. Asenov, IEEE Trans. ElectronDevices 53 (2006) 3063–3070.

[3] Y. Li, S.-M. Yu, J.-R. Hwang, F.-L. Yang, IEEE Trans. Electron Devices 55 (2008)1449–1455.

[4] Y. Li, C.-H. Hwang, T.-Y. Li, M.-H. Han, IEEE Trans. Electron Devices 57 (2010)437–447.

[5] G. Panagopoulos, K. Roy, IEEE Trans. Electron Devices 58 (2011) 392–403.[6] A. Appaswamy, P. Chakraborty, J. Cressler, IEEE Electron Device Lett. 31 (5)

(2010) 387–389.[7] P. Andricciola, H.P. Tuinhout, B. De Vries, N.A.H. Wils, A.J. Scholten, D.B.M.

Klaassen, In: IEDM Tech. Dig. 711–714 (2009).[8] P.K. Hurley, K. Cherkaoui, S. McDonnell, G. Hughes, A.W. Groenland,

Microelectron. Reliab. 47 (2007) 1195–1201.[9] M. Cassé1, K. Tachi1, S. Thiele, T. Ernst, Appl. Phys. Lett. 96 (2010) 123506.

[10] M.F. Bukhori, S. Roy, A. Asenov, IEEE Trans Electron Devices Dev. 57 (2010)795–803.