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Interconnect Complexity-Aware FPGA Interconnect Complexity-Aware FPGA Placement Using Rent’s RulePlacement Using Rent’s Rule
G. Parthasarathy
Malgorzata Marek-Sadowska
Arindam Mukherjee
Amit Singh
University of California, Santa Barbara
9/7/00 2
OutlineOutline
Motivation
Rent’s Parameter
Analysis
New Placement Algorithm
Results
Conclusions
Future Work
9/7/00 3
MotivationMotivation
80-90% of die area = interconnectsincreased programmability
routing resource utilization (RRU) is low 100% logic utilization
unused LUTs -> better RRU
maybe at the cost of increased area?
Maybe not!
interconnect complexity guided placement - Rent’s
parameter
9/7/00 4
Rent’s ParameterRent’s Parameter
Common measure for Interconnect Complexity
Nio = K NgP
Nio – Number of IO pins/terminals external to the logic partition
K - Average number of interconnections per LUT
Ng – Number of LUTs in a logic partition
p – Rent’s parameter after E.F.Rent
E.F.Rent,1960
Landman, Russo, 1971
9/7/00 5
Local Rent’s parameter Pld
Complexity Varies across design.
Solution – Use local interconnect complexity measure based in interconnect length distributions. (Van Marck et al.,95)
Reduces to Landman’s Rent’s exponent for uniform design at the top level
9/7/00 6
Rent’s ParameterRent’s Parameter
Van Marck, Stroobandt, Campenhout, 1995
p : (log Ni) / (log Li)p – Rent’s parameter
Li - length of a net
Ni - number of nets of length Li
9/7/00 8
AnalysisAnalysis Consists of LUTs, connection boxes and switch-boxes
Regular 2-D mesh array of unit tiles
FPGA ArchitectureFPGA Architecture
9/7/00 9
FPGA Fabric Min-Size-Up
Definitions Pa – Rent’s parameter for Architecture
Pd – Rent’s parameter for Design
Case 1: Pd <= Pa Design routable. Try to get best placement.
Case 2: Pd > Pa Design Un-routable. Need more resources.
Solution – Increase FPGA fabric size by scaling factor C
Pd
PaPd
g
Pa
gPd
g
NC
)K(C.NK NNio
9/7/00 10
New Placement AlgorithmNew Placement Algorithm
Simulated Annealing - VPR
scale-up fabric by C
modify VPR’s existing Cost Function
| pld - pl
a | used as scaling factor for bounding-box
based cost function
uniform distribution of interconnect complexity
n
net q(i) Function Crossing TrackBi)ox_length(Bounding_bpl
apld
1i
(1+ )
9/7/00 11
Place-and-Route CAD Flow
Generate BenchmarksKnown Pd
Uniform Distribution
Map to Net-list
Place-and-routeVPR
MVPR
Compare
pld pl
a> ?
scale-up fabric by C
yes
no
use MVPR
placed and routed design
9/7/00 12
Results - Results - BenchmarksBenchmarks
gnl generated ckts
random ckts - ISCAS benchmarks
p1d
p2d p3
d
p4d
p5d
p6d
p1d = p2
d = p3d
= p4d = p5
d = p6d
9/7/00 13
Rent’s Parameter for Architecture1
Segmentation = 1, channel width = 7, Pa = 0.62
ResultsResults
9/7/00 14
Rent’s parameter for Architecture2
Segmentation = 2, channel width = 7, Pa = 0.64
9/7/00 15
Routing Utilization for seg = 1
MVPR produces better
routing utilization: 15-25% better
AvailableSegment Wire#
Used Segments Wire#nUtilizatio Routing
9/7/00 16
Routing Utilization for seg = 1:2
MVPR produces better
routing utilization: 10-15% better
AvailableSegment Wire#
Used Segments Wire#nUtilizatio Routing
9/7/00 17
Routing Utilization for seg = 2
MVPR produces only
minimally better routing
utilization: 1-5% better
AvailableSegment Wire#
Used Segments Wire#nUtilizatio Routing
9/7/00 18
Routing Overhead Results (MVPR vs VPR) seg = 1
Total Routing Area
0.00E+00
2.00E+07
4.00E+07
6.00E+07
8.00E+07
1.00E+08
1.20E+08
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Rent's parameter P_d
Ro
uti
ng
are
a in
tra
nsis
tor
eq
vts
MVPR
VPR
results follow trend for changes in architecture
9/7/00 19
CLB Area Utilization (MVPR v/s VPR) seg = 1
results follow trend for changes in architecture
logic area utilization falls with increasing Pd
9/7/00 20
MVPR over VPR for gnl generated cktsMVPR over VPR for gnl generated ckts
25% higher RRU
10-15% lower Area
9/7/00 22
MVPR over VPR for ISCAS cktsMVPR over VPR for ISCAS ckts
same track utilization
5% lower average wire length
2-5% higher RRU
10-15% higher Area
9/7/00 23
ConclusionsConclusions
PlusesNew Cost Function
Minimum size fabric derived for Pd > Pa
Min-Area <-> Max-RRU
MinusesErrors in the estimation of Pd and Pa
second-order effects
Non-uniform interconnect complexities
9/7/00 24
Future WorkFuture Work
Modifying MVPR non-uniform interconnect complexity
timing/power-dissipation and complexity-aware
FPGA placement
correlating track segmentation with accurate
estimation of Rent’s parameter