7/30/2019 intel 80386

1/17

Pin Description of 80386dx.

Introduction to 80386dx Architecture.

7/30/2019 intel 80386

2/17

Introduction to the 80386

Microprocessor

the 80386DX is packaged in a 132-pin PGA.

80386DX addresses 4G bytes of memory

through its 32-bit data bus and 32-bit

address.

7/30/2019 intel 80386

3/17

7/30/2019 intel 80386

4/17

7/30/2019 intel 80386

5/17

Function of each 80386dx group of

pins:

A31 to A2 - Address bus connections address

any of the 4G bytes memory locations in the

80386 memory system.

A0 - A1 are encoded in the Bus Enable BE0-

BE3 to select any or all of the four bytes in a

32-bit wide memory location.

7/30/2019 intel 80386

6/17

Bank Enable Signals (BE3 - BE0)

These signals select the access of abyte, word, or double word ofdata.

These signals are generatedinternally by the microprocessorfrom address bits A1 and A0.

The 32- bit data bus supported by80386 and the memory system of80386 can be viewed as a 4- byte

wide memory access mechanism.The 4 byte enable lines BE

0to BE

3,

may be used for enabling these 4blanks. Using these 4 enable signallines, the CPU may transfer 1 byte/ 2 / 3 / 4 byte of datasimultaneously.

7/30/2019 intel 80386

7/17

Data Bus (D31 - D0)

Data bus connections transfer data between

microprocessor and its memory and I/O

system.

These 32 lines act as bidirectional data bus

during different access cycles.

7/30/2019 intel 80386

8/17

Bus Cycle Definition Pins

M/IO -a)This output pindifferentiates betweenmemory & I/O cycles.

b)The pin selects a memorydevice when at logic 1 andan I/O device in case of logic0.

W/R -

a) This pin distinguishes theread and write cycles fromone another.b) It indicates that thecurrent bus cycle is a writewhen at logic 1 and a readat logic 0.

7/30/2019 intel 80386

9/17

Bus Cycle Definition Pins

D/C - Data/Control Pin

a) This pin distinguishes a data transfer cycle from a machine control cycle.

b) Indicates that the data bus contains data for or from memory of I/O when at

logic 1.

c) At logic 0, microprocessor is halted or executes an interrupt acknowledge.

LOCK - this pin enables the CPU from preventing other bus masters from gaining

control of the system bus.

7/30/2019 intel 80386

10/17

Bus Control Pins

ADS - Address Data Strobe.

a) The address status output pin indicates that the address bus and bus cycle

definition pins are carrying the respective valid signals.

b) This signal becomes active whenever the 80386 has issued a valid memory or I/O

address.

NA - Next Address causes the 80386 to output the address of the next instruction or

data in the current bus cycle. This pin is used for pipelining the address.

7/30/2019 intel 80386

11/17

Bus Control Pins

BS16 - Bus Size 16 pin selectseither a 32 bit data bus (BS16 = 1)or a 16 bit data bus (BS16 = 0)a) In most cases, 80386DX isoperated on 16 bit data bus.

b) The bus size16 input pin allowsthe interfacing of 16 bit deviceswith the 32 bit wide 80386 databus.

READY - The ready signalsindicates to the CPU that theprevious bus cycle has been

terminated and the bus is readyfor the next cycle. The signal isused to insert WAIT states in a buscycle and is useful for interfacingof slow devices with CPU.

7/30/2019 intel 80386

12/17

Interrupts

Interrupt is a signal to the processoremitted by hardware or softwareindicating an event that needsimmediate attention.

An interrupt alerts the processor to ahigh-priority condition requiring theinterruption of the current code theprocessor is executing.

The processor responds bysuspending its current activities,saving its state, and executing a small

program called an interrupt handler(or interrupt service routine, ISR) todeal with the event.

This interruption is temporary, andafter the interrupt handler finishes,the processor resumes execution ofthe previous thread.

7/30/2019 intel 80386

13/17

Interrupt Pins

INTR - An Interrupt Request is used by external circuitry to request an interrupt.

This interrupt pin is a maskable interrupt, that can be masked using the IF of the flag register.

NMI - A Non-Maskable interrupt requests a non-maskable interrupt as it did not in the earlier

versions of the microprocessor.

RESET - A high at this input pin suspends the current operation and restart the execution fromthe starting location. (location for 80386dx is FFFFFFF0H.)

7/30/2019 intel 80386

14/17

Bus Arbitration Pins

HOLD - The bus hold input pin enables the other bus masters to gain control of the

system bus if it is asserted.

Hold requests a DMA action.

- Direct memory access (DMA) is a feature of modern computers that allows certain

hardware subsystems within the computer to access system memory independently of

the central processing unit (CPU).

HLDA - Hold Acknowledge indicates that the 80386 is currently in hold condition.

7/30/2019 intel 80386

15/17

Co-process or Signaling

BUSY - The busy input signalindicates to the CPU that thecoprocessor is busy with theallocated task.This input is used by the WAIT

instruction.

ERROR - Indicates to themicroprocessor that an error isdetected by the coprocessorwhile executing an instruction.

PEREQ - The CoprocessorRequest asks the 80386 torelinquish control and is a directconnection to the 80387arithmetic coprocessor.

7/30/2019 intel 80386

16/17

Clock Times 2 & Power Connections

CLK2 :This input pin provides the basic system clock timing for the operation

of 80386.

- Clock Times 2 is driven by a clock signal that is twice the operating

frequency of the 80386.

VCC: These are system power supply lines.

VSS: These return lines for the power supply.

7/30/2019 intel 80386

17/17

References

The 80386 and 80486 Microprocessor -

Barry B. Brey.

NPTEL Introduction to 80386 Architecture

PDF.

Wikipedia - for some definitions and

80386DX Image.