Integrated Readout Electronics for the PbW04 Photon Spectrometer'

M. L. Simpson, G. T. Alley, T. Awes, C. L. Britton, W. Bryan, M. S. Emery,

Oak Ridge National Laboratory

- f*. '7 ?, F,f ;: 0 M. N. Ericson, F. P h i l , P. Stankus, A. L. Wintenberg and G. R. Yogng- w

R. G. Jackson and M. Xu University of Tennessee

V. Manko, Yu. Sibiryak, A. Tsvetkov and A. Vinogradov RSC Kurchatov

ABSTRACT

A proposed readout system for the ALICE PbW04 photon spectrometer is presented. In one proposed implementation, light will be detected from each end of the crystals by PIN photodiodes and this signal will be amplified by charge-sensitive amplifiers. The 73,728 channel readout system will accept the preamplifier signals and deliver digitized data to the data collection modules. A readout board will consist of 8-channel, custom front-end chips which form energy and timing signals, and board- level control and communication circuits. Many of the subcircuits proposed for this spectrometer have been developed for use in other applications. The performance of these circuits is shown.

1.0 INTRODUCTION

The PbWO4 calorimeter of the ALICE detector is designed to detect the prompt photons to provide direct information on the partonic, early phases of the heavy-ion interaction [l]. The goal is to measure all the photons over a large enough solid angle to reconstruct both no's and q's [l]. In one proposed implementation, the detector will consist of 36,864 2.2 cm X 2.2 cm X 18 cm crystals that are longitudinally segmented. In this case, the light will be read from both ends of the detector requiring twice as many readout channels. If the crystals are not segmented, the light will only be collected at one end of the crystal.

The photodiode signal will be amplified by a charge sensitive preamplifier and then processed by the readout system. The purpose of the readout systems is to produce energy and timing measurements from the preamplifier output signals, as well as energy sums for the level-1 triggei system.

'Research sponsored by the U. S. Depment of Energy and performed at Oak Ridge National Labontoty. managed by Lockheed Manin Energy Systems, Inc.. for the U. S. Department of Energy under conmct DE- AC05-840R21400.

Figure 1 shows a block diagram of the proposed readout system. The system will consist of 8-channel custom front-end chips (FEC) for the signal processing and digitization, a serial interface circuit for receiving set-up and control commands, a board-level controller, and a data readout interface circuit that transmits the digitized data to the data collection modules. Many of the subcircuits described here are similar to those used in the WA-98 Pb- glass calorimeter that is described in the literature [2,3].

Figure 1. Readout Board Block Diagram.

2.0 FRONT-END CHIP

A block diagram of 1 channel of the proposed FEC is shown in figure 2. We envision this chip being fabricated in a standard, N-well, CMOS process with minimum device length of about 1 pm. Using the custom ICs developed for the WA-98 Pb-glass calorimeter as a guide, we estimate that an 8-channel FEC would require a 5 mm X 5 mm die.

2.1 Energy Processing

In the energy channel, the shaping amplifier filters the preamplifier output to increase the signal-to-noise ratio

(SNR) before digitization. A triangular shaping [4] is proposed here. As shown in figure 3, the SNR is a function of the peaking time of the shaping amplifier. For a detector capacitance of 70 pF and a leakage current of 10 nA, the optimum peaking time of = 1 ps provides less than 20 MeV of noise without generating excessive deadtime.

Dynamic Range Power Consumption Droop Rate

Shaping

Calibnt. Pulser -

~~

1OO:l (25 mV min) 0.75 mW 8.25 mV/ms

35 33 31

z 2 9 z21

5 23

19 17 15

$25

€21

Figure 2. FEC Block Diagram

0.1 1 10 Peaking Time (p)

Figure 3. Energy Channel Noise Vs. Shaping Amplifier Peaking Time.

As shown in figure 2, the peak value of the shaping amplifier is stored in a track-and-hold amplifier ("HA) while the level- 1 trigger is being formed. The THA topology proposed here is shown in figure 4. The input and the output signals initially track in this circuit. When the input signal crosses the threshold of the timing discriminator, the bias current is disabled. Then, the output signal will only track the input signal until it reaches its peak. At this point, the peak value is held until the circuit is reset and the bias current is re-enabled. This circuit was originally developed for use in a Ge-strip detector spectrometer [5]. As shown in table 1, this THA features wide dynamic range, low integral non-linearity, low power consumption, and low droop. If a level-1 trigger is received, the voltage in the THA is digitized, otherwise the THA is reset and a new acquisition cycle is begun.

Non-overlapping 2 X 2 sums of energy signals will be formed on each FEC. These 2 X 2 sums will be transmitted across chip and (in some cases) board boundaries to form overlapping 4 X 4 sums. The 4 X 4 sums will be transmitted to the level-1 trigger system for use in trigger formation.

Reset

output o+-+L-~

Input

Figure 4. THA Topology

Table 1. THA Performance.

m I <+0.05% Pedestal Voltage I < 3 5 m ~

2.2 Timing Processing

The preamplifier signal must be shaped for optimum timing performance also. The timing filter amplifier (TFA) shown in figure 2, will remove the long tail from the preamplifier pulse and limit timing jitter by squelching high-frequency noise.

A constant-fraction discriminator (CFD) is proposed for the timing discriminator. Several low walk, CMOS CFDs have been reported recently [6-81. Figure 5 shows a block diagram of the CFD topology proposed here. This circuit uses cascaded differential-inpuddifferential output amplifiers to maximize gain bandwidth and minimize walk [6-81. The delay will be accomplished with one of the lumped-element, integratable method recently reported [6-91. The arming discriminator uses the first three stages of the zerocrossing discriminator to save die area [7]. The threshold is a current-mode signal injected into the double-ended-to-single-ended converter of the arming discriminator. The DC feedback loop removes the dc offset of the zero-crossing comparator and eliminates the need for a walk adjustment [7]. Figure 6 shows the walk obtained from 4 channels of one of these circuits [6]. It is

probable that off-line slewing corrections can be eliminated by the use of a CFD.

Conversion Range (Full- Scale) Power Consumption

Thresh.

Figure 5. CFD Topology.

I Settable from 20 ns to 1 ps

= I m W

Figure 6. CFD Walk Vs. Amplitude for 4 Channels of CMOS CFD Prototype.

The time-to-amplitude converter PAC) will measure the time interval between the discriminator output and the subsequent beam clock. As shown in figure 7, the TAC proposed here is of the gated charge integrator type. Initially the capacitor is held reset by the feedback switch and the current is flowing into the virtual node of the amplifier. When a start signal arrives, the feedback switch is opened and the current source starts to charge the capacitor. When the stop signal arrives, the current source is switched away from the virtual node of the amplifier and the capacitor voltage holds at that value. A reset is accomplished by putting the switches back in the initial state. A similar TAC was developed for use in the WA-98 Pb-glass calorimeter. The performance of this TAC is given in table 2.

A - -

Figure 7. TAC Block Diagram

Table 2. TAC Performance

out

m I 0.1% from 5 ns to FS Settling Time <lo0 ns

I Reset Time I 4 0 ns I

2 3 Analog-to-Digital Conversion (ADC)

Figure 8 is a block diagram of the 11-bit ADC proposed for the FEC. A prototype of this circuit has been fabricated and tested. The prototype ADC is an 11-bit Wilkinson type with a maximum dynamic range of 4.5 Volts. The Gray code counter uses a positive ECL logic level, differential clock input with frequencies as high as 200 MHz. Since the Gray-code counter is double-edge triggered, the maximum counting rate is 400 MHz.

The ramp generation circuit consists of a an operational amplifier with an on-chip feedback capacitor to form an integrator. The ramp and comparator circuits use a separate analog power and ground connection from the rest of the digital sections of the chip allowing better performance from the ADC. The ADC chip consumes = 5 mW per channel. At a clock rate of 100 MHz, an 11-bit conversion requires 10.2 p. Some key performance parameters are shown in table 3.

We propose one ADC channel for each THA and TAC output so that conversions can be performed in parallel to reduce the deadtime. The ADC clock will be disabled except during the conversion to prevent clock- edge coupling into the energy or timing channels during signal acquisition.

Figure 8. ADC Block Diagram

Table 3. Measured performance of ADC

Channel Width

With a 10 GeV full scale energy range for each channel, an 1 1-bit ADC will have a least count of =5 MeV. A TAC full-scale range of 25 ns would produce timing bins of = 12 ps. This granularity is more than adequate for both timing and energy.

2.4 Diagnostic Features

As shown in figure 2 there are two diagnostic features proposed for the FEC. The calibration pulser allows signals to be injected into the shaping amplifier and TFA, while the multiplexer permits important internal signals on the FEC to be probed. These circuits provide the means to test chips and boards both before and after installation. These diagnostic features were found to be very useful in the testing and installation of the WA-98 Pb- glass calorimeter readout boards.

2.5 Serial Control Interface

The CFD threshold, the calibration pulser amplitude and channel pattern, and the multiplexer address are all controlled by a bit pattern read into the FEC via a serial data interface. Since these settings are generally static for large periods of time, the speed constraints on the serial control interface are very loose.

3.0 BOARD LEVEL ELECTRONICS

The kamd level electronics provides the digital circuitry net- to conno1 the FEC functions, receive the serial con id commands, and transmit the data to the data collection d u l e s . It is expected that these functions can be realized ik a few programmable gate arrays.

The hard-level controller will be a state machine that generates k control signals for the THA, ADC, and calibration p u k of the FEC. This circuit will await a trigger or a clearsignal. If a trigger is received, the board- level controllcr will start the conversion. After the conversion is wmplete, the data readout interface circuit will be i n s t r u d to begin transmitting the data and the THA will be r e a to await the next signal acquisition. If a clear signal is meived instead of a trigger, the THA is simply reset.

The s5d control interface circuit will accept control and s a a p data for the CFD threshold, the calibration puf%a amplitude and channel pattern, and the multiplexer a d k .

The &out interface circuit controls the transmission d @he data from the ADCs to the data collection morhks. This circuit will arrange the data and add the appro- headers and trailers. The data will be transmitted overqtical fibers.

REFERENCES

[l] Letter of In= for A Large Ion Collider Exueriment. Rev. 31, March 9993.

[2] WintenbergA L., T. C. Awes, C. L. Britton, M. S. Emery, M. N. =son, F. Plasil, M. L. Simpson, J. W. Walker, G. R. Ymg and L. G. Clonts. Monolithic Circuits for the WA-98 Lead-Glass Calorimetry. Conference Record of the I W I E E E Nuclear Science Symposium. Vol. 1,493-497.

[3] WintenbergA L., T. C. Awes, C. L. Britton, L. G. Clonts, M. S. Emmy, M. N. Ericson, F. Plasil, M. L. Simpson, J. W. Walker, and G. R. Young. Monolithic Circuits for Led-GTass Calorimetrv. Proceedings of the International Cd-Fence on Electronics for Future Colliders, LeCqCorp., May 1994.

[4] Goulding, F- S, D. A. Landis, and N. W. Madden. Design Philosadh for High-Resolution Rate and Throughuut S ~ o s c o D v Svstems. IEEE Trans. Nucl. Sci. Vol. NS-30, N a 1, February 1983.

[5] Ericson, M. M,M. L. Simpson, C. L. Britton, M. D. Allen, R. A. Krnqer, and S. E. Inderhees. A Low-Power, CMOS Peak Deaest and Hold Circuit for Nuclear Pulse

Spectroscopv. To be published in the IEEE Trans. Nucl. Sci. 1995.

[6] Simpson, M. L., G. R. Young, R. G. Jackson, and M. Xu. A Monolithic. Constant-Fraction Discriminator Usin5 Distributed R-C Delay-Line Shaping. To be presented at the 1995 IEEE Nuclear Science Symposium.

[9] Nowlin, C. H. F g Filters with Rise-time Invariant Crossover Times. Rev. of Sci. Instr. Vol. 63, No. 4, April 1992.

[7] Simpson, M. L., C. L. Britton, A. L. Wintenberg, and G, R. Young. An Integrated. CMOS. Co ns tan t-Frac ti on Tirninp Discriminator for Multichannel Detector Svstems. To be published in the IEEE Trans. Nucl. Sci.. Aug. 1995.

[8] Binkley, D. M. Performance of Non-Delav-Line Constant-Fraction Discriminator Timing Circuits. IEEE Trans. Nucl. Sci. Vol. 41, No. 4, August 1994.

DISCLAIMER

This report was prepared as an account of work sponsored by an agency of the United States Government. Neither the United States Government nor any agency thereof, nor any of their employees, makes any warranty, express or implied, or assumes any legal liability or responsi- bility for the accuracy, completeness, or usefulness of any information, apparatus, product, or process disclosed, or represents that its use would not infringe privately owned rights. Refer- ence herein to any specific commercial product, process, or service. by trade name, trademark, manufacturer, or otherwise does not necessarily constitute or imply its endorsement, recom- mendation, or favoring by the United States Government or any agency thereof. The views and opinions of authors expressed herein do not necessarily state or reflect those of the United States Government or any agency thereof.

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