Integrated Automotive High-Power LED-Lighting Systems in 3D-MID Technology

Integrated Automotive High-Power LED-Lighting Systems in 3D-MID Technology

Werner Thomas

Integrated Automotive High-Power LED-Lighting Systems in 3D-MID Technology

Proefschrift

ter verkrijging van de graad van doctor

aan de Technische Universiteit Delft,

op gezag van de Rector Magnificus prof.ir. K.C.A.M. Luyben;

voorzitter van het College voor Promoties,

in het openbaar te verdedigen op maandag 10 maart 2014 om 10.00 uur

door

Werner THOMAS

Diplom-Ingenieur (FH), Ingolstadt University of Applied Sciences

geboren te Kösching, Germany

Dit proefschrift is goedgekeurd door de promotoren: Prof.dr.eng. J.A. Ferreira Prof.dr. J. Pforr Samenstelling promotiecommissie:

Rector Magnificus, voorzitter Prof.dr.eng. J.A. Ferreira, Technische Universiteit Delft, promotor Prof.dr. J. Pforr, Ingolstadt University of Applied Sciences, Germany, promotor Prof.dr. J.A. Cobos, Universidad Politécnica de Madrid, Spain Prof.dr. techn. N. Seliger, Rosenheim University of Applied Sciences, Germany Prof.dr. G.Q. Zhang, Technische Universiteit Delft Prof.ir. L. van der Sluis, Technische Universiteit Delft Dr. J. Popovi -Gerber, Technische Universiteit Delft

Bibliografische Information der Deutschen Nationalbibliothek Die Deutsche Nationalbibliothek verzeichnet diese Publikation in der Deutschen Nationalbibliografie; detaillierte bibliografische Daten sind im Internet über http://dnb.d-nb.de abrufbar. 1. Aufl. - Göttingen : Cuvillier, 2014 Zugl.: (TU) Delft, Univ., Diss., 2014

978-3-95404-643-0 © CUVILLIER VERLAG, Göttingen 2014 Nonnenstieg 8, 37075 Göttingen Telefon: 0551-54724-0 Telefax: 0551-54724-21 www.cuvillier.de Alle Rechte vorbehalten. Ohne ausdrückliche Genehmigung des Verlages ist es nicht gestattet, das Buch oder Teile daraus auf fotomechanischem Weg (Fotokopie, Mikrokopie) zu vervielfältigen. 1. Auflage, 2014 Gedruckt auf umweltfreundlichem, säurefreiem Papier aus nachhaltiger Forstwirtschaft.

978-3-95404-643-0

to my family

Acknowledgements The research presented in this thesis has been performed at the Institute of Applied Research at Ingolstadt University of Applied Sciences. The work has been carried out in cooperation with the Electrical Power Processing (EPP) group at the Delft University of Technology. Over the past years, many people have contributed to the thesis either directly or indirectly. I would like to take this opportunity to thank those involved.

I am very grateful to my promotor, Professor Braham Ferreira, for giving me the opportunity to do my Ph.D. in his research group, for his support and his constructive comments to my work and to the thesis.

I would like to express my gratitude to Professor Johannes Pforr, for giving me the possibility to work in the field of power electronics and LED-lighting systems. Thank you for the tireless engagement in reviewing the publications, the endless discussions and for the guidance throughout my five years at the institute.

I would like to thank my daily supervisor Dr. Jelena Popović-Gerber for the support and discussions during writing the thesis as well as for being “my place to go” in Delft for all my questions independently of orginsational or technical nature.

Sincere thanks goes to the AUDI AG for supporting my research project. Especially, I would like to thank Stephan Berlitz, head of development lighting functions and innovations, for his continuous support and for giving me the possibility to carry out research in the field of Solid-State-Lighting.

I would like to thank my Ph.D. commission members: Professor J.A. Cobos, Professor N. Seliger, Professor L. van der Sluis and Professor G.Q. Zhang for the time and effort they spent reading my thesis, for their comments and suggestions.

Special thanks go to Ivan Josifovic for helping me through the organisational “paperwork” and to Martin van der Geest for translating the summary into Dutch.

I would like to thank Thomas Baier, my contact person at AUDI AG for the help and the great collaboration, especially in the first part of the project.

I am very grateful to my former colleagues at Ingolstadt University of Applied Sciences, especially Christian Augustin, Roland Cziezior, Thomas Hackner and Michael Stadler for the technical discussions and for making the time enjoyable. In particular, I would like to thank Sebastian Utz for “enduring” five years in the same office, all the discussions, countless night shifts in the lab or in the office and for being such a good friend.

I am deeply grateful to my parents and my sister for their love, for being there when ever needed and for their boundless support during my entire life. Thank you so much.

Most of all, I would like to thank my “better half” Anja for everything you did and meant to me in the last six years; for always being there, for enduring my unavailability, for bringing so much joy in my life and for always believing in me.

Table of content

List of symbols ..................................................................................................................................... xiii

1. Introduction ..................................................................................................................................... 1

1.1. Background ............................................................................................................................. 1

1.2. Applications of LED-lighting .................................................................................................. 2

1.2.1. Automotive lighting......................................................................................................... 2

1.2.2. General lighting and consumer electronics ..................................................................... 5

1.3. Requirements on three-dimensional LED-lighting systems .................................................... 6

1.4. Problem description ................................................................................................................. 8

1.4.1. Derived objectives ........................................................................................................... 9

1.5. Thesis layout ............................................................................................................................ 9

2. Overview of three-dimensional LED-lighting systems ................................................................. 13

2.1. Introduction ........................................................................................................................... 13

2.2. LED-lighting systems: components and functions ................................................................ 13

2.2.1. Light-Emitting-Diodes (LEDs) ..................................................................................... 14

2.2.2. LED-driver .................................................................................................................... 16

2.2.3. External thermal management components ................................................................... 19

2.2.4. Circuit carrier technology .............................................................................................. 20

2.3. Evolution towards three-dimensional LED-lighting ............................................................. 21

2.3.1. Printed Circuit Board (PCB)-based assemblies ............................................................. 21

2.3.2. Insulated Metal Substrate (IMS)-based assemblies ....................................................... 24

2.3.3. Flexible Printed Circuit Board (Flex-PCB)-based assemblies ...................................... 26

2.3.4. 3D-Moulded Interconnect Device (3D-MID)-based assemblies ................................... 27

2.4. Requirements on future 3D LED-lighting systems ............................................................... 32

2.4.1. Conclusions on evolution towards three-dimensional LED-lighting ............................ 32

2.4.2. Requirements for future 3D LED-lighting systems ....................................................... 32

2.5. Summary ............................................................................................................................... 33

3. Enabling 3D-MID-based high-power LED-lighting systems ........................................................ 39

3.1. Introduction ........................................................................................................................... 39

3.2. 3D-MID-based high-power LED-lighting systems ............................................................... 39

3.2.1. Concept idea .................................................................................................................. 40

3.2.2. Concept challenges ........................................................................................................ 41

3.3. Making 3D-MID-based high-power LED-lighting possible ................................................. 43

3.3.1. LED-driver topologies ................................................................................................... 44

3.3.2. Spatial- and electrical design ......................................................................................... 44

x Table of content

3.3.3. Thermal management design ......................................................................................... 45

3.3.4. Interrelation between domains ...................................................................................... 45

3.3.5. Spatial configurations .................................................................................................... 46

3.4. Summary ............................................................................................................................... 47

4. Integration of LED-driver functions .............................................................................................. 51

4.1. Introduction ........................................................................................................................... 51

4.2. Survey of LED-drivers for application on 3D-MIDs ............................................................ 52

4.2.1. Series LED-structures .................................................................................................... 52

4.2.2. Multiple power converters and converter-cells ............................................................. 53

4.2.3. Parallel LED-structures ................................................................................................. 54

4.2.4. Summary ....................................................................................................................... 59

4.3. Development of inductive current balancing technique for high-power LEDs ..................... 60

4.3.1. Basic idea and operation principle................................................................................. 60

4.3.2. Parallel input-structures ................................................................................................. 63

4.3.3. Series input-structures ................................................................................................... 66

4.3.4. Comparison of equal power and equal current LED operation ..................................... 69

4.3.5. Experimental verification .............................................................................................. 72

4.4. Compensation of increased LED-tolerances and of LED failures......................................... 75

4.4.1. Basic idea ...................................................................................................................... 76

4.4.2. Analysis of current balancing behaviour ....................................................................... 77

4.4.3. Operation with LED failures ......................................................................................... 82


4.5. Integration of external PWM dimming ................................................................................. 87

4.5.1. Basic idea and operation principle................................................................................. 87

4.5.2. Investigation of dimming related colour shift ............................................................... 88

4.5.3. Converter design for modulated dimming ..................................................................... 90


4.6. Overview of developed LED-drivers for 3D-MID application ............................................. 97

4.7. Summary ............................................................................................................................... 98

5. Integration of spatial and electrical functions.............................................................................. 105

5.1. Introduction ......................................................................................................................... 105

5.2. Comparison of 3D-MID and PCB construction .................................................................. 106

5.2.1. Substrate technology ................................................................................................... 107

5.2.2. Circuit artwork assembly ............................................................................................. 109

5.2.3. Via interconnection technology ................................................................................... 112

5.2.4. Summary on 3D-MID vs. PCB construction ............................................................... 115

Table of content xi

5.3. Contacting challenges of components ................................................................................. 117

5.3.1. Current carrying capacity of 3D-MID circuit tracks ................................................... 117

5.3.2. Integration potential of passive components with 3D-MIDs ....................................... 123

5.3.3. Circuit trace parasitics ................................................................................................. 125

5.4. Spatial- and electrical performance of 3D-MID-based power converters ........................... 133

5.4.1. Case study introduction ............................................................................................... 133

5.4.2. Spatial performance ..................................................................................................... 136

5.4.3. Electrical performance ................................................................................................. 142

5.4.4. Estimation of power limits of 3D-MID-based power electronics ............................... 150

5.5. 3D-routing possibilities and concepts ................................................................................. 156

5.5.1. Increasing the circuit- and the component-density ...................................................... 157

5.5.2. Integration of additional functions .............................................................................. 158

5.5.3. Summary on 3D-routing .............................................................................................. 159

5.6. Summary ............................................................................................................................. 161

6. Integration of thermal management functions ............................................................................. 167

6.1. Introduction ......................................................................................................................... 167

6.2. Identification of dominant heat transfer modes in LED-lighting systems ........................... 167

6.2.1. LED-driver components .............................................................................................. 168

6.2.2. High-power LEDs ....................................................................................................... 169

6.2.3. 3D-MID challenges ..................................................................................................... 169

6.3. Converter level thermal management .................................................................................. 170

6.3.1. Perpendicular heat transport and heat spreading ......................................................... 170

6.3.2. Layout and geometry optimisation .............................................................................. 177

6.3.3. Integration of extra thermal pathways ......................................................................... 180

6.3.4. Substrate material modification ................................................................................... 180

6.3.5. External cooling structures: Heat sinks ....................................................................... 181

6.3.6. Constraints for 3D-MID-based LED-lighting applications ......................................... 182

6.4. Thermal management with the 3D-MID circuit carrier – a case study ............................... 183

6.4.1. Design of circuit carrier based thermal management .................................................. 185

6.4.2. Case study implementation .......................................................................................... 185

6.4.3. Case study results ........................................................................................................ 191

6.5. Integrated Reflector Heat Sink ............................................................................................ 194

6.5.1. Basic idea .................................................................................................................... 195

6.5.2. IRHS construction ....................................................................................................... 197

6.5.3. IRHS design ................................................................................................................ 198

6.5.4. Implementation – a case study .................................................................................... 200

xii Table of content

6.6. Summary ............................................................................................................................. 205

7. Case study: 3D-MID-based high-power LED-lighting system ................................................... 211

7.1. Introduction ......................................................................................................................... 211

7.2. System specification ............................................................................................................ 211

7.3. System design ...................................................................................................................... 212

7.3.1. LED-driver topology selection .................................................................................... 213

7.3.2. Spatial design and routing ........................................................................................... 215

7.3.3. Thermal management design ....................................................................................... 217

7.4. Realisation of the case study prototype ............................................................................... 221

7.5. Spatial evaluation ................................................................................................................ 224

7.6. Electrical evaluation ............................................................................................................ 225

7.6.1. Current-balancing ........................................................................................................ 225

7.6.2. LED failures ................................................................................................................ 226

7.6.3. Modulated dimming .................................................................................................... 227

7.6.4. LED-driver efficiency ................................................................................................. 228

7.7. Thermal evaluation .............................................................................................................. 229

7.7.1. LED-driver .................................................................................................................. 229

7.7.2. LED-section ................................................................................................................. 231

7.8. Summary ............................................................................................................................. 231

8. Conclusions and recommendations ............................................................................................. 235

8.1. Summary ............................................................................................................................. 235

8.2. Conclusions ......................................................................................................................... 236

8.2.1. Present practice and evolution of (3D) LED-lighting system construction ................. 236

8.2.2. 3D-MID technology application to enhance the 3D-design of high-power LED-lighting systems with LED-driver ............................................................................................................. 237

8.2.3. Development of adapted LED-driver topologies for 3D-MID realisation .................. 238

8.2.4. Influence of 3D-MID usage on electrical and spatial realisation of power electronics238

8.2.5. Thermal management of 3D-MID-based LED-lighting systems ................................ 239

8.2.6. Thesis contributions..................................................................................................... 240

8.3. Recommendations for further research................................................................................ 241

A. Appendix: Influence of inductor tolerances ................................................................................ 245

B. Appendix: Loss analysis and -comparison .................................................................................. 251

C. Appendix: Thermal-modelling and -simulation .......................................................................... 265

SUMMARY ........................................................................................................................................ 273

SAMENVATTING ............................................................................................................................. 277

ZUSAMMENFASSUNG .................................................................................................................... 281

CURRICULUM VITAE ..................................................................................................................... 287

List of symbols

Latin Letters

A Area [m²] A Active Source A Attenuation Aactive Surface area that contributes to radiation [m²] Aback Back surface [m²] Abot Bottom surface [m²] Achip Chip area [m²] Afront Front surface [m²] Aplate Plate area [m²] Aside Side surface [m²] Atop Top surface [m²] B Magnetic flux density [T] B Width [m] Bpk Peak magnetic flux density [T] C Capacitance [F] Cdg Drain gate capacitance [F] Cds Drain source capacitance [F] Cgs Gate source capacitance [F] Cin Input capacitance [F] Ciss MOSFET input source capacitance [F] Cout Output capacitance [F] CP Heat capacity of the fluid [J/K] Crss MOSFET output source capacitance [F] Cx Branch capacitance [F] ci Inner diameter of vias [m] cvia_3D-MID Diameter of 3D-MID vias [m] D Duty cycle [%] D Diode Dr Driver dtrace Distance among circuit traces [m³] dvia Distance between vias [m] E Energy [J] FC Frequency response of C-filter FCL Frequency response of C-L-filter fe Effective frequency [Hz] fo Repetition frequency [Hz] fs Switching frequency [Hz] fmod Modulation frequency [Hz] hc Convection based heat transfer coefficient [W/m²K] hinductance Inductor height [m] hIRHS Height of Integrated Reflector Heat Sink [m] hhor Horizontal heat transfer coefficient [W/m²K] hvert Vertical heat transfer coefficient [W/m²K] I Current [A]

xiv List of symbols

Iavg Average Current [A]ID Diode Current [A]Idr Gate driver current [A]IL Current through inductance [A]ILED LED current [A]ILp_x Current through primary winding of transformer x [A]ILs_x Current through secondary winding of transformer x [A]In Input current [A]IRMS Root mean square current [A]J Current Density [A/m²]K0 Core volume [m³]K1 AC loss constantKf Frequency constantKb Flux density constantL Inductance [H]L Length [m]LA Parasitic anode inductance [H]Ldx Parasitic drain inductance [H]lCu Copper length [m]lIRHS Length of Integrated Reflector Heat Sink [m]LK Parasitic cathode inductance [H]Lin Input inductance [H]Lloop Parasitic loop inductance [H]Lo Output inductance [H]Ls Leakage inductance [H]Lsx Parasitic source inductance [H]Lx Branch inductance [H]M Mutual inductance [H]M Modulation signalN Number of windingsnbranch Number of branchesncell Number of (converter-) cellsnLED Number of LEDsP Power [W]Pc Core losses [W]Pconduction Conduction losses [W]Pconv Power dissipated by convective heat transfer [W]PLED LED power [W]Pload Power of load [W]Ploss Power loss [W]Prad Power dissipated by radiative heat transfer [W]Psw Switching losses [W]PV Magnetic core loss [W]Q Heat dissipated by a source [W]Q MOSFETq Heat flux [W/m²]Qgd MOSFET gate charge [C]R Resistance [Ω]Rbx Balancing resistance [Ω]Rac Ac resistance [Ω]Rd Diode resistance [Ω]

List of symbols xv Rdc Dc resistance [Ω]Rel Resistance of circuit trace [Ω]Rdson On resistance of MOSFET [Ω]Rg Gate resistance [Ω]Rgate_dr Internal driver gate resistance [Ω]Rloop Loop resistance [Ω]Rm Magnetic resistance [H-1]Rmax Maximum resistance [Ω]Rm_air-gap Magnetic resistance of air gap [H-1]Rm_ferrite Magnetic resistance of ferrite [H-1]Roper Temperature corrected resistance [Ω]Rth_Cu Thermal resistance of copper (-layer) [K/W]Rth_Cu_spread Thermal spreading resistance of copper [K/W]Rth_interface Thermal resistance of interface material [K/W]Rth_IRHS Thermal resistance of Integrated Reflector Heat Sink [K/W]Rth_IRHS_ambient Thermal resistance of Integrated Reflector Heat Sink to ambient [K/W]Rth_j_c Junction to case thermal resistance [K/W]Rth_LED Thermal resistance of LED package [K/W]Rth_perp Perpendicular thermal resistance [K/W]Rth_sub Thermal resistance of substrate [K/W]Rth_sub_ambient Thermal resistance of substrate to ambient [K/W]Rconv Convection resistance [K/W]Rsp Thermal spreading resistance [K/W]Rtotal Total resistance [Ω]Rtot Total thermal resistance [K/W]sx Edge length [m]Tambient Ambient temperature [K]TC Time response C-filter [s]TCL Time response C-L-filter [s]tCu Copper thickness [m]tif Current fall-time [s]Tj Junction-temperature [K]toff Off-time [s]ton On-time [s]Tmax Maximum temperature [K]Ts Switching period [s]tsub Substrate thickness [m]tvr Voltage rise-time [s]V Voltage [V]VCx Voltage of capacitor [V]VD Diode forward voltage [V]Ve Core volume [m³]Vg Gate voltage [V]Vin Input voltage [V]VL Voltage across inductance [V]VLED LED forward voltage [V]Vo Output voltage [V]Vout Output voltage [V]Vplt MOSFET plateau voltage [V]VRx Voltage of resistor [V]Vs Voltage across power switch [V]

xvi List of symbols

Vth Threshold voltage of MOSFET [V]Vx Volume [m³]wCu Copper width [m]wIRHS Width of Integrated Reflector Heat Sink [m]wwindow Width of magnetic core’s winding window [m]

Greek Letters

α Angle [°]α Aspect ratioα20 Linear temperature coefficient [1/K]β Expansion coefficient of the fluid [1/K]δ Skin depth [m]ε Permittivity [F/m]ε Surface emission coefficientεr Relative permittivityεr Relative surface emission coefficientζrelative Relative volume utilisation factorη Electrical efficiency [%]ηLED Electrical LED efficiency [%]Θ Magnetomotive Force [AT]Δ I Peak inductor current [A]Δ ILED_max Maximum branch current deviation [%]Δ Irel Relative current deviation [%]Δ Irel_simp Simplified relative current deviation [%]Δ L Inductance deviation [%]Δ Lloop Change of parasitic loop inductance [H]Δ PLED_max Maximum branch power deviation [%]Δ Prel Relative power deviation [%]ΔT Temperature increase [K]ΔTLED Temperature increase of LED chip [K]ΔT22 Time interval [s]Δton Rise time [s]Δtoff Fall time [s]ΔTtrace Temperature increase of circuit trace [K]Δ Vds Overvoltage at MOSFET [V]Δ VLED LED branch voltage deviation [V]Δ vo Output voltage deviation [V]Δx Colour shift in x-direction chromaticity diagram CIE 1931Δy Colour shift in y-direction chromaticity diagram CIE 1931Φ Magnetic Flux [Wb]λ Thermal conductivity [W/mK]λCu Thermal conductivity of copper [W/mK]λIRHS Thermal conductivity of Integrated Reflector Heat Sink [W/mK]λsub Thermal conductivity of substrate [W/mK]μ Absolute viscosity of the fluid [Ns/m²]μ0 Magnetic permeability of vacuum [H/m]μr Relative magnetic permeabilityρ20 Specific electrical resistivity [Ω mm²/m]

List of symbols xvii ξ Damping ratio ρ Fluid density [kg/m³]σ Electrical conductivity [S/m]σ Stefan-Boltzmann constant [J/K]tan(δ) Loss tangentψcomponent Component volume [m³]ψtotal_assembly Total assembly volume [m³]ψunused Total unused volume in the assembly [m³]ω Angular frequency [rad-1]ωd Angular frequency diode current [rad-1]

Acronyms

2D Two-dimensional3D Three-dimensional3D-MID 3D Moulded Interconnect Deviceac Alternating currentCCC Current Carrying CapacityCCD Charge Coupled DeviceCCM Continuous Conduction ModeCTE Coefficient of Thermal Expansiondc Direct currentDCM Discontinuous Conduction ModeDRL Daytime Running LightEMC Electromagnetic CompatibilityEMI Electromagnetic InterferenceFEM Finite Element ModellingIMS Insulated Metal SubstrateIRHS Integrated Reflector Heat SinkLCD Liquid Cristal DisplayLCP Liquid Crystal PolymerLDS Laser Direct StructuringLED Light Emitting DiodeMOSFET Metal Oxide Field Effect TransistorPA PolyamidePC Phosphor coatedPC-ABS Polycarbonate/Acrylonitrile Butadiene StyrenePCB Printed Circuit BoardPEEC Partial Elements Equivalent CircuitPEN Polyethylene NaphthalatePET Polyethylene TerephthalatePI PolyimidePMMA Polymethyl MethacrylatePPA PolyphtalamidePWM Pulse Width ModulatedRMS Root Mean SquareSEPIC Single Ended Primary Inductor ConverterSMT Surface Mount TechnologySSL Solid State Lighting

1. Introduction

1.1. Background

Rising luminous fluxes of high-power LEDs as well as the growing energy consumption of lighting – 19 percent of the global energy production in 2006 [WT06] – have contributed to the widespread use of LEDs in modern lighting systems [St08]. Today, single LED-packages reach a light output that is competitive or even higher than those of incandescent- and compact-fluorescent-lamps, as illustrated in Figure 1-1. LED-arrays even surpass these values and achieve luminous fluxes of up to 9,000lm [Br11].

Figure 1-1: Total luminous flux of different light-sources derived from [WT06] with updated values for high-power LEDs [Os07], [Os08]

Increasing luminous efficacies, i.e. the emitted luminous flux per watt electrical power consumption, are another important reason for the growth of LED-lighting [Wh057].

The technological progress of LED-lighting can be seen from Figure 1-2, where a comparison of the luminous efficacy of different selected light sources is given. Currently, high-power LEDs achieve a maximum luminous efficacy of up to 157 lm/W, with a mean value of about 75 lm/W considering different power-classes [SSL11]. This is a factor 5 to 10 higher performance when compared to conventional incandescent- or halogen- lamps. Commercially available high-power LEDs can also compete with energy-saving- and fluorescent-lamps in terms of their luminous efficacy.

Furthermore, the general research goal for white high-power LEDs is set to reach 200 lm/W [SSL11] (single-chip LEDs), which is even higher than the efficacy of High-Intensity-Discharge lamps.

0 500 1000 1500 2000 2500 3000 3500

High-power LEDs(single package)(different types)

Xenon lamp (low- to high-beam)

Compact fluorescent (9-25W)

Standard incandescent (40-100W)

Luminous flux [lm]

Light-Emitting-Diode(single package)

(0.01-12W)

Xenon lamp(low- to high-beam)

Standard incandescent lamp

(40-100W)

Compact fluorescent(9-25W)

2 Chapter 1

Figure 1-2: Luminous efficacy of selected light-sources derived from [AL03]with updated values for high-power LEDs [Os08], [Os07], [Ph07a], [Cr08b], [SSL11]

Another advantage of LEDs is their long lifetime which can reach a peak value of over 100,000 operating hours [Ph06] at optimal environmental conditions. Due to this, a multitude of lighting applications can be designed without considering maintainability. When combining this feature with the small geometrical dimensions of the LED-chips – a typical chip has an area of =1-2mm² – very compact or thin systems get possible.

These benefits as well as a wide range of available colours make LEDs and especially high-power LEDs the technology of choice for a multitude of applications. Besides, a large variety of customised lighting functions can be fulfilled by Solid-State-Lighting.

1.2. Applications of LED-lighting

LED-lighting applications comprise the automotive-sector, general-lighting and consumer electronics. These will be characterised in the following.

1.2.1. Automotive lighting

In the last years, LED exterior lighting has started to become a prominent innovation in automotive lighting. The beginnings have been already made in the 1990’s with the introduction of the ’third stop-light’ in LED-technology, where the fast turn-on behaviour of LEDs was used to decrease the reaction time of the following drivers [Ve06].

The use of complete LED taillights has been a further step to advance automotive exterior lighting. With the introduction of white light generated by LEDs and rising luminous fluxes, LED-based automotive front-lighting emerged and is already used in insular series applications today.

Besides to increased efficacies and lifetime, other technological benefits have contributed to the success of LED-lighting in automotive applications:

0 50 100 150 200 250Efficacy [lm/W]

Standard incandescentTungsten halogen

Halogen infrared reflectingMercury vapor

Compact fluorescent (5-26W)Compact fluorescent (27-55W)

Linear fluorescentMetal halide

Compact metal halideLED (1-3W)

LED (5W)LED (12-20W)

LED (research goal)

Introduction 3

The small footprint and height of LEDs allows new degrees of freedom in placing light elements and allows improved as well as complex three-dimensional lamp designs.

LED-lighting systems often comprise a multitude of single LEDs, which can be individually arranged or electrically driven to enable new lighting functions highly exceeding the possibilities of conventional single and central light sources.

Figure 1-3 shows several examples of modern automotive LED-lighting systems which already benefit from the flexibility in lamp design obtained by the LED-technology. It is common to these solutions that the LEDs are spatially arranged in three-dimensions (3D) to create a more individual design of the day- and night-appearance of the automobile-front and -rear when compared to conventional halogen- or xenon-lamps. These systems will be called 3D LED-lighting systems throughout this thesis.

Figure 1-3: Trends in automotive exterior lighting: LED-lighting used as recognition feature to stand out from the competition and to differentiate model specific design

The arrangement of the LEDs is particularly used to underline the exterior shape of the automobile. The LED-design therefore provides a diversification in between the model-range of a car manufacturer. Furthermore, it is a recognition feature to stand out from the competitors.

Solutions with (advanced) 3D-designs, however, require a complex assembly to mount and to electrically contact the LEDs in space that also comes at the cost of a large component count (Figure 1-4). Besides, conventional cooling solutions have to be adapted according to the desired 3D-shape. Unfortunately, these aspects limit the design versatility that can be achieved in 3D LED-lighting systems and increase system costs when using state of the art assemblies. Therefore, the majority of contemporary automotive lamp designs are still

(Source: Audi AG)

4 Chapter 1

focused on conventional shapes with single and central light source, as known for the past decades.

Figure 1-4: Full-LED headlamp with limited 3D-design

State of the art solutions for creating three-dimensional LED-lighting systems and their limitations will be discussed in detail in Chapter 2.

Environmental conditions and requirements

Automotive LED-lighting systems often consist of a multitude of LEDs that can have different power levels and colour values to perform lighting functions, like in stop-lights, day-time-running lights or even as low- or high-beam (Figure 1-5). The coloured and white LEDs are often located as clearly visible single light sources.

Figure 1-5: Full LED-headlamp (left) and LED tail-lamp (right)

As the conventional 14V automotive electrical power net has a variable input voltage with typical values of Vin =8V-17V, a stable LED-brightness level has to be achieved over the entire input voltage range. Commonly, switched mode power converters are used to maintain and control the LED-brightness. When a large number of LEDs is used, a uniform brightness distribution is additionally required in order to maintain the required light output distribution as well as for optical reasons. In addition, brightness control is a key requirement in automotive lighting to provide basic lighting functions, e.g. day-time-running-lights are operated at night as position light which requires dimmed LED-operation. Finally, a high

LEDs(behind lenses)

Design element

Optical system

Thermal management(backside)

Circuit carrier(backside)

(Source: Cadillac)

Low Beam:14 LED-Chips

Daytime-Running-Light:24 LEDsIndicator LEDs

High Beam:2 x 4 LED-Chips

Tail- and stop light:41 LEDs

(Source: Audi AG)

Introduction 5

availability of the lighting system is required due to its security-related function. All these attributes define essential lighting functions, which require LED-drivers that are optimisedtowards automotive requirements.

3D LED-lighting systems further demand on solutions that allow the mechanical- and the electrical-connection of LEDs and LED-driver components in space to achieve the required design and functionality. As constructed space is limited in automobiles, the desired 3D-shapes have to be realised without consuming excess space.

Harsh environmental conditions within the vehicle, with vibrations and shocks, amplify the requirements on the LED-lighting system. Furthermore, the LEDs and LED-driver components are excited to wide temperature ranges of -40 C to +80°C (up to +120°C in special cases) which requires an effective thermal management to keep component temperatures below critical values (Chapter 2). The heat dissipated by high-power LEDs increases temperature levels above environmental temperatures in the lamps. The electrical system should therefore operate at reduced losses when integrated in the lighting system.

1.2.2. General lighting and consumer electronics

Next to the automotive environment, LED-lighting is increasingly used in general lighting and in consumer electronics. In the latter case, LEDs have been used as signal or control lights for decades, comparably to automotive (stop-) lighting. With rising luminous fluxes, however, also consumer articles emerged that contain high-power LEDs, e.g. in video projectors or in backlights of LCD-displays [Lu09].

The use of Solid-State-Lighting in general lighting has started to grow in the last few years. General lighting is considered in this thesis, as indoor- and outdoor-lighting, e.g. in street-lamps with LEDs that exhibit high luminous fluxes of 2,000-10,000 lumens [Ca09], [PT096], [Ow096]. The resolution of the European Commission for phasing out incandescent lamps and of lamps with a non-tolerable luminous efficacy [Eu08] further accelerated the demand on high-power LEDs as an alternative light-source in general lighting.

Like in automotive applications, in general lighting or in consumer electronics LEDs are not only used for reasons of saving energy and for lifetime considerations. Moreover, there are some applications that benefit from LEDs’ small footprints and the ability to spatially arrange individual light sources. Figure 1-6 (a) shows an LED street lamp with a three-dimensional design as one possible example. In this lamp, the LEDs are used to create a completely new design which allows a diversification among other street lamps, which is comparable to the approaches in the automotive segment. Further, a three-dimensional LED-arrangement can also be used to obtain an improved brightness distribution on the street (Figure 1-6 (b)).

In contrast to the automotive sector, in consumer electronics or in general lighting, there is no general trend towards three-dimensional shaping of lighting systems, due to the wide span of applications, which neither require enhanced shaping possibilities nor need to save construction space.

6 Chapter 1

Figure 1-6: Three-dimensional shaped LED streetlamps

The absence of a simple solution for forming 3D LED-lamps and the high assemblycomplexity – with a large number of components (Figure 1-6 (b), (c)) – further contributes to the low number of applications, which benefit from a three-dimensional alignment of LEDs up to now.

Environmental conditions and requirements

General lighting solutions often comprise a multitude of high-power LEDs to meet the requirements on high luminous fluxes, as shown in Figure 1-6. Also consumer electronics, like the background illumination of flat-screen TVs, contains a large number of LEDs. A power electronic system is therefore required to maintain required LED-brightness-distribution and -control, e.g. for dynamic background illumination [WKM09]. Further, in 230 VAC mains application systems, galvanic isolation is required to decouple high input voltages from the LEDs. This is especially necessary when a compact lamp-design without extra LED-housing is desired. Hence, a power converter is required to transform high ac voltages into appropriate dc voltages for the LEDs.

Different environmental conditions, e.g. ambient temperatures, have to be considered in domestic applications, depending on indoor- or outdoor usage. In the vast majority of applications, the environmental impacts are significantly lower than in automotive LED-lighting. It is therefore assumed that most of the foregoing environmental conditions are also covered by the demands of automotive exterior lighting.

Thus, the automotive environment, with its conventional 14V automotive electrical power net, will be the considered environment in this thesis. However, special applications suitable for the mains will be commented throughout the work when applicable.

1.3. Requirements on three-dimensional LED-lighting systems

Progresses in the LED technology have led to a variety of applications in automotive- and general-lighting. Especially the field of automotive exterior LED-lighting uses the small footprint of LEDs and their characteristic as point light sources as key features to combine lighting tasks with design (Section 1.2).

(Source: Schréder GmbH)

LED power supply

Additional wiring

LEDOptical system

Printed circuit board

Housing

Environmental protection

Additional wiring

Closing clips

(a) (b) (c)(Source: Siteco GmbH)

Introduction 7

Although automotive LED-lighting is at the leading edge regarding three-dimensional lighting solutions, the current construction of 3D LED-lighting systems is not optimised towards complex design requirements. Contemporary assemblies require a large number of construction parts to perform 3D-contacting and -mechanical fixation of LEDs and their related power electronic LED-drivers.

Thus, the plurality of automotive LED-lighting systems is still focused on conventional designs of front- and tail-lights, as known for decades. The same limitation has been observed for the majority of LED-based general-lighting systems.

To improve 3D LED-lighting systems, the following target functions can be identified and should be addressed:

Spatial und mechanical functions:

o The lighting systems must be able to follow complex three-dimensional shapes to further improve the degrees of freedom in the lamp design. For this reason, the LEDs and the power electronics, for their electrical drive, require a 3D-structure which fixes them.

o Due to the requirement of reduced constructed space (automotive), the system should also be able to achieve the required 3D-shape at a minimum of excess volume. Hence, solutions which allow a reduced construction height are desirable.

o The systems should be built at a reduced number of components to reduce efforts in their spatial fixation. Furthermore, they must be robust against application specific environmental conditions, e.g. vibrations or maximum temperatures.

Electrical functions:

o In 3D LED-lighting systems, the LEDs and the power electronics must be electrically contacted in three dimensions and the appropriate signals have to be delivered to the spatially distributed LEDs.

o The electrical drive has to ensure that a homogeneous brightness distribution is achieved among the LEDs, as they are often clearly visible as single light-sources. Here, LED specific requirements concerning temperature- and electrical-behaviour (Chapter 2 and 4) have to be observed.

o As input-voltage levels can vary, the LED drive has the function to keep stable LED brightness levels over input voltage variations. Furthermore, the power electronics should provide a galvanic isolation when high (input-) voltages appear to separate them from the remaining system.

o (Automotive) illumination requires high system availability. Therefore, the LED-driver should be able to maintain a high operational availability even at LED failures.

8 Chapter 1

Thermal functions:

o An effective cooling of the used high-power LEDs and the power electronic components, especially for high power levels, is required and has to take care of the demand on high degrees of freedom in 3D-design.

1.4. Problem description

The high versatility in placing individual and compact light sources is a key feature provided by LED-lighting technology. It allows an enhanced design flexibility which can skilfully be used to improve the appearance, but moreover to enhance functions of modern lighting systems, as introduced in Section 1.2. So far, the LED-technology’s potential for improving three-dimensional designs is, however, insufficiently used in the vast majority of LED-lighting applications.

The physical realisation of contemporary LED-lighting systems requires a large number of components and is identified as the main hurdle for limiting the distribution of 3D LED-lighting systems. These systems comprise LED-drivers, 3D-mounting and -contacting components as well as thermal management structures that have to be mounted and arranged in three-dimensions leading to high efforts and costs (Section 1.2).

A new approach is therefore needed for the realisation of 3D LED-lighting systems to decrease the number of components and to enhance the design versatility. This directly addresses the components which are necessary to fulfil spatial-, electrical- and thermal-functions, defined in Section 1.3.

Determining a new concept for the realisation of 3D LED-lighting systems requires the analysis of the current practice and evolution of 3D LED-lighting assemblies to identify the main technological boundaries as well as to derive requirements on future assemblies.

The main objective in this concept, and hence in this thesis, is to decrease the number of components of contemporary automotive LED-lighting systems and to enhance the design versatility in three-dimensions by integrating the functions provided by individual parts into one or more multifunctional components. This concept requires the investigation of the integration potential for the LED-driver, for the electrical- and spatial-contacting and for the thermal-management in the ‘3D multifunctional-component(s)’.

As a wide range of applications, with different spatial arrangements and power levels, exist for LED-lighting it is further required to provide techniques that derive the limitations and possibilities for the concept’s electrical-, spatial- and thermal-design. These parameters can be used to determine the feasibility of prospective applications and to derive adapted designs.

Introduction 9

1.4.1. Derived objectives

Analysing the foregoing problem description, the main objective of this thesis is to:

decrease the component number required in high-power 3D LED-lighting systems with power electronic LED-driver to reduce the complexity in the assembly and to increase the degrees of freedom in the design.

To achieve this aim the following objectives have to be determined:

Identification of the main reasons that limit enhanced designs of contemporary high-power LED-lighting systems by analysing the present practice of construction and the evolution towards 3D LED-lighting systems

Determination of an approach to use the technology of 3D-Moulded Interconnect Devices (3D-MID) for enhancing the 3D-design whilst decreasing the construction complexity of high-power LED-lighting systems with LED-driver by increasing the level of function integration

Development of optimised LED-drivers with integrated lighting functions for asimplified 3D-MID realisation

Determination of merits and limitations to mount and contact the LED-driver and the LEDs on the 3D-MID as well as to analyse influences of the 3D-MID technology on the spatial- and electrical- realisation of power-electronics

Examination of the potential to integrate thermal management functions into the 3D-MID for low complexity systems and to derive a solution to enhance the power level of 3D-MID-based LED-lighting systems whilst maintaining high degrees of freedom

1.5. Thesis layout

Figure 1-7 visualises the layout of the thesis.

10 Chapter 1

Figure 1-7: Thesis layout

Chapter 1Introduction

Chapter 2Overview of 3D LED-

lighting systems

Chapter 3Enabling 3D-MID based high-power LED-lighting

systems

Chapter 7Case Study: 3D-MID

based high-power LED-lighting system

Chapter 8Conclusions and

Recommendations

Chapter 5Integration of spatial and

electrical functions

Chapter 6Integration of Thermal management functions

Chapter 4Integration of LED-driver

functions

Bibliography [AL03] ALG: Advanced Lighting Guidelines. New Buildings Institute Inc, White Salmon,

Washington, D.C, 2003.

[Br11] Bridgelux: Bridgelux RS Array Series: Product Data Sheet DS25, 2011.

[Ca09] Cardenas, A.: Operating the City Green Lighting Building the Harmonious Society - DMX Solar LED Street Light Specification-, 2009.

[Cr08b] Cree XLamp MC-E Datasheet, online available at: http://www.cree.com/products/xlamp.asp, 2008.

[Eu08] Phasing out incandescent bulbs in the EU, Technical briefing, 2008.

[Lu09] Lucas, J.: Samsung Begins Producing Ultra-slim, Energy-efficient LCD Panels with Edge-lit LED Backlighting. In Samsung Press Release online available at: http://www.businesswire.com/news/home/20090326005854/en, 2009.

[Os07] Osram Semiconductors: Osram Golden Dragon Datasheet ZW W5SG, 2007.

[Os08] Osram Semiconductors: Osram Ostar Datasheet LE UW E3B, 2008.

[Ow096] Owen, B.: Big Apple goes green with LED pilot projects. In LEDs Magazine, 2009.

[Ph06] Philips Lumileds: Custom Luxeon Design Guide, Application Brief AB 12, 2006.

[Ph07a] Philips Lumileds: Luxeon K2 Datasheet DS51, 2007.

[PT096] Photonics Industry; Technology Development Agency: Taiwan develops LED Cluster in Southern Taiwan Science Park. In LEDs Magazine, 2009; pp. 45–46.

[SSL11] Solid-state lighting research and development. Multi-year program plan. U.S. Department of Energy, Office of Energy Efficiency and Renewable Energy, [Washington, D.C.], 2011.

[St08] Steel, R.: High-Brightness LED Market Overview & Forecast: Proc. Strategies in Light 2008, 2008.

[Ve06] Verband der Automobilindustrie: Leuchtdioden für mehr Sicherheit und Langlebigkeit. In Auto Jahresbericht, 2006, 1; pp. 145-147.

[Wh057] Whitaker, T.: LEDs in the mainstream: technical hurdles and standardization issues. In LEDs Magazine, 2005; p. 44.

[WKM09] Wonbok, L.; Kimish, P.; Massoud, P.: White LED Backlight Control for Motion Blur Reduction and Power Minimization in Large LCD TVs. In Journal of the Society for Information Display, 2009; pp. 1–18.

[WT06] Waide, P.; Tanishima, S.: Light’s labour’s lost. Policies for energy-efficient lighting; in support of the G8 plan of action. OECD, Paris, 2006.

2. Overview of three-dimensional LED-lighting systems

2.1. Introduction

Chapter 1 has shown that enabling LED-lighting systems with an enhanced three-dimensional shape for improved design and functionality is the core topic of this thesis. The main limitations of contemporary assemblies – namely the limited degrees of freedom and the multitude of components needed – have been indicated.

In this chapter an overview of the essential components found in state of the art LED-lighting systems is given with a focus on the required power electronic system (Section 2.2). This includes the components’ technological requirements as well as functions that they have to fulfil.

The technical evolution towards three-dimensional LED-lighting is outlined in Section 2.3 and gives an overview of how contemporary LED-lighting assemblies are able to create 3D-structures.

The technological hurdles but also potentials, identified in Section 2.3, are used in Section 2.4 to derive requirements which should be fulfilled for making enhanced three-dimensional design and versatility in future LED-lighting systems possible.

The chapter will be summarised in Section 2.5.

2.2. LED-lighting systems: components and functions

Modern LED-lighting systems comprise a variety of components that are required to fulfil lighting functions, as already introduced in Chapter 1. Figure 2-1 shows an automotive LED-lighting system used in front lighting, visualised in an exploded view. In this system, all light-functions are realised with LED-technology.

It can be seen from the figure that a multitude of LEDs, circuit carriers for their electrical interconnection, external thermal management and optical components as well as several design elements are required to build high-power LED-lighting systems. The housing and the LED-driver complete the system, but are not shown in this view.

In contrast to the vast majority of (power) electronic systems, LED-lighting devices usually contain the LED-driver as well as the load – the LEDs – in the same enclosure and they are often also attached on the same circuit carrier. The electrical and thermal behaviour of the LEDs, e.g. regarding power losses, has therefore to be considered in the design of the power electronic system. Moreover, the planned design – including the number and size of the LEDs – defines the lamps’ power level as well as the component positions in three-dimensional space.

14 Chapter 2

Figure 2-1: Example: exploded view of automotive front LED-lighting system (Source: AUDI AG)

It can also be deduced from Figure 2-1 that a variety of functional interdependencies appear in LED-lighting systems. For example, the electrical system containing the LED-driver, the LEDs and the circuit carrier is mechanically attached to thermal management components. A part of this structure is further connected to the optical system, and so forth. This leads to a complex combination of single components that are often individually constructed; this challenges the assembly of the final three-dimensional LED-lighting system.

In the following, relevant components of LED-lighting systems with LED-driver will be explained to give an overview of their main functions and requirements. The overview includes the LEDs, the LED-driver, the thermal management components as well as the circuit carrier technology. These components build the “electronic system” in the LED-lamp.

The housing and the optical components will not be discussed further here, as their implementation is out of the scope of this thesis.

Detailed investigations on each domain of the electronic system will be individually performed in Chapters 4-6 to enhance the degrees of freedom of future 3D LED-lighting systems.

2.2.1. Light-Emitting-Diodes (LEDs)

LEDs play a central role in the realisation and assembly of LED-lighting systems. As Light-Emitting-Diodes and their high-power derivatives show a highly different optical, thermal and electrical behaviour compared to incandescent lights a short summary of state of the art LED characteristics and requirements concerning the power electronic system will be given in the following.

LEDs

Design element

Optical systemThermal management

component

Circuit carrier

(Source: Audi AG)

Overview of three-dimensional LED-lighting systems 15

The thesis’ focus lies on white high-power LEDs, as these build the cornerstone for using LEDs in general lighting, e.g. in automotive- or domestic-applications. White light can be created by three different methods using the LED technology [Sc03]:

Multi-colour LEDs can be used to obtain white light by mixing the emission spectra of the individual LED (-chips).

Wavelength converters use ultraviolet or blue LEDs attached with several layers of different phosphors. As a result of this combination, white light is excited. For this reason, the LEDs are also-called Phosphor-Coated (PC-) LEDs.

Semiconductor converters use a primary light source, e.g. a blue LED chip, and an additional active semiconductor region that absorbs a fraction of this optical power and re-emits photons with a longer wavelength. As a composition white light is emitted.

The wavelength-conversion is the most common and widely distributed approach to create white light. This is mainly determined by cost reasons, the simplified drive of single LED-chips and the comparably stable colour values of phosphor-coated LEDs [Sc03], [BSS06]. Hence, general illumination applications and automotive (front) lighting use these types of LEDs and will therefore be focused on in this work.

LED power level

Light-Emitting Diodes are used in a variety of application fields and cover a wide range of light output levels and a variety of colours, as already shown in Chapter 1. Next to the light output, also the power level can be used as criteria to diversify LEDs. Besides it is an important figure to determine the electrical design of the LED-driver as well as for the implementation of an effective thermal management. The latter is linked to the electrical LED-efficiency which shows typical values of 15-20 percent for high power LEDs [QLH09]. The remaining power is dissipated as heat and has to be effectively cooled in the LED-lighting system.

Figure 2-2 gives an overview of common LED power levels with related drive currents, luminous fluxes and typical LED-packages of each power-class. The overview divides the LEDs into three classes that will be referred to subsequently in the thesis:

Low-power LEDs with a power consumption of below PLED=0.3W

High-power LEDs comprise power levels of PLED=0.5-3W as a typical indication of size

Ultra high-power LEDs are mainly realised by combining several high-power LED-chips in a single package, leading to power levels PLED>3W and luminous fluxes of 1000 lumens out of one LED package and higher [Os08].

16 Chapter 2

Figure 2-2: Overview of different LED power levels with selected electrical and photometric properties

Thermal characteristics

Next to the choice of the power class, the design and application of LED-lighting has to focus on LEDs’ thermal characteristics. Although LEDs are inherently robust and long-lasting components [Ph06], one big issue is the influence of the ambient temperature on the LEDs’ light emission and lifetime.

The emission intensity of LEDs decreases with increasing temperature [Sc03]. Furthermore, agradual reduction in light output during lifetime appears. This is called light output degradation [Ph07b]. Next to the insidious decrease in luminous flux, complete LED failures are possible. LEDs can fail with open circuit, e.g. due to broken bond wires, or with short circuit caused by ’threading dislocations’ or by the ’degraded passivation’ [Ba97], [Wu09], [Ar08]. A comprehensive list with details to the LED failure modes is given in [Ar08].

Further, the dominant wavelength and the overall emission spectrum of LEDs is affected by the LED-junction temperature which causes a shift of colour values [Sc03], [BSS06] which could be perceived by the human eye, e.g. at white Multi-colour LEDs.

Considering rough environmental conditions, e.g. defined by automotive applications with a large temperature range from -40°C to +80°C, temperature cycles, mechanical vibrations and shocks, the ideal lifetime of LEDs will be further decreased and cannot be completely ignored in automotive LED-lighting. Especially the thermal management and the LED-driver have to be designed to ensure high system availability.

2.2.2. LED-driver

Common LED-lighting systems contain a multitude of LEDs that have to be driven in a manner that requirements on light output, light distribution and design are fulfilled. A so-called LED-driver is therefore essential to supply the LEDs with the required drive currents and that takes care of their electrical characteristics (Chapter 4).

Low-power High-power Ultra-high -power

Nominal drive current ILED [mA] 30-50 350-1000 >1000

Typical power consumption PLED [W] <0.3 0.5-3 >12

Luminous Flux ΦV [lm] ≤ 15 ≤ 350 >600

Example packages


Apart from that the LED-driver must be able to provide the following essential lighting functions:

Creation of a uniform brightness distribution among a multitude of high-power LEDs

Control of LED brightness with stable colour values

Compensation of single LED failures

The simplest application of an LED-driver can be seen in a constant voltage source connected to a series resistor which defines the current flowing through a string of LEDs. This system,however, suffers from low efficiency due to losses in the current limiting resistor and makes the system unsuitable for high-power LED applications.

In addition, systems with a variable input voltage, e.g. the automotive electrical power net, require more sophisticated solutions that allow driving the LEDs with a stable brightness level over input voltage changes. Therefore, most drivers for high-power LEDs contain a switched mode dc-dc or ac-dc power converter to drive the LEDs. Especially for high voltage applications, where the LEDs are mounted on the surface and are therefore easy to access, a galvanic isolation should also be provided by the LED-driver to decouple the high input voltages from the LEDs.

Power converter topologies used in LED-drivers

In respective papers, a large number of power converters has already been proposed for driving high-power LEDs. This contains non-isolated topologies which are mainly operated directly from (low-voltage) dc networks. Furthermore, isolated topologies have been used to bring solid-state-lighting into applications operating directly from the 230 VAC mains supply.

Figure 2-3 gives a brief overview of published power converters for driving high-power LEDs with an excerpt of respective references. In the field of non-isolated converters, a variety of basic converter topologies have been suggested to act as LED-drivers. This contains boost- [XW08], buck- [Sa08], [Ya09], buck-boost- [TP09b], CUK- [Br08b] and SEPIC- [ZGZ08] converters.

Figure 2-3: Overview of non-resonant power converters used as LED-driver with related references

Isolated topologies like the flyback [Ri05], [Mi09] and forward [Fa06] converter have also been suggested to drive LEDs for mains applications. Likewise, isolated derivatives of SEPIC and CUK converters have been proposed in [Hu08].

LED driver topologies

non-isolated

Buck [XW08]

Boost[Sa08], [Ya09]

Buck-Boost[TP09b]

CUK [Bro08]

SEPIC [ZGZ08]

isolated

Flyback [Ri05], [Mi09]

Forward[Fa06]

CUK SEPIC [Hu08]

18 Chapter 2

Beyond non-resonant LED-drivers, resonant power converters can also be considered for driving LEDs and could be an option to obtain improved EMI behaviour. Resonant converters will not be covered in this work due to already high efficiencies of hard-switching LED-drivers, increased part number of many resonant converters and the pure mass of publications concerning resonant-switching.

Brightness distribution networks

The number of connected LEDs not only determines the power converter topology, but also influences the requirement on so-called brightness distribution networks. When high output voltages are unwanted due to security issues, e.g. above 54V in the conventional 14Vautomotive electrical power net, the number of LEDs that can be driven in a simple series connection gets limited.

As a consequence, it is often required that a single LED-string is split into various series connections which still have to be operated with a uniform brightness distribution. Different solutions have been suggested to obtain this operation mode and external active or passive networks are commonly used to unify LED-brightness levels [PZ08], [MM05], [BZ04], [DZ07]. These networks are therefore also an important component in the LED-driver.

A discussion of LED-driver topologies with brightness distribution networks will be performed detailed in Chapter 4.

Brightness control networks

Finally, brightness control (dimming) has also to be performed by the LED-driver. Two different methods are most commonly used in state of the art systems. The simplest solution is obtained by regulating the dc current flowing through the LEDs, caused by the direct relationship between LED current and luminous flux. An alternative method is Pulse-Width-Modulated dimming (PWM) which is used in the vast majority of LED-lighting. State of the art LED-drivers achieve PWM-control by connecting an additional external dimming networkto the LEDs [NZ04]. The ratio of on- and off-time of an extra dimming switch in the network defines the level of brightness.

A discussion of brightness control solutions and their performances, as well as the development of a novel dimming approach will be introduced in detail in Chapter 4.

LED-driver components

It can be summarized that state of the art LED-drivers typically comprise individual brightness distribution and control networks that have to be combined with the power converter to perform essential lighting functions, shown in Figure 2-4.


Figure 2-4: Components of LED-driver in state of the art systems

2.2.3. External thermal management components

Section 2.2.1 already showed that LEDs are temperature sensitive devices. Their junction temperatures influence the light emission spectrum in terms of wavelengths as well as amplitude. Further, low junction temperatures increase LED-lifetime and light output over time. An effective thermal management implementation is, therefore, required for the LEDs, as well as for the power electronic components in the LED-driver.

Chapter 6 will focus on the discussion of thermal management solutions and their application for three-dimensional LED-lighting systems, separately. However, a short overview on state of the art solutions will be shown here.

Different active and passive heat removal components exist for the cooling of power electronic equipment in general. Their application is dependent on the power class of the entire system, required space, environmental conditions and consequently on the loss density appearing in the system. Figure 2-5 gives an overview of cooling concepts and their thermal efficiency according to [To11].

Figure 2-5: Achievable power dissipation by heat fluxes with various thermal management solutions [To11]

The optimisation of cooling concepts is still a subject of research to find improved designs and boundaries of cooling [Cl05]. Especially the cooling of high-power LEDs is strongly

Powerconverter

Brightnessdistribution

network

Brightnesscontrolnetwork

20 Chapter 2

focused in research and industry as typical LED-efficiencies of 15-20 percent [QLH09] are dramatically lower than those of modern power converters with efficiencies exceeding 80 percent. An overview of thermal management solutions for LEDs is given in [To11].

However, not only external components (Figure 2-5) like heat sinks or cold-plates are part of the thermal management but also the entire pathway from the component to the heat exchange structures. For this reason, also the circuit carrier plays an essential role in the thermal management implementation.

2.2.4. Circuit carrier technology

Figure 2-1 has already indicated that the circuit carrier technology plays a central role in the design and assembly of three-dimensional LED-lighting systems. The circuit carrier’s functions will be defined in accordance with the definition of packaging functions of power converters, introduced by [PF053]. The resulting packaging functions of the circuit carrier are:

Electrical (integrity) function:

o Providing electrical interconnection between the LED-driver components and LEDs and creating electrical isolation

Mechanical (integrity) function:

o Creating mechanical stability and fixation of the electronic components in the LED-lighting system

o Enabling environmental protection for the system and fixation of the optical system

Thermal (integrity) function:

o Fulfilling thermal management functions to transport the heat from the components to an external thermal management component, e.g. heat-sink, or to directly dissipate the heat by itself

It can be derived from the foregoing functions, that the circuit carrier is the linking devicebetween the electrical domain, with electron flow paths, the thermal management, defining heat paths, and the mechanical mounting of the entire system.

The evolution of LED-lighting towards three-dimensional designs is, therefore, strongly linked to the choice and availability of circuit carrier technologies. The next section will be used to describe how state of the art circuit carrier technologies contribute towards the creation of three-dimensional LED-lighting systems and technological shortcomings as well as limitations of contemporary realisations will be summarised.


2.3. Evolution towards three-dimensional LED-lighting

Section 2.2 identified the essential power electronic components and functions they have to fulfil in LED-lighting systems. In this section, the evolution towards three-dimensional LED-lighting systems will be discussed to determine the current practice of realising 3D-structures and to deduce requirements on the realisation of future three-dimensional LED-lighting systems.

A classification of the geometrical degrees of freedom of electronic systems, as defined by [RC08], will be used in the progress of this section to rate the design versatility of state of the art LED-lighting assemblies. Figure 2-6 shows this classification with principle drawings used for illustration.

Figure 2-6: Classification of geometrical degrees of freedom in LED-lighting systems based on [RC08]

The overview shows that circuit carriers can be classified in four different dimensions, ranging from simple two-dimensional (2D) structures to free-form surfaces which equates to a completely three-dimensional (3D) system design. Intermediate stages are defined as 2.5Dand Nx2D. In the prior, parallel shifted planes exist where components are attached, whereas in the latter also angled planes carry electronic components, e.g. LEDs to obtain improved light distributions.

The evolution towards three-dimensional LED-lighting will be presented according to the available circuit carrier technology. Each circuit carrier technology will be characterised in a short manner; the resulting assembly as well as the achievable dimensions will be described and solutions found in the market will be given.

2.3.1. Printed Circuit Board (PCB)-based assemblies

The change from incandescent lighting to LED-lighting in general illumination required a change towards a different circuit carrier technology. Previously, lead frames have been used

Dimensions 2D 2.5D Nx2D 3D

Drawing

Attribute planarcomponent side

planar component side,3D-snaps, ribs on opposite side

different angledplanar component

sides

Standard forms (cylinder, cube,…)

Planar component side,3D-snaps, ribs

Free-formsurfacesdifferent plan parallel

component sides

22 Chapter 2

for contacting of incandescent lamps and could have been found especially in automotive applications. This was possible, as usually no driver electronics has been required to drive the lamp. A direct connection of the lamps to the automotive 14V electrical power has been sufficient.

With LEDs, the number of light sources and LED-driver components increased significantly, which lead to the widespread use of Printed Circuit Boards (PCB) for contacting the LED-lighting systems.

Up to now, the PCB is one of the standard circuit carriers used for conventional LED-lighting systems.

Technology description

The PCB technology offers a standardised and inexpensive solution for contacting electrical components with high reliability and optimised assembly processes due to its wide distribution. It covers almost any electrical application, including power electronic systems [Po05]. Hence, standardised and fully automated processing of Surface Mount Devices (SMT)or of leaded components is available, including high-speed pick & place, as well as soldering and in-line electrical testing.

Additionally, a wide range of copper layer thicknesses, e.g. 35μm, 70μm and 105μm, is available with standard PCB technology. A large span of current levels can therefore be carried by the PCB’s copper tracks, which is sufficient for the majority of LED-lighting applications.

Moreover, the large number of available copper layers on PCBs – up to 48 [Ci12] – make the PCB to a very universal circuit carrier technique that allows solving challenging contacting demands, e.g. complex LED-driver circuits.

Low thermal conductivities of PCB substrates, e.g. FR-4 with λ=0.25W/mK, however, challenge the LED-cooling by means of only the circuit carrier.

PCB-based assemblies

PCBs are inherently two-dimensional devices which initially led to LED-lamps with two-dimensional shape only, shown in Figure 2-7. In this configuration, the PCBs mainly provide contacting and mounting functions for the LEDs as well as for the LED-driver components.

Depending on the power class, the PCB is complemented by an external heat sink with active or passive cooling to dissipate the heat generated by the LEDs and the LED-driver components. Conventional systems use mechanical mounting elements, e.g. screws, to attach the PCB to the heat sink structures, whereas thermal interface materials are used to provide low thermal resistances between both components. The optical system, e.g. a reflector, is mounted in a similar way. Figure 2-7 shows typical examples of PCB-based LED-lamps used in different lighting applications.


Figure 2-7: (a) 2D-LED streetlamp; (b,c) 2D-day-time-running light (top perspective): (b) PCB with LED-driver and heat-sink and (c) with assembled reflector and housing

Because of the PCB‘s two-dimensional shape, a three-dimensional design of LED-lighting systems cannot be achieved with the circuit carrier only. In fact, additional components are required to obtain 3D-arrangements and 3D-electrical interconnection. Therefore, systems emerged that utilize extra supporting structures to create the desired LED-lamp design by fixating individual PCBs in space. These mounting elements are normally realised as injection moulded plastic parts and can sometimes be directly integrated in existing reflectors or lamp housings. However, extra supporting structures are often inevitable for the spatial orientation of LEDs and LED-driver components.

Figure 2-8 shows two examples of automotive lighting that use this assembly. In (a) the lamp housing is used for attaching the PCBs in space whereas the lamp’s reflector is used in (c).

Figure 2-8: 2.5D LED taillight (a,b) and daytime-running-light (c,d) using rigid PCB-based assembly

It can be seen from both examples, that additional wire interconnections are necessary for the spatial contacting of the individual rigid PCBs. The LED-driver can be directly attached to one of the LED-boards or realised separately as external device, with its own PCB and

(b)

(c)

2D PCB

Heat sink


LEDs

Reflector

Housing (bottom part)

(a)

LEDs

Reflector

Housing

Heat sink(Source: DSD Lighting & Electronics)

2.5D assemblies

with rigid PCB technology and

wire interconnections

(a)

Housing

2D PCB

Wire interconnections2D PCB

LEDs2D PCB

LED-driver (external)

Heat sinkLEDs

(c)

ReflectorWire interconnections

2D PCB with heat sink

(b) (d)

24 Chapter 2

individual thermal management, as shown in Figure 2-8 (d). Available construction spaces as well as the option of using pre-manufactured and standardised LED-drivers determine the choice of an integrated or separate LED-driver unit.

As a consequence of the PCB-based assembly a large number of components and production steps are required to build the power electronic system. The assembly of the whole LED-lamp requires additional components and manufacturing steps that have to be performed in 3D,which increases production costs.

Next to the high complexity in the assembly, the PCB solution suffers from a limited degree of freedom in creating three-dimensional structures. Thus, the examples of Figure 2-8 still provide only low degrees of freedom, according Figure 2-6: dimension 2.5D. If more complex shaping is required, assembly efforts will have to be further increased or even won’t be manageable with PCB technology.

2.3.2. Insulated Metal Substrate (IMS)-based assemblies


Not only the limited three-dimensional variance is a shortcoming of the PCB technology, but also the relatively low thermal conductivity of the substrate material can limit applications with high loss density when bulky external thermal management solutions get inevitable (Section 2.3.1).

Insulated Metal Substrates (IMS) have therefore been introduced in many high-power LED-lighting systems [Fa12] to provide significantly enhanced thermal conductivities contributing to less cooling efforts. In content of LED-cooling, IMS structures are also referred to as Metal Core Printed Circuit Boards (MCPCBs). Figure 2-9 shows a typical composition of an IMS.

Figure 2-9: (a) Principle of IMS layer composition [Bea] and (b) IMS application in LED incandescent lamp replacement [co12]

It contains a thin dielectric layer of 76μm to 152μm thickness [Bea] which shows thermal conductivities of λ -2.2W/mK [ORA09], [Pe04]. The dielectric layer links the top copper layer with the metal base plate. The prior has a typical thickness of 17.5μm to 350μm [La], [Bea] which enables a wide range of current levels that can be carried by the IMS. The metal base plate is used for heat spreading as well as to provide mechanical support to the system.

Circuit layerDielectric layerBase layer

(a) (b)

Heat sink IMSLEDs

Opticalsystem

IMS with LEDs

(Source: Berquist)


Common materials are aluminium or copper and show typical thickness levels of 1.6mm,contributing to greatly increased heat spreading performance when compared to FR-4 base material. Thus, higher power levels can be processed without requiring external thermal management solutions. Additional technologies exist where the dielectric and copper layers are directly mounted on a heat sink to decrease the thermal resistance of the entire system[La]. Typical LED applications for an IMS can be found in replacement solutions for incandescent lamps [Ma11], shown in Figure 2-9 (b).

IMS-based assemblies

As IMS use the backside for heat spreading and component cooling, only the front side is available for component placing, leading to reduced circuit density. PCBs are, therefore, often used in combination with the IMS technology to increase package density and to keep costs low [Po05], [Ma10]. Figure 2-10 shows such configuration used in a 230VAC LED-lighting module.

Figure 2-10: (a) LED Module (Source: Cree) with IMS (b) and LED-driver on seperate PCB (c), [Ma10]

In the light of creating three-dimensional LED-lighting systems, no significant differences can be found between IMS and PCB solutions, as the IMS structure is inherently a two-dimensional device that can be processed comparable to PCB technology.

Figure 2-11 (a) shows an example of an IMS-based LED-headlamp with a three-dimensional assembly of LED-driver and LEDs.

Figure 2-11: IMS based LED-headlamp (a) (Source: Blackd Diamond),(b) housing and 2.5D stacking of IMS structure (c) [Mi12]

The LED-driver is mounted on two IMS substrates (c). A plastic supporting structure is furthermore used to stack the IMS substrates in two levels for reduced system footprint leading to a 2.5D-LED-lighting system according to the classification made in Figure 2-6.

(a) (b) (c)

(Source: Cree)

(a) (b) (c)

(Source: Black Diamond)

26 Chapter 2

2.3.3. Flexible Printed Circuit Board (Flex-PCB)-based assemblies


The next step towards creating LED-lighting systems with an enhanced 3D-design has been identified as the application of Flexible Printed Circuit Boards (Flex-PCBs) or rigid-flexible PCBs instead of rigid two-dimensional circuit carriers (Figure 2-12).

Flex-PCBs are built by a combination of a metal foil — in general copper — attached to a polymer foil which creates a flexible system with similar technical characteristics as the PCB technology. Due to their versatility, Flex-PCBs are already used in a variety of applications that require a dynamic or complex three-dimensional interconnection, e.g. in digital cameras, hard-drives, cell phones and even in 3D power converter assemblies [Jo07].

Figure 2-12: Flexible Printed Circuit Boards with LEDs attached

The simplest variant of Flex-PCBs is a single-layer composition containing one base, cover and copper-layer which allows a single-sided component attachment. More advanced Flex-PCBs contain layer stacks of up to 20, where a multiple of single- or double-sided Flex-PCBs are laminated with a thermoset adhesive. This allows complex circuit routing. However, the increasing number of copper layers reduces the circuit carrier’s flexibility, which in turn will limit the possibilities in creating complex spatial configurations.

Furthermore, the number of bending-cycles and -radii is limited and is mainly determined by the adhesion of the polymer base layer and the copper tracks as well as by the brittleness of the circuit tracks. An overview of allowed bending-radii and -cycles for Polyimide (PI), Polyethylene Naphthalate (PEN) and Polyethylene Terephthalate (PET) is given in [P.07].

The substrate behaviour has especially to be considered for lighting systems that work under harsh environmental conditions, e.g. in automotive applications, when vibrations and shocks impact the circuit carrier. In addition, the minimum bending radii require the use of excess material when forming curves or large structures with complex 3D-geometries.

Flex-PCB-based assemblies

LED-lighting systems using Flex-PCBs are assembled similar to those with PCBs or IMS’substrates. To obtain a three-dimensional design, a 3D-supporting structure is still required to

(Source: Osram) (Source: MOLEX)


generate the desired shape und to fixate the flexible circuit carrier. Figure 2-13 shows a typical Flex-PCB-based 3D-LED-lighting assembly.

The figure shows an automotive LED taillight containing the reflector unit, the Flex-PCB, the LED-driver and the thermal-management comprising individual aluminium heat-sink plates.

It can be seen that the Flex-PCB is attached to the reflector unit that serves as 3D-supporting structure. The shape of the reflector is comparable to a stairway where one LED is located at every ‘step’ of the stair. This requires an elaborately fixation at every step of the reflector unit.

In contrast to rigid PCBs, the Flex-PCB allows the contacting of the entire lighting system with a single circuit carrier only. This contributes to a significant reduction of fault-prone wire interconnections between individual circuit carriers and furthermore leads to a reduced component count as well as to decreased manufacturing efforts.

Figure 2-13: 2.5D LED taillight with LED-driver using a Flex-PCB-based assembly with reflector as supporting structure

However, still a large number of components is required to obtain a 3D-geometry. In addition, complex as well as not always fully automated assembly processes are required for the fixation of the Flex-PCB. This makes the production time consuming and fault-prone.

Next to the high complexity in the assembly, the degree of freedom in creating 3D-structures is still limited due to the necessity of the supporting structure and by the limited bending radii of the flexible PCB. Hence, free-form surfaces (Figure 2-6 dimension 3D) are not possible with Flex-PCBs and only 2.5D to Nx2D shapes can be created.

2.3.4. 3D-Moulded Interconnect Device (3D-MID)-based assemblies

The technology group of 3D-Moulded Interconnect Devices (3D-MIDs) emerged as complementary technology to flexible- and rigid-printed circuit boards and promises three-dimensional electronic systems with even more complex 3D-shapes. So far, 3D-MIDs are increasingly used in series applications with low power levels [Fe04], [RC08], [Br08a].


3D-MIDs are injection moulded devices with circuit tracks directly routed on the three-dimensional surface of the injection moulded part [FP98], as visualised in Figure 2-14.

LED-driver

Flex-PCBLEDs

28 Chapter 2

Figure 2-14: Functional principle of 3D-MIDs

The potential of 3D-MIDs to create three-dimensional mechanical structures with integrated routing allows new ways in the exterior- and interior design of components, but furthermore enables the integration of additional external functions in the 3D-MID, e.g. housing, snap joints, stiffeners, battery clamps, connectors, switches, etc. [Fe04], [LHS08]. As a consequence, fewer components are required in contrast to rigid- and flexible-PCB solutions, offering potential to reduce assembly steps and production costs of the entire system at enhanced degrees of freedom.

The achievable geometrical complexity of the 3D-MID substrate is defined by the limits of conventional injection moulding processes, and hence is very high.

A variety of sub technologies emerged over the past decades to create 3D-MIDs which meet the demands on flexibility, degrees of freedom in the design, component size and piece number defined by the considered application. Widely used technologies are 2-shot moulding, hot stamping and insert moulding [Fe04]. However, they suffer from poor flexibility regarding design changes and high costs per part for low volume applications caused by expensive tool costs. To avoid these limitations selective additive and subtractive technologies have been developed as an alternative, e.g. Laser-Direct-Structuring (LDS) [Fe04], Laser-Subtractive-Structuring [SRKN02] and direct writing techniques [Br10]. They allow a high flexibility towards design changes, the realisation of different variants on the same substrate and they allow rapid prototyping [Fe04], [SRKN02].

In addition, the degree of freedom in creating three-dimensional circuit tracks is dependent on the sub- process of 3D-MID production and shows the highest flexibility in the LDS technology [SRKN02]. The enhanced flexibility has already led to a variety of applications using the LDS 3D-MID technology. Laser activated MIDs can be found in automotive applications [RC08], sensor applications [Fe04] and other application fields, such as in medical devices [Br08a].

3D-MID limitations

One of the major limitations of the 3D-MID technology, and especially of laser-direct-structured 3D-MIDs, is their limited copper layer thickness. LDS 3D-MIDs require electroless plating processes, which only achieve low copper deposition rates of only 5-8μm/hour. This causes that conventional LDS 3D-MIDs use copper thickness levels significantly below 20μmto keep the assembly costs low [Ba07]. Whenever higher thickness levels are required,

3D-Substrate 3D-Circuit 3D-MID


additional electroplating processes can be performed, but these increase the production efforts and require a coherent circuit artwork to achieve effective plating.

Alternatively, wider copper tracks can be used to avoid electroplating and to decrease the process time and, hence the plating costs. This is only possible when narrow circuit tracks and low track distances are not required for the contacting nor for compact routing. Thus, a trade-off between track-width and track-thickness has to be found when the ampacity has to be increased for high-power LED-lighting systems.

Furthermore, only the 3D-MID surfaces can be used for circuit routing, as no multilayer processes are usable in series applications, so far. Both aspects lead to the fact that nearly exclusively low-power systems with a minimum on components have been realised on 3D-MIDs, yet.

This is also linked to the challenge of effectively cooling the (power) electronic components when higher power levels are considered. As 3D-MIDs do not allow multi-layer structures, noextra heat spreading layers can be implemented like in PCBs. This issue gets amplified by the limited heat spreading performance of the comparably thin copper layer. Thus, electronic systems that operate with a high efficiency and a uniform loss distribution among its components are advantageous for a 3D-MID realisation. Nevertheless, increasing the heat spreading performance will influence the circuit layout.

In addition, the thermal conductivity of standard polymers, compatible with the LDS process, is low – comparable to FR-4. Further, standard planar heat sinks can often not be attached to the entire three-dimensionally shaped 3D-MID. Using multiple heat sinks on the substrate, however, implies increased part costs and assembly efforts for individual pick-and-place in 3D. This limitation also appears when small SMT heat sinks are considered for the cooling of discrete power electronic components. Research activities, therefore, focus on extending the power handling of 3D-MIDs by modifying the substrate’s thermal conductivity [Ho11], [HF11] and combining active cooling approaches with MIDs [LHS08].

3D-MID-based assemblies

The use of the 3D-MID technology is a relatively new approach that can be found in three-dimensional LED-lighting systems. This is also related to general technological differences of 3D-MID assemblies compared to printed circuit board-based solutions, used in the majority of lighting applications.

As 3D-MIDs build a mechatronic system where mechanical component layout and electrical circuit routing has to be combined in a single component, an integrated design approach is required. Hence, the dependency of the 3D-MID’s spatial construction and the positioning of electronic components as well as of the circuit tracks has to be considered in the system design phase. Thus, special design tools are required to construct 3D-MID devices in a consistent environment [YDJ10] as standard mechanical CAD tools do not consider electrical connections of components and electrical CAD software is typically limited to 2D-PCBs.

30 Chapter 2

The resultant design data are required for the creation of the injection moulding tools, for the programming of the laser structuring pattern as well as for the component processing on the 3D-MID. The latter contains dispensing of soldering paste, the assembly of electronic components as well as soldering which has to be performed in 3D – in contrast to printed circuit board solutions. Special machines like six-axis robot systems or modified pick-and-place machines with additional moving axes are therefore utilized in 3D-MID series applications. Soldering is typically performed with in-line vapour phase soldering machines [Fe04].

Besides the 3D data generation also the physical assembly of 3D-MID-based LED-lighting systems differs from the foregoing technologies. The substrate material of 3D-MIDs is utilised to create mechanical stability in the circuit carrier and to provide electrical isolation between the copper traces, like in PCBs.

However, the thermoplastic substrate material can be spatially arranged by means of the injection moulding process and integrates the function of mechanical connection in three-dimensions and the electrical interconnection of electronic components. No 3D-supporting structures are therefore required to achieve the desired shapes and a single circuit carrier is sufficient to provide contacting functions. This leads to a significantly higher variance in design and functionality compared to printed circuit boards.

Figure 2-15 shows an example LED-lighting system utilising 3D-MID LDS-technology.

Figure 2-15: Compact 3D-MID-based LED system with integrated LED-driver: (a) principle view, (b)multiple units, (Source: Audi AG and MIDTRONIC)

The system uses a 3D-MID for contacting the LED-driver and for the arrangement of the LEDs. Furthermore, housing is directly provided by the circuit carrier. The optical system is also directly fixed by the MID-structure and cooling of the low-power LEDs is performed with the 3D-MID’s copper layer. In contrast to rigid- and flexible-PCB-based assemblies, asignificantly lower number of components is required to generate the lighting system, which in turn allows the generation of compact and slim lighting systems, as shown in the foregoing example.

Next to the aspect of component reduction, assemblies with greatly increased three-dimensional complexity which would not be realisable with PCB-technologies can be realised with 3D-MIDs. Figure 2-16 shows a part of a motorcycle steering grip that integrates several push-bottons in a compact and fully three-dimensional circuit carrier. No external parts are

Optical system

LEDs


(a) (b)

(Source: Audi AG and MIDTRONIC)


used for wiring, as the 3D-MID is used to provide mechanical stability, 3D-shaping and electrical interconnection [RC08] in a single component.

Figure 2-16: 3D-MID-based motorcycle grip with integrated functions [RC08]

Figure 2-17 shows a completely three-dimensional LED-lighting system using a 3D-MID that serves as 3D-circuit carrier and housing of the entire structure. The system is shaped as sphere that contains integrated light-slots that allow the light excitation of 54 low-power LEDs which are distributed in three-dimensions inside the sphere. The system does not contain electronic components except the LEDs that are contacted by the 3D-MID only, by using 3D-circuit tracks on the inside and outside of the sphere. Besides, the thermal management is realised by using the MIDs’ copper-surfaces for heat removal from the LEDs.

Figure 2-17: 3D LED-lighting system with 54 LEDs arranged in free-form sphere structure: (a) concept idea, (b) construction cross-sectional view, (c) and (d) real system shown in different views

It can be derived from the example systems that with 3D-MIDs, geometrical structures get possible that are completely three-dimensional according to the classification in Figure 2-6,which greatly extends the possibilities in design and spatial orientation of components. This gets accomplished by the ability to integrate mechanical functions into the circuit carrier leading to a reduced number of components.

However, 3D-MIDs are only used for low circuit complexity systems and at low power levels so far, as it is essential to keep the number of components low. The reasons are limitations in circuit artwork creation as well as keeping the implementation of thermal management solutions simple.

Push-Buttons3D-substrate

Circuit traces

(Source: Kromberg & Schubert)

(a)3D

circuit tracks

LEDs

Batterycompartment

(b) (c) (d)

(Source: Audi AG)

32 Chapter 2

2.4. Requirements on future 3D LED-lighting systems

2.4.1. Conclusions on evolution towards three-dimensional LED-lighting

It can be concluded from the overview of contemporary 3D LED-lighting systems that a multitude of parts has to be assembled to a complex system for providing lighting and design functions. The high complexity is also reflected in the current practice of building LED-drivers containing a power converter as well as separate networks for dimming and brightness distribution, required to cope with the electrical and photometric requirements of high-power LEDs.

The evolution towards three-dimensional LED-lighting (Section 2.3) further shows that the chosen assembly, with its required components, is not only defined by the number and power level of the LEDs. The available circuit carrier technology strongly defines the assembly effort and components required, as it is the linking device between electronic, cooling, optical and housing components (Figure 2-7 to Figure 2-13). Whilst PCB- and IMS-structures are able to cover a wide range of power levels, their ability to create three-dimensional structures is limited. This is caused by their purely 2D-shape, which requires complex mounting solutions with a multitude of components, e.g. wire-interconnections and supporting structures.

The evolution further shows that with the introduction of a more versatile circuit carrier that is able to provide (limited) three-dimensional contacting – the Flex-PCB technology – improved degrees of freedom emerged in the design of LED-lighting systems, whilst simultaneously the assembly efforts and the number of components decreased. However, the 3D-versatily of Flex-PCB assemblies is still limited (Section 2.3.3).

Right now, 3D-MID assemblies arise which are capable to provide higher degrees of freedom for low-power LED-lighting systems. They offer the ability to integrate additional functions into the circuit carrier, contributing to assemblies with a low number of components. However, 3D-MIDs have not been faced with the challenges of realising three-dimensional high-power LED-lighting systems with LED-driver, yet.

2.4.2. Requirements for future 3D LED-lighting systems

The foregoing evolution towards three-dimensional LED-lighting can be used to identify requirements that have to be fulfilled to enable future applications with enhanced three-dimensional shaping. The requirements can be summarised in four points:

1. Increased degrees of freedom in spatial design: The degrees of freedom of the LED system have to be increased to fulfill rising demands on 3D-design and 3D-integration of lighting functions. The versatility of the circuit carrier technology contributes significantly to the dimensions the entire system can achieve, and should therefore be increased.


2. Integration of mechanical and electrical functions: Three-dimensional supporting structures are widely used to achieve 3D-shaping of LED-systems, but limit the design variances and cause increased manufacturing costs and efforts which gets amplified with rising 3D-complexity. The circuit carrier should, therefore, be able to provide electrical contacting and mechanical mounting in three-dimensions in a single and robust component by itself.

3. Integration of the LED-driver: The complexity of the LED-driver defines the number of components that have to be attached in three-dimensions and furthermore defines the layout complexity the circuit carrier has to be capable of. This also defines if additional circuit carriers are required for the contacting of the electronic components, e.g. for the LED-driver. Thus, a reduced complexity in the LED-driver is beneficial for simplified routing and contacting of the power electronic components.

4. Integration of thermal management functions: Solutions that operate without external thermal management solution whilst maintaining the desired 3D-shape are needed to obtain simplified heat removal with low assembly complexity.

The 3D-MID technology meets the foregoing requirements on future 3D LED-lighting systems for low-power solutions without LED-driver, already. It shows a high versatility toachieve complex three-dimensional designs and offers the ability to integrate mechanical functions into the circuit carrier, as required for future systems.

However, limitations and possibilities of the 3D-MID technology for realising LED-lighting systems with increased power level and integrated LED-driver have not been investigated, so far. This requires investigations on the implementation of LED-drivers, on the routing and spatial realisation of power electronics on 3D-MIDs as well as on the thermal management design.

Chapter 3 will introduce an approach to determine the implementation of 3D LED-lighting systems with high-power LEDs and LED-drivers on 3D-MIDs.

2.5. Summary

In this chapter, an overview of the essential components of LED-lighting systems was given to show the present practice of realising LED-lamps and to describe the evolution towards three-dimensional LED-lighting.

Section 2.2 focused on the components of the lamps’ electronic system to define essential component characteristics and requirements that have to be considered when designing LED-lighting systems. An overview on contemporary LED-driver solutions has been given and shows the necessity on power electronics to fulfil essential lighting functions. In Section 2.3the evolution towards the assembly of three-dimensional LED-lighting systems has been outlined.

34 Chapter 2

The circuit carrier is identified in this chapter as central element in the LED-lighting system, as it strongly defines the number of components that are required in the assembly. Besides, it influences significantly the degrees of freedom concerning the lamp construction.

The evolution towards 3D LED-lighting systems is used to determine requirements that have to be fulfilled to make future LED-lighting systems with enhanced three-dimensional -design and -versatility possible (Section 2.4). It is identified that technologies that are able to provide increased spatial degrees of freedom and function-integration could be used to enhance future LED-lighting systems.

The 3D-MID technology is identified as technology that is already able to meet the requirements on mechanical- and electrical-function integration for 3D-LED-lighting systems with low power levels and low complexity. However, taking the 3D-MID technology into new applications of LED-lighting systems with increased power level and integrated LED-driver has not been investigated, so far.

An approach to determine the implementation of future 3D LED-lighting systems with high-power LEDs and LED-driver on 3D-MIDs will be introduced in Chapter 3.

Bibliography [Ar08] Arnold, J.: When the Lights Go Out: LED Failure Modes and Mechanisms. In Electrical

Source Magazine, 2008, Dfr Solutions.

[Ba07] 3D-MID Bayer Kunststoffe, 2007.

[Ba97] Barton, D.; Osinski, M.; Perlin, P.; Helms, C. et al.: Life tests and failure mechanisms of GaN/AlGaN/InGaN light emitting diodes: Proc. IEEE International Reliability Physics Symposium 35th Annual, 1997; pp. 276 281.

[Bea] Berquist Company: T-Clad Overview: Circuit Design Guidelines.

[Br08a] Brand, A. Ed.: Developing Technical and Economical Potentials in MID with Successful Serial Products, 2008a.

[Br08b] Britto, J. de; Demian, A.; Freitas, L. de; Farias, V. et al.: A proposal of LED Lamp Driver for universal input using CUK converter: Proc. IEEE Power Electronics Specialists Conference PESC 2008, 2008b; pp. 2640 2644.

[Br10] Brose, A.; Leneke, T.; Hirsch, S.; Schmidt, B.: Aerosol deposition of catalytic ink to fabricate fine pitch metallizations for moulded interconnect devices (MID). In 2010 3rd Electronic System Integration Technology Conference (ESTC), 2010; pp. 1–4.

[BSS06] Bernitz, F.; Schallmoser, O.; Sowa, W.: Advanced Electronic Driver for Power LEDs with Integrated Colour Management: 41st IAS Annual Meeting Industry Applications Conference Conference Record of the 2006 IEEE, 2006; pp. 2604 2607.

[BZ04] Baddela, S.; Zinger, D.: Parallel connected LEDs operated at high frequency to improve current sharing. In (Zinger, D. Ed.): 39th IAS Annual Meeting Industry Applications Conference Conference Record of the 2004 IEEE, 2004; pp. 1677 1681 vol.3.

[Ci12] CircuitMart Inc.: PCB Capability, 2012.

[Cl05] Clemens J. M. and Lasance, a. R. E. S.: Advances In High-Performance Cooling For Electronics, 2005.

[co12] cocasdaneve: Cheap E14 3W LED bulb teardown, online avilable at: http://cocasdaneve.wordpress.com/2012/04/11/cheap-230v-3w-led-bulb-teardown/, 2012.

[DZ07] Doshi, M.; Zane, R.: Digital Architecture for Driving Large LED Arrays with Dynamic Bus Voltage Regulation and Phase Shifted PWM. In (Sauerlander, G. Ed.): Proc. APEC 2007 - Twenty Second Annual IEEE Applied Power Electronics Conference, 2007; pp. 287 293.

[Fa06] Fan, Y.; Wu, C. F. C.; Chih, K.; Liao, L.: A Simplified LED Converter Design and Implement: Proceedings of the 9th Joint Conference on Information Sciences (JCIS), 2006.

[Fa12] Fan, A.; Bonner, R.; Sharratt, S.; Ju, Y. S.: An innovative passive cooling method for high performance light-emitting diodes: Proc. 28th Annual IEEE Semiconductor Thermal Measurement and Management Symp. (SEMI-THERM), 2012; pp. 319 324.

[Fe04] Feldmann, K. Ed.: Technologie 3D-MID. Räumliche elektronische Baugruppen ; Herstellungsverfahren, Gebrauchsanforderungen, Materialkennwerte. Hanser, München, 2004.

[FP98] Feldmann, K.; Pohlau, F.: MID in the automotive industry-potentials, benefits and applications. In 1998. IEMT Europe 1998. Twenty Second IEEE/CPMT International Electronics Manufacturing Technology Symposium, 1998; pp. 76–81.

[HF11] Hörber, J.; Franke, J.: Thermisch leitfähige Kunststoffe für kostengünstige Fertigung und erweiterte Funktionalität in der MID-Technologie, 2011.

[Ho11] Hoerber, J.; Mueller, M.; Franke, J.; Ranft, F. et al.: Assembly and interconnection technologies for MID based on thermally conductive plastics for heat dissipation. In 2011 34th International Spring Seminar on Electronics Technology (ISSE), 2011; pp. 103–108.

[Hu08] Huang, H.-M.; Twu, S.-H.; Cheng, S.-J.; Chiu, H.-J.: A Single-Stage SEPIC PFC Converter for Multiple Lighting LED Lamps: Proc. 4th IEEE International Symposium on Electronic Design, Test and Applications DELTA 2008, 2008; pp. 15 19.

[Jo07] Jong, E. C. W. de: Three-dimensional integration of power electronic converters on printed circuit board. PhD Thesis, 2007.

[La] Laird Technologies: Thermally Conductive PCB Materials.

[LHS08] Leneke, T.; Hirsch, S.; Schmidt, B.: A multilayer process for fine-pitch assemblies on molded interconnect devices (MIDs), 2008; pp. 663 668.

[Ma10] Margery, C.: Cree's LMR4 LED light module: What's inside, and how TrueWhite works, online avilable at: http://www.edn.com/electronics-blogs/led-zone, 2010.

[Ma11] Margery, C.: LED bulbs reveal different design approaches, online avilable at: http://www.edn.com/design/led/4369641/LED-bulbs-reveal-different-design-approaches, 2011.

[Mi09] Mineiro Sa, E.; Postiglione, C.; Santiago, R.; Antunes, F. et al.: Self-oscillating flyback driver for power LEDs: Proc. IEEE Energy Conversion Congress and Exposition ECCE 2009, 2009; pp. 2827 2832.

[Mi12] Mirowski, D.: Black Diamond Storm - 100 lumens in compact waterproof case, online avilable at: http://www.light-test.info/, 2012.

[MM05] Marques, L. S.; Mineiro, E. S., JR: Step Down Current Controlled DC-DC Converter to Drive a High Power LED Matrix Employed in an Automotive Headlight: Proceedings of the 8th COBE, 2005; pp. p474-478.

[NZ04] Narra, P.; Zinger, D.: An effective LED dimming approach. In (Zinger, D. Ed.): 39th IAS Annual Meeting Industry Applications Conference Conference Record of the 2004 IEEE, 2004; pp. 1671 1676.

[ORA09] Oliver, G.; Roberts, K.; Amey, D.: Benchmark Study of Metal Core Thermal Lamintes. In IMAPS Device Packaging Conference, 2009.


[P.07] P.M.C. Leiterplatten Technology GmbH: Laminate für Flexleiterplatten, 2007.

[Pe04] Petroski, J.: Spacing of high-brightness LEDs on metal substrate PCB’s for proper thermal performance: Proc. Ninth Intersociety Conf. Thermal and Thermomechanical Phenomena in Electronic Systems ITHERM ’04, 2004; pp. 507 514.

[PF053] Popovic, J.; Ferreira, J.: An approach to deal with packaging in power electronics. In IEEE Transactions on Power Electronics, 2005, 20; pp. 550–557.

[Ph06] Philips Lumileds: Custom Luxeon Design Guide, Application Brief AB 12, 2006.

[Ph07b] Philips Lumileds: Luxeon K2 Reliability, Releibility Datasheet RD 06, 2007.

[Po05] Popovic, J.: Improving packaging and increasing the level of integration in power electronics. PhD Thesis, 2005.

[PZ08] Patterson, J.; Zane, R.: Series input modular architecture for driving multiple LEDs: Proc. IEEE Power Electronics Specialists Conference PESC 2008, 2008; pp. 2650 2656.

[QLH09] Qin, Y. X.; Lin, D. Y.; Hui, S. Y. R.: A Simple Method for Comparative Study on the Thermal Performance of Light Emitting Diodes (LED) and Fluorescent Lamps: Proc. Twenty-Fourth Annual IEEE Applied Power Electronics Conf. and Exposition APEC 2009, 2009; pp. 152 158.

[RC08] Rega, E.; Czabanski, J. Eds.: The PCB conquers space, 2008.

[Ri05] Rico-Secades, M.; Calleja, A.; Ribas, J.; Corominas, E. et al.: Evaluation of a low-cost permanent emergency lighting system based on high-efficiency LEDs: IEEE Transactions on Industry Applications, 2005; pp. 1386 1390.

[Sa08] Sarhan, S.: A novel fixed-frequency dimming scheme with ultra-wide, high-frequency dimming range: Proceedings of the Power Conversion Intelligent Motion Conference, 2008.

[Sc03] Schubert, E. F.: Light-Emitting Diodes. Cambridge University Press, 2003.

[SRKN02] Schlueter, R.; Roesner B.; Kickelhain L.; Naundorf G.: LPKF-LDS-technology - a laser supported fully additive process to manufacture three dimensional circuit boards for mechatronic applications: International Congress on Molded Interconnect 2002.

[To11] Tong, X. C.: Advanced materials for thermal management of electronic packaging. Springer, New York, 2011.

[TP09b] Thomas, W.; Pforr, J.: Buck-Boost converter topology for paralleling HB-LEDs using constant-power operation: Proc. The Eighth International Conference on Power Electronics and Drive Systems, PEDS 2009, 2009.

[Wu09] Wu, F.; Zhao, W.; Yang, S.; Zhang, C.: Failure modes and failure analysis of white LEDs: Proc. 9th International Conference on Electronic Measurement & Instruments ICEMI ’09, 2009; pp. 4-978 4-981.

[XW08] Xu, X.; Wu, X.: High dimming ratio LED driver with fast transient boost converter: Proc. IEEE Power Electronics Specialists Conference PESC 2008, 2008; pp. 4192 4195.

[Ya09] Yang, Z.-Z.; Liu, Y.-H.; Chen, P.-Y.; Huang, J.-W.: Sequential-color voltage-adaptable RGB-LED backlight driving system with local dimming control for LCD panels: Proc. International Conference on Power Electronics and Drive Systems PEDS 2009, 2009; pp. 1542 1546.

[YDJ10] Yong, Z.; Du Xiaolei; Jianqiang, Z.: A electromechanical parts library for 3D-MID design. In 2010 IEEE 11th International Conference on Computer Aided Industrial Design & Conceptual Design (CAIDCD), 2010, 1; pp. 17–21.

[ZGZ08] Zhongming Ye; Greenfeld, F.; Zhixiang Liang: Design considerations of a high power factor SEPIC converter for high brightness white LED lighting applications: Proc. IEEE Power Electronics Specialists Conference PESC 2008, 2008; pp. 2657 2663.

3. Enabling 3D-MID-based high-power LED-lighting systems

3.1. Introduction

In the previous chapter, the current construction of LED-lighting systems has been summarised; besides, requirements that have to be fulfilled for enabling future applications with improved three-dimensional design have been identified. The 3D-MID technology has been considered as technology to improve future 3D LED-lighting systems, as it is increasingly used as circuit carrier to enhance three-dimensional low-power LED-systems without LED-driver (Section 2.3.4), already.

However, limitations and perspectives of the 3D-MID technology for realising LED-lighting systems with increased power level and integrated LED-driver have not been investigated, so far. This chapter introduces an approach to enable future 3D LED-lighting systems with high-power LEDs and LED-driver on 3D-MIDs, based on the observations made in Section 2.4. The requirements on future LED-systems that challenge a 3D-MID realisation are further discussed in Section 3.2.

Section 3.3 translates these requirements into three domains that have to be investigated in the future chapters. The domains and investigation steps that are necessary will be briefly introduced. These domains will be investigated in detail in the subsequent Chapters 4 to 6 to determine the concept’s limitations as well as to develop solutions for enabling 3D-MID-based high-power 3D LED-lighting systems.

The chapter is summarized in Section 3.4

3.2. 3D-MID-based high-power LED-lighting systems

The evolution towards 3D LED-lighting in Section 2.3 has shown that a wide range of applications contain LED-driver and LEDs which are assembled in one enclosure and attached to the same circuit carrier to avoid external LED-driver solutions with individual thermal management and housing components.

Especially these systems are limited in their possibilities to create 3D-designs, as the demand on complex shaping has to deal with the current practice of assembling LED-lighting systems. These comprise a large number of construction components that have to be assembled together which lead to the fact that only 2.5D- to Nx2D geometries (Section 2.3) can be realised.

40 Chapter 3

3.2.1. Concept idea

In Section 2.4 four requirements have been identified to enhance the design and the versatility of future three-dimensional LED-lighting systems. Figure 3-1 repeats these requirements and furthermore identifies the two main themes these requirements focus on.

Figure 3-1: Overview of requirements on future 3D LED-lighting systems aiming to two central themes

It can be seen from the figure, that obtaining a high flexibility in 3D-design as well as decreasing the number of components are essential parameters that should be focused on to enhance the degrees of freedom of future LED-lighting systems. In addition, the latter helps to reduce the efforts in the assembly of complex 3D-shapes.

Both themes are directly linked to the available circuit carrier technology and its three-dimensional shaping possibilities, as identified from the evolution towards 3D LED-lighting systems in Section 2.3.

A concept that uses a 3D-MID not only as a 3D Moulded Interconnect Device, but furthermore as “3D Multi-functional Interconnect Device” that performs spatial, electrical and thermal functions is suggested in this thesis to make future LED-lighting systems with enhanced three-dimensional shaping possible. Figure 3-2 visualises the proposed concept in aprinciple view with involved components and shows their gearing to meet the requirements of future 3D LED-lighting systems.

The figure further addresses the key functions of each component:

The 3D-MID integrates the functions of electrical contacting and mechanical mounting of the LEDs and the LED-driver in three-dimensions in a single component. It therefore substitutes supporting structures and wire-interconnections used in contemporary solutions. Besides, the 3D-MID is considered to perform thermal management functions to transport and dissipate the heat from crucial components.

The LED-driver is used to enable the lighting functions required in the system, as defined in Section 2.2.2. Its power-level and topology is dependent on the chosen application which defines the LED-power class, the LED-number, etc.

External thermal management components are considered to extend the heat transport capabilities when increased performance is required that exceeds the MID’s possibilities.

2. Integration ofmechanical and

electrical functions

3. Integration of the LED-driver

4. Integration of thermal management

functions

Requirements on future 3D LED-lighting systems

Central themes Decreasing the number of required components

1. Increased degrees of freedom

Maintaining a high 3D-flexibility

Enabling 3D-MID-based high-power LED-lighting systems 41

Figure 3-2: Concept definition with 3D-MID as multi-functional device and related functions

Thus, the 3D-MID can be seen as linking device between the power electronic components of the LED-driver, the LEDs and (optional) external thermal management components, as indicated with the chosen visualisation of three teethed gear-wheels in Figure 3-2.

Furthermore, it can be seen that the concept aims to maintain a low number of components for decreased number of complex assembly steps that have to be performed in 3D.

The basic idea of integrating (packaging) functions is similar to approaches made to decrease the complexity of power-converter assemblies and power-modules, as done in [Po05], [Ge05], [Pa06], [Jo07].

However, the aim in this thesis is to increase 3D-shaping possibilities and to decrease component numbers rather than increasing power density. Moreover, the possibility to realise the entire LED-lighting system with power electronics and LEDs is considered here to obtain the desired enhanced 3D-design, rather than enhancing the 3D-shape of the power-electronic LED-driver.

3.2.2. Concept challenges

Chapter 2 described that 3D-MIDs are able to integrate electrical and mechanical functions to enhance the functionality and to decrease the number of components of low-power applications that show a manageable circuit complexity. This can be combined with 3D-MIDs’ enhanced spatial possibilities to optimise such systems.

However, when the MID is considered as multi-functional component to enhance LED-lighting systems with higher power levels, new challenges arise for a 3D-MD application.

3D-MIDLED-driver

andLEDs

Externalthermal

managementcomponents

(optional)

3D-MID

Functions:

Mechanical fixation in 3D and environmental protection

Electrical contacting of LED-driver and LEDs in 3D

Heat transport and dissipation

Functions:

Extended heat transport and dissipation

Functions:

Brightness distribution control

Brightness level control

LED-failure compensation

42 Chapter 3

These are mainly determined by increased power levels, leading to increased power losses and demanding (more) complex LED-drivers that have to be implemented on the 3D-MID.

If we consider the requirements on future 3D LED-lighting systems (Figure 3-1), the following main challenges on the proposed concept can be identified (assorted to the requirements):

Integration of the LED-driver

a. High-power LEDs require LED-drivers with power converter as well as brightness control and distribution solutions to fulfil lighting functions.

b. Contemporary LED-drivers are designed for PCB-based assemblies that allow complex routing; an application on 3D-MIDs is therefore challenging.

Integration of spatial - and electrical-functions

a. Increased current levels have to be carried by the 3D-MID’s thin circuit tracks.

b. Routing and spatial arrangement of LEDs and LED-driver, containing a switched mode power converter, is required on 3D-MID’s restricted copper layer number whilst maintaining the LED-driver’s electrical performance.

Integration of thermal management functions:

a. Increased power losses appear in LEDs and LED-driver that challenge the heat dissipation capabilities of 3D-MIDs.

b. External thermal management solutions might get inevitable – comparable to state of the art PCB-based systems (Section 2.3.1) – which require a 3D-assembly.

The concept of using the 3D-MID as a multifunctional component that integrates electrical, spatial and thermal functions has to deal with these challenges. The following section will be used to identify the domains that have to be investigated to make the concept possible.


3.3. Making 3D-MID-based high-power LED-lighting possible

It has been observed in the previous sections that the 3D-MID has to perform electrical, spatial and thermal functions to enable 3D-MID-based high-power LED-lighting systems.Figure 3-3 shows the key domains that have to be investigated by using the previously discussed requirements and challenges as input parameters.

Figure 3-3: Investigation domains to enable 3D-MID-based LED-lighting concepts

The figure shows that the LED-driver topologies, the spatial- and electrical design as well as the thermal management are identified as design domains that have to be investigated in detail to make the concept possible. The figure further shows essential parameters that have to be considered in these domains to meet the challenges defined in Section 3.2.2.

The three domains are similar to those investigated in research and literature for optimizing power converters or power modules in an integral manner including the electrical-, thermal- and spatial-design to obtain high-power density, as shown in [Ge05], [Po05], [Pa06]. In contrast to these approaches, the aim in this work is not to enhance power density, but moreover to increase the 3D-shaping potential and therefore to allow new ways in design or to provide new functionality.

In addition, the technological limitations and possibilities are not clear when 3D-MIDs are considered as circuit carrier for power-electronic systems (with increased power level). It is furthermore expected from the circuit carrier configuration in terms of substrate material and available copper layers that the achievable power-level of 3D-MID-based assemblies will be defined by limitations arising from the requirements on:

Integration of functions

Complexity reduction

Component reduction

Determination of routing limits and possibilities

Determination of electrical and spatial performance

Determination of cooling options and of thermal boundaries of 3D-MID

Increase of power level with external cooling solution

Integration of spatialand electrical

functions

Integration of LED-driver functions

Integration of thermal management

functions

44 Chapter 3

Complex circuit routing

Increased current carrying capacity

Enhanced heat-transport and -dissipation

An essential part of the investigations to follow in this thesis is, therefore, the determination of possibilities and limitations of realising LED-drivers as power-electronic systems on 3D-MIDs. This contains the three domains shown in Figure 3-3, which will be shortly introduced in the following three sections.

Chapters 4 to 6 will focus on each domain, in detail.

3.3.1. LED-driver topologies

The LED-driver’s topology is an essential cornerstone for the design of the LED-lighting system. Reasons are the limited routing options and current carrying capacity of 3D-MIDs that restricts the routing of complex topologies with a multitude of components. Furthermore, when the 3D-MID is supposed to perform thermal management functions, e.g. by using its copper layer for heat-transport, routing and thermal-management, these functions may collide (Section 2.3.4).

Consequently, the choice of the LED-driver topology has a significant influence on the electrical and spatial design of the 3D-MID-based lighting system and can further determine the thermal-management implementation.

However, contemporary LED-drivers are designed for PCB-based assemblies that allow complex routing and are not designed for a 3D-MID application.

Chapter 4 of this thesis will, therefore, focus on the development of LED-drivers for simplified 3D-MID application, in detail.

Those are aimed to fulfil required lighting functions while working with a:

low number of components

simple circuit layout

In Chapter 4, technological limitations of contemporary solutions for 3D-MID application will be identified and adapted LED-drivers will be developed.

3.3.2. Spatial- and electrical design

High-power LED-lighting requires increased current levels that have to be carried by the 3D-MID circuit tracks, which gets reflected in enlarged circuit trace dimensions whencompared to conventional low-power systems.

This influences the spatial realisation of single circuit tracks and therefore also changes circuit track parasitics which has to be considered.


The central aims of the spatial and electrical design are to systematically determine

the influences of the 3D-MID technology on the spatial realisation of power converter layouts

how the electrical performance of power converters gets affected by resulting circuit track parasitics

Both domains can be used to derive the power level that can be processed from an electrical point of view, which is essential for future designs of power electronic systems on 3D-MIDs. Further, investigations will be performed to address the spatial and electrical design of power-electronics on 3D-MIDs and to identify techniques to determine the resulting merits and limitations.

The spatial and electrical design of power converters on 3D-MIDs will be discussed in detail in Chapter 5.

3.3.3. Thermal management design

The thermal management design is used to determine cooling solutions and boundary conditions for enabling high-power LED-lighting systems on 3D-MIDs.

The power classes of LEDs, with their respective LED-driver, are strongly linked to the thermal management, as those define the power that has to be dissipated from the 3D-MID.

In the most convenient solution the 3D-MID is able to dissipate the heat from the components, but will probably not be sufficient for increased power levels. The main themes of the thermal management design are the determination of:

the power that can be transported and dissipated by the 3D-MID itself

solutions that can be used to extend the power level that can be cooled on 3D-MIDs without limiting the 3D-shaping possibility

Chapter 6 of this thesis will discuss the thermal design of LED-lighting systems on 3D-MIDs in detail and will show technological possibilities and limitations.

3.3.4. Interrelation between domains

The concept of using the 3D-MID as multifunctional component causes that the domains of LED-driver topology, spatial and electrical design as well as thermal management design are linked, as already indicated with the gearing of components, shown in Figure 3-2.

The 3D-MID acts as a mechanical fixation of the LEDs and LED-driver components. Besides, it contacts the LEDs with the LED-driver. The converter’s power level and topology is

46 Chapter 3

dependent on the LED-power class, and therefore influences the required ampacity of the circuit tracks on the interconnect medium.

Power losses in the LEDs link the domain of thermal management with the circuit carrier, as generated heat has to be dissipated from the LEDs. Further, the LED-driver efficiency will determine its losses which in turn are applied to the 3D-MID. The heat generated by the converter components has to be effectively conducted and dissipated by the circuit carrier.

Greatly improved coupled simulations and integral design methods exist to determine a combined view of such interactions in general, e.g. with Finite Element Modelling or the Finite Difference Technique to model resulting thermal pathways dependent on the physical circuit layout [FL09], [AN12], [Pa05], [Ja94]. A trade-off analysis can be supported by combined thermal- and electrical simulations that determine component temperatures and circuit layout parasitics simultaneously, which has been demonstrated for power electronic module applications in [Ch01], [Jo02].

Developing an integral design method for 3D-MID-based high-power LED-lighting systems is out of the focus of this thesis, as central limitations and possibilities have to be determined for the 3D-MID application, first. Nevertheless, the interrelation between the three design-domains will be considered throughout the work and will not be neglected. Solutions and approaches to combine the design domains will be commented in the corresponding sections.

A prototype will be shown in Chapter 7 which uses the results obtained from Chapters 4 to 6to determine a design of a high-power LED-lighting system for 3D-MIDs. The prototype combines the entire LED-lighting system on a single circuit carrier.

3.3.5. Spatial configurations

The interrelations between the three design domains are also influenced by the spatial orientation of LEDs and LED-driver. From a spatial point of view, two principalconfigurations can be generally obtained and will be compared briefly. Their application is mainly dependent on the available space in the LED-lamp. Figure 3-4 visualises both configurations in principle cross-sectional views.

Figure 3-4: Principle configurations of LEDs, LED-driver and 3D-MID

Configuration 1 – single sided Configuration 2 - double sided


LEDs


LEDs

3D-MID


Configuration 1 – single sided

In the first setup, the LEDs and the power converter are arranged on the same side of the circuit carrier. The benefits of this solution are that the LEDs and the other components can be directly connected on the same surface. Hence, vias are not required and the circuit carrier can be processed from a single side, without flipping the interconnect medium. In addition, the circuit carrier’s backside is available as increased routing area or to attach external cooling solutions. Furthermore, no thermal cross coupling between heat sources, which are connected on opposite sides of the circuit carrier, appears.

On the contrary, an enlarged footprint size is required when a single side component assembly is considered. This might be limiting for applications with restricted constructed space, as the LED-position is normally fixed due to optical reasons. Hence, the circuit traces and (power) electronic components have to be placed in the remaining area. Further, the placing of optional reflectors in the LED lamp has also to be considered. Thus, this solution is only applicable to LED-lighting systems which provide enough space between the LEDs.

Configuration 2 – double sided

The second configuration separates the LED-driver components and the LEDs by the 3D-MID. Thus, the LEDs are situated on the front-side of the circuit carrier and the driver components on the back-side of the LED-lamp. This makes the solution especially applicable when the LEDs are arranged in a close distance. The separation of LEDs and the power converter allows the usage of wider circuit tracks for the contacting, as routing space is generally not as limited as in the prior concept. The solution can also be considered to obtain galvanic isolation by the circuit carrier, when a contactless power transfer is possible, e.g. by transformer coupling.

The drawbacks of this configuration are that the 3D-MID has to be processed from both sides. In addition, heat sources could be attached on contrary sides which might influence component temperatures among each other. Further, the 3D-MID backside is not available to attach powerful external cooling structures.

Both spatial configurations will be addressed throughout the thesis in the Chapters 4 to 6.

3.4. Summary

In this chapter, a concept for 3D-MID-based LED-lighting systems with high-power LEDs has been introduced which will be followed throughout this thesis.

The requirements on future 3D LED-lighting systems that have been identified in Section 2.4 are used to determine a concept of using a 3D-MID as multi-functional device that performs spatial, electrical and thermal functions (Section 3.2). The aim is to decrease component count whilst increasing the three-dimensional shaping possibilities. In addition, concept challenges that arise when high-power LEDs are used are identified.

48 Chapter 3

In the next step, the requirements on future LED-lighting systems and identified concept challenges are translated into three domains that have to be investigated to make 3D-MID-based high-power LED-lighting systems possible (Section 3.3).

The LED-driver topology defines the circuit complexity and the number of components that have to be connected on the 3D-MID. The LED-driver complexity must, therefore, be low to enable a simplified spatial-, electrical- and thermal- design of the entire system.

The system’s spatial- and electrical design is determined by the available routing options and circuit trace parameters of 3D-MIDs and has to be investigated to predict the influence of the 3D-MID technology on the spatial realisation, but moreover, on the electrical performance of integrated power electronic LED-drivers.

The third domain, that has to be focused on, is the thermal management as heat removal solutions available with 3D-MIDs will define the manageable power-level and it might also influence the achievable three-dimensional shape of the LED-lighting system. It is, therefore, required to determine the available heat transfer by the 3D-MID itself and to derive solutions to extend the power level of 3D-MIDs without undermining its versatile 3D-shaping possibilities.

Chapters 4 to 6 will be used to investigate the feasibility, solutions and limitations of 3D-MID-based high-power 3D LED-lighting systems in the three identified domains, in detail.

Bibliography [AN12] ANSYS, Inc: ANSYS, 2012.

[Ch01] Chen, J. Z.; Wu, Y.; Gence, C.; Boroyevich, D. et al.: Integrated electrical and thermal analysis of integrated power electronics modules using iSIGHT: Proc. Sixteenth Annual IEEE Applied Power Electronics Conf. and Exposition APEC 2001, 2001; pp. 1002 1006.

[FL09] Forster, S.; Lindemann, A.: Combined optimisation of thermal behaviour and electrical parasitics in Power Semiconductor components: Proc. 13th European Conf. Power Electronics and Applications EPE ’09, 2009; pp. 1 10.

[Ge05] Gerber, M. B.: The Electrical, Thermal and Spatial Integration of a Converter in a Power Electronic Module. PhD Thesis, 2005.

[Ja94] Jamieson, D. J.; Mansell, A. D.; Staniforth, J. A.; Tebb, D. W.: Application of finite difference techniques for the thermal modelling of power electronic switching devices: Proc. Fifth Int Power Electronics and Variable-Speed Drives Conf, 1994; pp. 313 318.

[Jo02] Jonah Zhou Chen; Ying Feng Pang; Boroyevich, D.; Scott, E. P. et al.: Electrical and thermal layout design considerations for integrated power electronics modules: Proc. 37th IAS Annual Meeting Industry Applications Conf. Conf. Record of the, 2002; pp. 242 246.


[Pa05] Pang, Y.: Assessment of Thermal Behavior and Development of Thermal Design Guidelines for Integrated Power Electronics Modules, 2005.

[Pa06] Pavlovsky, M.: Electronic DC Transformer with High Power Density, Delft, 2006.


4. Integration of LED-driver functions

4.1. Introduction

Chapters 2 and 3 have shown that LED-lighting systems require power electronic LED-drivers that are able to fulfil essential lighting functions: providing stable LED brightness levels over input voltage variations, creating a uniform brightness distribution among a variety of LEDs and maintaining dimming functionality with high colour stability. In addition, systems that are able to ensure lighting functionality after LED failures are preferable.

However, implementing LED-drivers on 3D-MIDs, which have highly limited routing possibilities, challenges the realisation of conventional complex LED-driver circuits. In this chapter, adapted LED-drivers will be developed to supply a multitude of high-power LEDs with a low number of driver components whilst external networks for dimming and brightness distribution are directly integrated to minimize complexity for a simplified 3D-MID realisation.

The chapter begins with a compact review of contemporary LED-drivers to determine whether those are able to maintain the required lighting functions for high-power LEDs and to derive, if they can be realised on 3D-MIDs in a simple manner (Section 4.2).

Results of the review are used in Section 4.3 to develop a novel principle of inductive brightness distribution which can be directly integrated into a variety of different power converter topologies which allows a simplified LED-driver realisation on 3D-MIDs. The modified topologies are furthermore able to cover a wide range of applications, containing non-isolated and isolated systems with step-up and step-down functionality.

In Section 4.4, the proposed brightness distribution technique of Section 4.3 is extended to compensate large LED tolerances and furthermore to improve the system’s performance at single LED failures whilst still maintaining low circuit complexity.

In a last step, the state of the art external dimming network is directly integrated in the power-converter to further decrease component count and trace numbers. Influences on LED colour stability, converter analysis and practical verification, using the proposed brightness distribution principle, will be shown in Section 4.5.

Section 4.6 finally gives a comparison of the developed LED-drivers to the conventional solutions in the light of a simple MID realisation and summarizes the brightness distribution performance of the developed topologies.

In this chapter, different prototypes are used to verify each step of integrating lighting functions as well as to validate the individual analyses made. This approach is performed, as the final prototype system (Chapter 7) will be realised with an adapted and compact layout to achieve a good electrical and thermal performance. Hence, not all signals required for verification will be measurable in the final prototype.

52 Chapter 4

The chapter is summarised in Section 4.7.

4.2. Survey of LED-drivers for application on 3D-MIDs

Chapter 2 has already shown that electronic circuits considered for a 3D-MID realisation are required to have a low component count and wiring complexity to obtain:

A simple circuit artwork creation and routing on 3D-MIDs

Low assembly efforts and production costs

Hence, LED-drivers are required that fulfil prior 3D-MID demands whilst still providing essential lighting functions. These are:

Creation of a uniform brightness distribution among a multitude of high-power LEDs

Control of LED brightness with stable chromaticity values

Compensation of single LED failures

It is further advantageous when the LED-driver operates with a homogeneous loss distribution among its components to allow a simplified thermal management implementation on 3D-MIDs.

The ability of conventional LED-drivers to drive LED-lighting systems, with the foregoing requirements, will be discussed in the following.

4.2.1. Series LED-structures

The simplest LED-driver is obtained by using a power converter that drives a single string of LEDs connected in series. This topology allows a simple LED brightness control by adjusting the current ILED flowing through the LED string. Therefore, LED failures with short-circuit can be directly regulated by changing the converter’s duty-cycle.

More sophisticated solutions achieve LED brightness control with PWM dimming by connecting external dimming networks with additional power switch and control IC to the LED string [NZ04], shown in Figure 4-1. PWM dimming allows a more precise brightness control at low duty cycles and increased colour stabilities over the entire dimming range when compared to linear brightness control.

Figure 4-1: dc-dc converter with single LED string and external PWM dimming

PWM-Dimming

Vin

DC

DCQ

ILEDVLED

LED-driver

Integration of LED-driver functions 53

The drawback of this solution, however, is that increased component count and wiring complexity are required for the external PWM dimming switch and its control, when compared to simple linear current dimming. This is unwanted in the case of a simplified 3D-MID realisation. Further limitations appear for this configuration when a large number of LEDs is connected in series, demanding high output voltages which may exceed allowed voltage levels (Chapter 2). In addition, already a single LED failure with open circuit causes the fault of the entire system.

Extended topologies have therefore been developed in research and industry to compensate LED failures, as shown in Figure 4-2 [De08]. Here, single switches are connected parallel to each LED to obtain increased robustness against LED failures. Furthermore, each LED brightness level can be controlled individually by pulse-width modulation due to the switch network. This, however, comes at the cost of greatly increased wiring effort and component count.

Figure 4-2: dc-dc converter with single LED string and individual LED control

4.2.2. Multiple power converters and converter-cells

The use of multiple power converters or converter cells is an alternative to single converter configurations to decrease unwanted high output voltages and to reduce the risk of complete system failure at a single open-circuit LED failure. Figure 4-3 shows two exemplary configurations with (a) parallel power converters and (b) a series input connection of power converter cells, as suggested by [PZ08].

Figure 4-3: (a) Paralleled dc-dc converters and (b) series connection of converter cells as LED-drivers

LEDx

Vin

DC

DC

PWM-dimming

LEDx

DC

DC

LEDx

DC

DC

LEDx

Vin

DC

DC

(a)

LEDxV1

LEDxV2

DC

DC

LEDxVi

Vin

DC

DC

DC

DC

(b)

Vin

Vin

54 Chapter 4

Both approaches, however, suffer from an increased number of components compared to single converter solutions, leading to increased wiring complexity, high component count and assembly challenges with 3D-MIDs.

4.2.3. Parallel LED-structures

Problem of paralleling LEDs

The use of parallel LED connections can reduce the issue of LED failures with open circuits and limits high output-voltages which are unwanted in several applications, like the conventional 14V automotive electrical power net. However, a simple parallel connection of LEDs (Figure 4-4) is typically not possible due to production-based tolerances regarding the LED forward voltages (Vi), which can cause big deviations in the resulting LED branch-currents.

Figure 4-4: dc-dc converter with parallel LED branches and external PWM dimming

Figure 4-5 shows this behaviour for two LEDs of the same type but with slightly different current-voltage characteristics. If we assume that LED 1 and LED 2 are connected in parallel and the voltage of V1 is applied to both LEDs, then LED currents I1 and I2 will have highly different magnitudes. The figure also shows that only a small difference between the LED forward voltages leads to these large current deviations and that LED 2 therefore requires only a small ΔV to achieve the same branch current I1 as LED 1.

Figure 4-5: Current-voltage characteristic of two similar LEDs

As the current level directly influences the LED brightness a simple parallel connection is no suitable option to obtain a homogenous light distribution.

Experimental determination of unbalanced LED-currents among parallel LEDs

The influence of forward voltage deviations on the current flowing through paralleled LEDs has been determined experimentally to quantify the significance of this effect for

PWM-DimmingVin

DC

DC

Q

V1 V2 Vi-2 Vi-1 Vi

I1 I2 Ii-2 Ii-1 Ii

V

I

LED 2

LED 1

V1

I1

I2

V2

ΔV


commercially available LEDs [TP09]. Two different types of high-power LEDs have been selected as light sources for reasons of comparison, LED-type 1: Osram Ostar LEDs [Os08] and LED-type 2: Cree XLamp MC-E LEDs without voltage binning [Cr08b].

In a first step, the LEDs’ forward voltages VLED have been measured to quantify the production tolerances among the test devices. All LEDs have been mounted on a common heat-sink to keep the LED temperature stable. The LEDs have been driven with a constant test current of ILED=400mA for t=300s to achieve stable LED junction temperatures and therefore comparable forward voltages. The resulting forward voltages are listed in Table 4-1.

Afterwards, the same LEDs have been connected in parallel and supplied by a constant input voltage. The resulting LED currents and the supply voltages are also summarised in Table 4-1.

Table 4-1: Measured LED-characteristics

LED-type

Operating conditionsTested LEDs

1 2 3 4 5 6 7 8

1VLED[V] at ILED=400mA 18.53 18.48 18.44 18.63 18.52 18.73 18.66 18.5

ILED[mA] at VLED=18.5V 366 430 406 317 380 309 310 399

2VLED[V] at ILED=400mA 11.52 13.05 12.71 11.61 12.44 11.91 11.98 11.62

ILED[mA] at VLED=11.5V 327 35 40 172 59 90 83 224

The deviations among the LED voltages ΔVLED and currents ΔILED of Table 4-1 are given in Figure 4-6 as percentile values for a better visibility. The relative deviations of the LED currents ΔILED are represented as pillars, whereas the voltage deviations ΔVLED are shown as numbers. The normalisation has been performed on the lowest voltage- and current values.

Figure 4-6: Forward voltage deviations of high-power LEDs with/without voltage-binning and resulting

current deviations in simple parallel LED-connections

It can be seen from the charts that small forward voltage deviations of only 2 percent, among LED-type 1, have lead to current deviations exceeding 30 percent. LEDs with higher forward voltage differences, like among LED-type 2 (ΔVLED =13%), show extremely unbalanced currents with a factor of nine between the branches.

0.5% 0.2% 0.0% 1.0% 0.4% 1.6% 1.2% 0.3%0%5%

10%15%20%25%30%35%40%45%

LED 1 LED 2 LED 3 LED 4 LED 5 LED 6 LED 7 LED 8

Cur

rent

-and

vol

tage

-dev

iatio

n

LED-type 1 (with voltage binning)

Delta_V_LED Delta_I_LED

0.0% 13.3% 10.3% 0.8% 8.0% 3.4% 4.0% 0.9%0%

100%200%300%400%500%600%700%800%900%

LED 1 LED 2 LED 3 LED 4 LED 5 LED 6 LED 7 LED 8

Cur

rent

-and

vol

tage

-dev

iatio

n

LED-type 2 (without voltage binning)

Delta_V_LED Delta_I_LEDΔVLED ΔILED ΔVLED ΔILED

56 Chapter 4

Principle of current balancing networks

To overcome limitations in paralleling LEDs different, so-called, current balancing networks have been developed and published in the literature [MM05],[BZ04],[DZ07].

The basic idea of current balancing is to add additional active or passive networks into each parallel LED branch that weaken or even completely compensate the influence of forward voltage deviations on the branch current. A principle illustration is given in Figure 4-7.Advanced networks are further used to increase the availability of the total LED-lighting system after LED failures.

Figure 4-7: Basic idea of current balancing

The suitability of existing current balancing networks for driving high-power LEDs on 3D-MIDs will be discussed in the following.

Resistor approach

The easiest way to achieve current balancing of paralleled LEDs is obtained by adding a series resistor in each branch (Figure 4-8). The voltage drops VRx across the balancing resistors Rbx have to be much larger than the forward voltage difference of the parallel connected LEDs to significantly reduce the current deviations ΔILED, as can be concluded from the data presented in [MM05].

Figure 4-8: Current balancing principle with resistors

A result of this principle, however, is that high power losses will appear in the resistor network when high-power LEDs are planned to be used. For example, if an automotive daytime running light is assumed, with specifications given in Table 4-2, losses of Ploss=8Wwould appear in each balancing resistor Rbx for the allowed branch current deviations. The branch losses are therefore nearly as high as the LED power consumption per branch.

Vin

DC

DC

Currentbalancing

Currentbalancing

Currentbalancing

Currentbalancing

I I I I

Vin

DC

DC

I I I I

Rb1 Rb2 Rb3 Rb4VR1 VR2 VR3 VR4


Table 4-2: Example system for current balancing calculations

Numberof LEDs

LED branches

LED current

Total LED power

Allowedcurrent deviation

Assumed forward voltage deviations

20 2 350mA 20 ±5% 5%

In general, the enormous losses of this technique make it to no suitable option for achieving a homogeneous brightness distribution among high-power LEDs.

Capacitor approach

Figure 4-9 shows another technique for current balancing which has been presented in [BZ04]. The system works similarly to the foregoing resistor based current balancing technique.

Here, balancing capacitors are connected in series to the LED branches and the system is supplied with a sinusoidal supply voltage. If the resulting voltage drops across the capacitors Cx dominate over the LED voltage differences, then current deviations can be reduced. In contrast to the resistor approach, current balancing losses are greatly reduced.

Figure 4-9: Current balancing principle with capacitors and sinusoidal voltage waveforms

A drawback of this solution is that sinusoidal current waveforms have to be generated in the converter, e.g. with complex resonant power converter topologies. In order to achieve a bidirectional current flow an anti-parallel connection of the LEDs is required in each LED branch and therefore, only half of the LEDs are permanently active. In addition, high-power LEDs are not designed for reversed operation [Os08], [Ph07a] and additional diodes would be required in each LED path. Further, the LEDs’ optical efficacy is reduced when operated with these waveforms [Sa06], [Sc07].

The system is therefore no suitable option for achieving a homogeneous brightness distribution when high luminous fluxes are required. As a result the system is not considered for application.

Active control

Not only passive techniques are used for current balancing, but also active ones. Figure 4-10shows an active current balancing principle with current sources, e.g. MOSFETs that are connected in series to each LED branch as introduced in [DZ07], [DZ08]. The active sources allow current adjustments between the parallel branches by controlling the voltage drop across themselves. In this case, the minimum voltage drop is given by the maximum voltage difference ΔVLED between the LED branches.

Vin

AC

DC VC1

I I I I

VC2 VC3 VC4

Vout

58 Chapter 4

In comparison to the foregoing passive techniques, additional current-sensing networks are required to measure the individual branch currents. Further, a control unit has to adjust the individual voltage drops to equalize the branch currents.

Figure 4-10: Current balancing with active control and bi-directional feedback to power converter

When using this topology in an LED-lighting system with variable input voltage, e.g. the automotive environment, a power converter is required to compensate input voltage variations. As a consequence, a bidirectional communication between the control of the linear current sources and the control loop of the power converter is required to reduce the converter output voltage and hence, to decrease the voltage drop across the MOSFETs to a minimum. This leads to a reduction of the power losses in the active sources and makes the system more suitable for driving high-power LEDs. However, the system’s complexity will be considerably increased when compared to the passive techniques.

A simplified estimation of the losses in the current balancing network will be given in the following by only considering losses generated due to the compensation of the forward voltages.

When the control of the power converter and the active sources get linked, the losses in each active source can then be calculated with: Ploss_x=ΔVLED •ILED. If the automotive daytime running light given in Table 4-2 is assumed, current balancing losses of Ploss_x=0.5W have been calculated for each branch. When a larger number of LEDs has to be paralleled, the total losses in the current balancing network will further increase. This complicates a solution where the balancing network and the control of the required power converter are realised in one integrated circuit because thermal issues arise. Hence, external current sources get required and component count increases. In addition, single LED failures with short circuit will significantly increase the losses in the current balancing components and will challenge the implementation of the thermal management, especially on 3D-MIDs that show limited heat spreading performances (Chapter 6).

The necessity of active components and active branch control with individual current sensing leads to an increased wiring complexity as well as to increased assembly efforts. A simple realisation on single layer 3D-MIDs is therefore very challenging.

Vin

DC

DC

Current balancing

control

I1

A1

VLED1

IrefI2

A2

VLED2

IrefI3

A3

VLED3

IrefI4

A4

VLED4

Iref


4.2.4. Summary

Table 4-3 summarizes characteristic parameters of the investigated state of the art LED-driver topologies and further shows how much active components are required to fulfil the desired lighting functions. Finally, key limitations are given that will restrict a 3D-MID realisation.

Table 4-3: Summary of available LED-driver principles for driving a multitude of LEDs

Power converter *) with serial LEDs

Power converter with parallel LEDs and current balancing

Single converter

Multiple converter (-cells)

Resistorapproach

Capacitorapproach

Active control

No. of switching cells 1 ncell 1 1 1

No. of active switches 1 ncell 1 1 nbranch + 1

PWM dimming with topology

possible?√ √ √ O √

PWM dimming directly with

topology possible? **)

O O O O √

Suitability for high-power LEDs √ √ O O √

Output voltage

No. of permanent active LEDs

Routing complexity ++ + ++ - --

Dominating limitation for

target application

Output voltage

No. of components Power losses Light output Wiring

complexity

√=yes, O=no *) For reasons of simplicity a single switch boost converter is assumed as power converter topology

**) Directly means that no additional external switching networks are required to obtain PWM-dimming

It can be seen from the table that simple series LED connections suffer from unwanted high output voltages and complete system failure at open circuit LED breakdown. Splitting the series structure in multiple converters (-cells) unfortunately increases the component number and the routing effort.

The comparison also shows that existing LED-drivers with paralleled LEDs and passive current balancing networks are no suitable options for systems with high-power LEDs. The

60 Chapter 4

implementation of active sources, however, can be designed for a brightness control with high LED power. This approach, however, requires a bidirectional communication between the power converter and the current balancing network, which increases routing complexity and component count unwanted on 3D-MIDs.

Furthermore, all prior concepts do not combine the power converter — e.g. necessary in automotive LED-lighting — with the current balancing network and consider them as two separate domains. As a consequence, a simplified current balancing network for high-power LEDs is missing. The ability to also integrate the dimming feature directly in the power converter topology will be explained in Section 4.5.

The most suitable approach would be the availability of a passive and (quasi-) lossless network which is easy to implement on 3D-MID-based LED-lighting systems. In addition, it would be convenient to combine the inevitable power converter and the current balancing network. Here, one optimised LED-driver could be formed that allows the drive of a large number of high-power LEDs with a homogeneous brightness distribution at reduced wiring effort.

4.3. Development of inductive current balancing technique for high-power LEDs

A new concept of passive current balancing which tries to satisfy the preceding requirements regarding simple LED-driver realisation on 3D-MIDs will be introduced in the following sections [TP09], [TP09b]. In comparison to the prior capacitor and resistor technique, the proposed principle uses an inductive approach for supplying the high-power LEDs with high luminous efficacy and reduced wiring complexity.

4.3.1. Basic idea and operation principle

The general idea behind the inductive current balancing approach is to link the current balancing performance to the relatively small forward voltage deviations that appear among voltage-binned LEDs [TP09], as has been introduced in Table 4-1.

A single-switch buck converter is used as an example to describe the basic operation of the proposed current balancing principle. The topology is shown in Figure 4-11. Each LED branch is connected in series to its own filter inductor Lx and the converter is operated in discontinuous conduction mode (DCM). The DCM is used to minimize the influence of the forward voltage deviations on the LED currents, as shown with the inductor current waveforms, also given in Figure 4-11.


Figure 4-11: Buck converter with inductor current balancing and resulting LED currents (without filter capacitor)

Because of DCM, the forward voltage differences ΔVLED among the LEDs will only influence the maximum achievable peak current value ΔIx and the free-wheeling time D2•Ts. Operating in continuous conduction mode (CCM) would have a significantly higher influence on the average LED currents because the minimum current values would also be influenced by the LED forward voltage differences.

The resulting current deviation ΔIrel among the LED branches will be analysed in the following for the proposed single-switch multi-inductor buck converter depending on the voltage deviations ΔVLED of the LEDs in the different branches. It has to be noted that connecting capacitors parallel to the LEDs in each branch – indicated with dashed lines in Figure 4-11– can be used to obtain dc LED-currents.

The following assumptions are made in the analysis

A converter with two LED branches is used

The LED strings are modelled as ideal voltage sources: #1: VLED and #2: VLED+ΔVLED

The dependency of the LED forward voltage from the LED current is neglected for reasons of simplicity

The duty-cycle D1 is adjusted to achieve boundary of DCM for LED string 1

Ideal inductors, capacitors and switching devices are assumed: conduction and switching losses are therefore neglected

The branch inductances are equal: L1 = L2 = L

The waveforms of Figure 4-11 show, that an increase in the LED forward voltage by ΔVLED

decreases the peak inductor current which is achieved when switch Q is conducting. At turn-off, the required free-wheeling time D2•Ts in branch 2 is also reduced by the voltage difference ΔVLED. Hence, the average current value in string 2 is also influenced by ΔVLED.

The duty-cycle D1 of the buck-converter is obtained from the assumption of boundary of discontinuous conduction mode of operation:

I

t

LVV

dtdi LEDin11

LVVV

dtdi LEDLEDin )(12

LV

dtdi LED21

LVV

dtdi LEDLED )(22

D1·Ts D2·Ts D3·Ts

ΔI1ΔI2

Vin D

Q L1

D1

L2

D2

62 Chapter 4

Where Vin is the input voltage and VLED is the forward voltage of the LEDs connected in branch 1. At the end of mode 1 with switch Q is conducting, the current flowing through inductor L1 reaches its maximum value ΔI1:

As branch 1 is operated at the boundary of DCM, the average LED current of branch 1 is obtained directly from (4.3.2):

For branch 2, the peak inductor current ΔI2 can be calculated from:

With ΔVLED is the forward voltage difference between the LEDs in branch 1 and branch 2. The free-wheeling time ΔT22=D2•Ts of branch 2 can be expressed by:

Integrating the time-dependent inductor current of branch 2 gives an expression for the averaged LED current in branch 2:

With the assumption of ideal lossless converter operation it can be obtained as:

The relative current deviation ΔIrel between the two branches can now be defined as:

Including (4.3.1), (4.3.4) and (4.3.5) into (4.3.7), subtracting the average current from branch 1 and normalization gives:

With ΔVLED << VLED (4.3.9) can be simplified and a linear relationship between ΔVLED and ΔIrel is obtained, as shown in (4.3.10):

It can be seen from the equation that the current balancing performance is not only influenced by the forward voltage deviation, but also from the input and LED-voltage. A further interpretation and visualization of the current balancing behaviour of the buck-converter will be given in the following section.


4.3.2. Parallel input-structures

Current balancing performance

The buck converter in Figure 4-11 is the simplest solution for integrating the inductor current balancing technique into a converter topology, as it is able to work with a minimum number of components. However, the principle can be applied to several power converter topologies and voltage conversion ratios.

Current balancing analyses similar to the prior buck-topology have been performed for boost- and buck-boost converter topologies, to compare the current balancing performance of the three basic non-isolated dc-dc converters. The voltage conversion ratio available with the boost- as well as the buck-boost- topologies are especially suitable for automotive applications operated directly from the conventional 14V automotive electrical power net, with input voltages level that can vary between 8V and 17V.

Figure 4-12 shows single switch buck- (a), boost- (b) as well as buck-boost (c) converters which have been modified with the proposed integrated current balancing technique. The latter two require additional diodes D1 and D2 for branch separation in single switch topologies. However, D1 and D2 could be replaced by using individual switches in each branch, e.g. with an IC that integrates multi-switches. Hence, diodes D1 and D2 could get obsolete which contributes to reduced losses within the converters.

Figure 4-12: Investigated inductor current balancing topologies: (a) buck-, (b) boost- and (c) buck-boost converter

Figure 4-13 shows the results of the current balancing analyses for (a) the buck, (b) the boost and (c) the buck-boost converter. In the figures, the relative deviations of the average LED currents ΔIrel have been calculated in dependency of the LED forward voltage deviation ΔVLED, according to (4.3.8). All calculations have been performed for systems with two parallel LED branches.

The forward voltage deviation ΔVLED has been varied between 1 and 5 percent in the calculations. These values correspond to the difference between binning classes of typical white high-power LEDs and have also been observed in practical measurements, as presented in Figure 4-6.

(a)

Vin D

Q L1

D1

L2

D2

Vin

Q

L1

D1

L2

D2

D3

D4

(b)

Vin

Q

L1

D1

D3

D2

L2

D4

(c)

64 Chapter 4

Figure 4-13: Calculated average current deviations between two parallel LED-branches for the (a) buck-,

(b) boost- and (c) buck-boost converter topology

The charts show that in all three converter topologies the average LED current deviation is approximately linearly dependent on the voltage deviation ΔVLED, as expected. However, the results also indicate that a variation of the input voltage Vin influences the current deviations in the buck- and boost- topology. The buck converter (Figure 4-13 (a)) reaches maximum values of ΔIrel≈10 percent at ΔVLED=5 percent when the input voltage is twice the LED voltage Vin=2VLED. Increasing Vin leads to reduced current differences. A high input voltage is, therefore, required for the buck converter to achieve an optimised current balancing behaviour and driving branches with several serial connected LEDs directly from the automotive power net would require an additional boost stage for the buck converter approach.

The boost topology is able to provide the required high LED voltages itself, but requires additional efforts for branch separation (Figure 4-13 (b)). Comparing the current balancing performance between the buck and the boost converter shows that the boost converter performs slightly better. A maximum average current deviation of 9.1 percent is achieved for the boost converter at ΔVLED=5 percent. The buck converter achieves 9.5 percent with the same LED forward voltage and the same voltage stress across the switching devices.

Figure 4-13 (c) shows results of the buck-boost converter topology. The relationship between ΔVLED and ΔILED is approximately linear as in the case of the buck- and boost- converter, but independent of Vin. This makes the topology especially attractive for automotive LED-lighting with variable input voltage ranges, and will therefore be used in Section 4.3.5 to verify the inductive current balancing technique with a prototype system.

Equal power operation

The buck-boost topology does not only improve current balancing among paralleled LEDs, but furthermore leads to an equal power LED operation. The reason for this is that the energy stored in each inductor branch is dependent on the peak inductor current, which is defined by

ΔVLED ΔVLED ΔVLED

ΔIre

l

ΔIre

l

ΔIre

lVin= 2 ·VLED

Vin= 4 ·VLED

Vin= 1.5 ·VLED

Vin= VLED/2Vin= VLED/4

Vin= VLED/1.5

(a) (c)


Vin= VLED/1.5

(b)


the input voltage, the inductor value and the converter’s duty-cycle as shown with the inductor waveforms in Figure 4-14. This energy is completely transferred to the LEDs atswitch Q turned off.

Figure 4-14: Buck-boost converter inductor currents

An analysis has been performed to calculate the energy transferred to the LEDs dependent on the input voltage and the duty-cycle. The energy stored in the inductor can be expressed by:

The maximum inductor current ΔI is dependent on the input voltage Vin, the duty-cycle D1 and the branch inductance L:

Including equation (4.3.12) into (4.3.11) leads to the energy stored in the inductors, when the switch Q turns off:

It can be seen from equation (4.3.13), that an equal power operation of the LEDs is achieved if identical inductor values L are assumed. The power deviation for the buck- and the boost-converter has been calculated analogous to the current deviations and is shown in Figure 4-15.

Figure 4-15: Calculated average power deviations between two parallel LED-branches for the (a) buck-,(b) boost- and (c) buck-boost converter topology

I

t

LV

dtdi

dtdi in1211

LV

dtdi LED21

LVV

dtdi LEDLED )(22


ΔI


Vin= VLED/1.5Vin= VLED/2Vin= VLED/4

Vin= VLED/1.5Vin= 2 ·VLED

Vin= 4 ·VLED

Vin= 1.5 ·VLED

ΔVLED ΔVLED ΔVLED

(a) (b) (c)

ΔPre

l

ΔPre

l

ΔPre

l

66 Chapter 4

It can be seen from the charts that the buck-boost converter operates at equal power as expected.

The brightness distribution quality of the equal power operation instead of the conventional constant current drive will be compared in Section 4.3.4.

4.3.3. Series input-structures

The foregoing technique of inductive current balancing and equal power operation can also be applied to series connections of coupled inductors. The principle’s field of operation can therefore be extended from low voltage dc applications to LED-lighting systems with high input voltages, e.g. when directly connected to the 230 VAC mains supply, or when a galvanic isolation is required in general between the input at the primary side and the secondary side, where the LEDs are connected. This can be beneficial for applications with the LEDs mounted on one side of the device and the power-electronics attached to the opposite side, like the double sided spatial configuration in Chapter 3. The galvanic isolation could be used for the power transfer through the circuit carrier, avoiding vias in the 3D-MID.

A topology with galvanic isolation which behaves comparable to the prior introduced buck-boost converter is the flyback converter topology. Figure 4-16 (a) shows a basic flyback structure which has been modified by a series connection of n-transformers L1 to Ln to supply a multitude of LED branches. Optional filter capacitors are used in parallel to the LEDs to achieve approximately dc LED currents for the best optical efficacy of the LEDs [Sa06].

The converter’s performance in equal power mode of operation with DCM and equal current mode of operation with CCM will be shortly discussed, in the following [TP10a], [TP10b].

Equal power operation

The analysis of the flyback’s DCM equal power operation is very similar to the analysis obtained for the buck-boost converter (Section 4.3.2). The following assumptions are made, additionally:

Ideal transformers, capacitors and switching devices have been assumed.

The transformer leakage inductances have been neglected and equal magnetizing inductances L1=L2=...=Ln=L are used.

The principle current waveforms of a topology with two parallel LED branches and operating in DCM are shown in Figure 4-16 (b). Here, the converter’s duty-cycle has been adjusted to achieve boundary of discontinuous conduction mode for LED string 1, which has the lower forward voltage VLED.

When the switch Q is turned-on, the current IL_px in the primary windings of each transformer will rise to the maximum value ΔI.


Figure 4-16: (a) Principle circuit diagram of flyback topology with n isolated LED branches (b) principle current waveforms of an ideal topology with 2 parallel LED branches

At switch Q turn-off, the peak current ΔI in the secondary windings will decrease with a negative slope, which is defined by the LED forward voltages and the inductance value L,until it reaches zero. As a consequence of the equal transformer magnetizing inductances, the voltages across the inductors are equal, as well:

, where n is the number of transformers connected in series.

With the assumption of boundary of DCM in branch 1, the energy stored in the transformer at switch Q turned off, can now be directly calculated from the buck-boost converter analysis by inserting (4.3.12) in (4.3.11), where VL is used instead of Vin, as defined in (4.3.14):

With the assumption of ideal transformers and discontinuous inductor currents, again an equal power LED operation is achieved. Further, the current balancing performance of the DCM flyback is also identical to the buck-boost converter, considering that VL equates to Vin.

Equal current operation

In contrast to the foregoing topologies, the flyback converter can also be operated in CCM, to achieve an equal current instead of an equal power operation of the parallel LED strings. CCM is obtained by increasing the magnetizing inductance of the transformers. The resulting current ripple decreases and becomes smaller than twice the average inductor currents. Figure 4-17 (a) shows the principle winding currents of a topology with two LED branches.

(a) (b)

Vin

Q

V1

V2

Vn

iLL1

L2

Ln

ILp_x

t

LV

dtdi 111

LV

dtdi 212

LV

dtdi LED21

LVV

dtdi LEDLED )(22


ΔI

ILs_x

tD1·Ts D2·Ts D3·Ts

ΔI

68 Chapter 4

Figure 4-17: (a) Principle current waveforms of an ideal topology with 2 parallel LED branches without leakage inductances and (b) modes of operation in CCM

It can be seen from the figure that there are three modes of operation obtained in CCM. The forward voltage difference ΔVLED causes different current slopes when the switch Q is turned-off. Hence, different current values are obtained at switch Q turn-on and mode 1, which is an additional current balancing mode, is obtained. The equivalent circuit diagrams of the three modes are shown Figure 4-17 (b).

When switch Q is turned on at the beginning of mode 1, the inductor with the smallest inductor current (L2) determines the current in the input circuit. The output diode of this particular branch is therefore not conducting in this mode. The difference between the individual inductor currents and the input current, however, leads to a current flow in the output diode of the other branch and forces the LED voltage across its inductor (L1). Hence, the voltage across inductor L2 is increased, leading to a high di/dt of the input current, and equalizing rapidly the different inductor currents. The duration of mode 1 is very short. The time D1•Ts shown in Figure 4-17 is only enlarged for a better visibility.

A further analysis has been performed to calculate the deviations between the LED currents of branches 1 and 2 dependent on the operating conditions of the converter. The influence of mode 1 is very small and its duration is therefore assumed to approach zero D1 ≈ 0 in the analysis presented. The deviation between the LED currents is defined as follows from the waveforms given in Figure 4-17:

where,

with:

and

Mode 2: Q= on

L2

Vin

+

-

L1

Mode 1: Q= onD1=„on“

L2

Vin+

-

L1 V LED

+

-

Mode 3: Q= off

L1 V LED

+

-

L2

V LED

+ΔV

LED

+

-

V in+

V LED

ILp_x

t

LV

dti LED21

LVV

dti LEDLED )(22

ΔI

ILs_x

t

ΔI

ILED

D2·Ts D3·TsD1·Ts

LV

LV

dti 21

D2·Ts D3·TsD1·Ts

(a) (b)


and with

The duty-cycle is defined by the LED voltage VLED and half of the input voltage Vin:

and D3 ≈ 1 - D2. Using the input current ripple during mode 2,

, the following general solution can be obtained for the relative LED current deviation between n LED branches:

It can be seen from (4.3.23) that the current balancing performance of the flyback converter is dependent on the forward voltage deviation ΔVLED as well as on the resultant current ripple Δi,which is defined by the size of the magnetizing inductance L.

In a practical design, the use of several in series connected transformers leads to an increase of transformer leakage inductances, which can cause high overvoltages at turn-off of the active power switch. This effect has to be compensated to decrease the voltage stress of the switch. Different solutions exist to deal with this issue, e.g. the introduction of resonant switching to use the leakage inductances for soft-switching or to introduce active or passive clamping networks to recycle the transformer leakage energy back to the input, so that no high overvoltages appear at switch turn-off e.g. presented in [YIN92], [WLH961], [LSL97], [Zh].

A two-switch flyback converter, as presented by [XB0812], has been investigated for the suitability of the proposed inductive current balancing principle. The topology recycles the transformer leakage energy by a passive clamping network to the input. Furthermore, the influence of transformer magnetizing- and leakage- inductances Ls on the achievable power transfer and methods to improve the power-transfer for given values of Ls have been investigated. The results have been published in [TP10a], [TP10b] and account the topology a good current balancing performance, even at increased leakage inductances.

4.3.4. Comparison of equal power and equal current LED operation

Chapters 4.3.2 and 4.3.3 have shown that the buck-boost and flyback converter topologies can be used to achieve an equal-power operation of the LEDs when operated in DCM. In this section a comparison will be performed between the state of the art equal-current and the proposed equal-power operation of LEDs. This is done to determine if the simplified equal power operation – available with the buck-boost and flyback topologies – can be used to

70 Chapter 4

obtain a sufficiently good brightness distribution among the LEDs when compared to the conventional constant current drive.

The measurements have been carried out with LED-type 2 [Cr08]. For the following measurements, all 4 LED chips in one package have been connected in series. To get representative data, three different production lots of LEDs have been used for these investigations.

In a first step, the forward voltages of the LEDs have been measured at a constant LED current of ILED=350mA. Table 4-4 shows the resulting forward voltages of six randomly selected LEDs from the three production lots and the correspondent brightness binning groups.

Table 4-4: Forward voltages of MC-E LEDs picked from three different production lots

Brightness binning group

Forward voltages VLED [V] at test current of ILED=350mA

1 2 3 4 5 6

Lot 1 KLED 111.15

LED 212.54

LED 312.25

LED 411.20

LED 512.00

LED 612.10

Lot 2 MLED 711.76

LED 812.19

LED 911.94

LED 1011.66

LED 1111.78

LED 1212.62

Lot 3 MLED 13

12.08LED 14

11.67LED 15

11.91LED 16

11.93LED 17

11.70LED 18

11.59

Voltage deviations of up to 12.5 percent have been determined between the LEDs of lot 1 and up to 8.8 percent between the LEDs of lot 2 and lot 3. When operated with constant-current,the electrical input power of the LEDs will be determined by the LED forward voltage.

In a second step, the luminous fluxes of the LEDs have been measured for the equal-current and for the equal-power operation of the LEDs. The optical measurements have been performed in an integrating sphere connected to a CCD-spectrometer and at constant junction temperatures to ensure comparable data. Therefore, the LEDs have been mounted on a heat sink unit with peltier-elements which kept the heat sink temperature stable. The LEDs have been driven with constant-current or constant-power for 300 seconds, to achieve stable LED junction temperatures. Due to a good thermal coupling of the LEDs with the cooling unit, the influence of the power deviations caused by the constant-current drive on the LED junction temperatures has been very small and could be calculated to be less than ΔT=1.5°C. The resulting deviation in the luminous flux is therefore below 0.5 percent and has been neglected.

Figure 4-18 shows the influence of the constant-current drive on the luminous flux of the 18 LEDs defined in Table 4-4.


Figure 4-18: Luminous flux of Cree MC-E LEDs from three production lots under equal-current operation: ILED=350mA

The LEDs have been driven with an LED current of ILED=350mA. The chart shows the relative luminous flux of the LEDs (bright pillars) and the corresponding power in the LEDs (dark pillars). The luminous fluxes have been normalized for a better visualisation. For this reason, the luminous flux of production lot 1 has been normalized on the highest luminous flux appearing in this production lot (LED 3). As the LEDs of lot 2 and 3 belong to the same brightness binning-group, the normalization has been performed on the highest flux appearing in lot 2 and 3 (LED 13).

The constant-current operation leads to a maximum deviation of 8.5 percent between the luminous fluxes of the LEDs of lot 1, and to the expected maximum power deviation of 12.5 percent caused by their forward voltage differences. A comparison of the luminous fluxes between the LEDs of lots 2 and 3 shows a maximum difference of 9 percent, with power deviations of 8.8 percent.

The measurements of the constant-power drive have been performed with an input power of PLED=4W. Figure 4-19 shows the resulting influence of the constant-power operation on the luminous flux of the same LEDs.

Figure 4-19: Luminous flux of Cree MC-E LEDs from three production lots under equal-power operation: PLED=4W

The normalization of the luminous fluxes has been performed in the same way as for Figure 4-18. The second y-axis shows the resulting LED currents due to the equal-power operation.

3.0

3.5

4.0

4.5

5.0

5.5

6.0

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Pow

er in

W

Rel

ativ

e lu

min

ous

flux

relative luminous flux Power

Lot 1 Lot 2 Lot 3

250

270

290

310

330

350

370

390

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Cur

rent

in m

A

Rel

ativ

e lu

min

ous

flux

relative luminous flux Current

Lot 1 Lot 2 Lot 3

72 Chapter 4

The measurements show, that the constant-power approach achieves a slightly more uniform brightness distribution between the LEDs, compared with the constant current operation. The maximum deviation of the luminous flux is 6.7 percent for lot 1 and 8 percent for lot 2 and 3.

It can be summarised, that the equal-power operation of the investigated white high-brightness LEDs shows a comparable or a slightly better performance in terms of brightness homogeneity than the common approach of constant current LED drive. Both drive methods are available with the proposed inductive brightness distribution technique and will be experimentally verified in the following.

4.3.5. Experimental verification

Different experiments have been performed to verify theoretical results derived for the proposed brightness distribution principle. A buck-boost LED-driver prototype with six parallel LED branches is used here to demonstrate the current balancing performance of the proposed inductive current balancing approach among different high-power LEDs and to show its performance in equal power LED-operation.

Prototype using the proposed inductor current balancing approach

The prototype’s principle schematic is shown in Figure 4-20. It consists of the modified buck-boost topology with six parallel LED branches and integrated inductive current balancing network. The prototype has been designed to achieve the required target specifications of an automotive head-light system. The system will subsequently be called Prototype 1.

Figure 4-20: Prototype 1: Buck-Boost Topology with six parallel LED branches and inductor current balancing

The system is operated from the 14V automotive electrical power net. By adjusting the converter’s switching frequency between 300 and 500 kHz, stable LED currents can be achieved over the whole automotive input voltage range (Vin=8-17V). The LED power consumption is approximately PLED=45W if six Ostar LEDs [Os08] are operated at a drive current of ILED=400mA. Table 4-5 shows the capacitor and inductor values obtained for the given automotive target specifications and implemented in Prototype 1.

Vin

Cin

Q

L1

D1

D3

L2

D2

D4

L6

D6

D12LED-package LED-package LED-package

Branch 1 Branch 2 Branch 6


Table 4-5: Prototype 1 component values

Branch inductances: L1-L6

[μH]Branch capacitances: C1-C6

[μF]Input capacitance Cin

[μF]

6.1 2.2 22

The operation of the converter in DCM further contributes to low inductance sizes, as the minimum energy is stored in the inductor in this operation mode. The branch inductances L1

to L6 have been realised with smallest standard planar cores (EILP 14/3.5/5) with a concentrated air gap. Maximum inductor tolerances of < 2 percent have been achieved with this setup. The influence of the tolerances in the magnetic core material on the inductance values, and hence on the current balancing performance of the converter is calculated in Appendix A.

Schottky diodes SB160 have been used as free-wheeling diodes and are connected in series to the inductors to separate the 6 branches from each other. Filter capacitors C1 to C6 have been connected in parallel to the high-power LEDs. The LED currents are therefore approximately dc and the best luminous efficacy is achieved. The converter has been built and tested with the two LED types of Section 4.2.3, to prove the prototype’s current balancing capability and to verify the results of the analyses (Section 4.3.2).

Verification of prototype’s current balancing principle

Figure 4-21 shows the measured switch voltage and the inductor currents of LED branches 1 to 3 and of LED branches 4 to 6 of Prototype 1 when operating with LED-type 2.

Figure 4-21: Ch1: Switch-voltage (50V/div), Ch2-Ch4: Inductor currents 1-3 (a.) and 4-6 (b.) (2A/div), time scale 500ns/div

It can be seen from the waveforms that the converter operates with discontinuous inductor currents in all branches and that the inductor currents are approximately the same. Hence, the average LED currents are nearly identical, as well.

Figure 4-22 presents a comparison of the average LED currents obtained from the prototype operated with both LED types. For reasons of comparison, the figure also shows the currents obtained from the measurements of the LEDs when operated directly in parallel without current balancing techniques.

74 Chapter 4

Figure 4-22: Comparison of average LED currents of Prototype 1 to system without current balancing:(a) LED-type 1 (b) LED-type 2

Deviations of only 1.7 to 4.7 percent between the branches appear with the proposed current balancing technique for LED-type 1 (Figure 4-22 (a)). Without current balancing technique, when operated directly in parallel, deviations over 30 percent have been observed. Figure 4-22 (b) shows the results obtained from the measurements for LED-type 2 without voltage binning. Current differences of factor 10 without current balancing are reduced to deviations of 1.8 to 13 percent with the proposed technique.

The current balancing performance has also been measured over the converter’s duty cycle for reasons of comparison. Figure 4-23 shows the measured 6 LED currents for both LED types. In addition to the LED currents, the maximum current deviation (ΔILED_max) between the LED branches is plotted against the second y-axis of the charts. The figure shows that the highest current deviation ΔILED_max is below 5 percent during DCM when driving LED-type 1 (Figure 4-23 (a)). As soon as the desired operating area is left and CCM is reached (D>0.67) high current deviations, comparable to the results in Table 4-1, will appear.

When operating LED-type 2 with the prototype LED-driver (Figure 4-23 (b)), the maximum current deviation (ΔILED_max) is about 13 percent during DCM. This is caused by the LEDs’ forward voltage deviations of up to 13 percent, as these are only grouped by colour and without voltage binning. Operating with continuous current at D>0.59 causes high current deviations, as expected.

Figure 4-23: Current balancing of Prototype 1 over duty-cycle for LED-types 1 and 2: (a), (b)

050

100150200250300350400450500

LED 1 LED 2 LED 3 LED 4 LED 5 LED 6Aver

age

LE

D c

urre

nt[m

A]

(b) LED-type 2: MC-E

without current sharing with current sharing

050

100150200250300350400450500

LED 1 LED 2 LED 3 LED 4 LED 5 LED 6Aver

age

LE

D c

urre

nt[m

A]

(a) LED-type 1: Ostar

without current sharing with current sharing

0%

10%

20%

30%

40%

50%

60%

0

100

200

300

400

500

600

700

0 0.2 0.4 0.6 0.8

ΔI L

ED

_max

Aver

age

LE

D C

urre

nt[m

A]

Duty cycle D

I_LED_1I_LED_2I_LED_3I_LED_4I_LED_5I_LED_6Δ_I_LED_max

DCM

(a) LED-type 1

CCM

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

0

100

200

300

400

500

600

700

0 0.2 0.4 0.6 0.8

ΔI L

ED

_max

Aver

age

LE

D C

urre

nt[m

A]

Duty cycle D

I_LED_1I_LED_2I_LED_3I_LED_4I_LED_5I_LED_6Δ_I_LED_max

DCM

(b) LED-type 2

CCM

ΔILED_max ΔILED_max


Verification of prototype’s equal power principle

Finally, measurements have been performed to verify the prototype’s equal-power operation. Figure 4-24 shows the results of these measurements where the power of LED 1 and LED 2 (Table 4-4), which showed the largest deviations in their forward voltages (ΔVLED=12.5 percent), has been plotted at different converter duty-cycles for the nominal input voltage.

Figure 4-24: Power in LED 1 and LED 2 over duty-cycle and resulting maximum power-deviation ΔPLED_max

The second y-axis shows the power differences (ΔPLED_max) between the two LEDs. Only small deviations of up to 2 percent appear for DCM operation, which are mainly caused by the tolerances of the branch inductors Lx. When the desired operating area of discontinuous conduction mode is left (D>0.59), high power deviations appear, as expected. Due to the equal-power supply of the LEDs at DCM, the prototype achieves approximately equal luminous fluxes of the LEDs, comparable to those presented in Figure 4-19.

Similar tests have been performed with flyback converter prototypes, and show current balancing behaviours which are in close correlation with the results obtained from Prototype 1. The results are presented in [TP10a], [TP10b].

It can be summarised, that the inductive brightness distribution technique is able to provide current balancing as well as equal-power operation. This can be used for driving parallel LED-networks with a multitude of LEDs at low circuit complexity given by the developed modified buck-boost and flyback topologies.

4.4. Compensation of increased LED-tolerances and of LED failures

In the foregoing section inductive brightness distribution networks for high-power LEDs have been developed. The topologies are able to provide current balancing or power sharing

0%5%10%15%20%25%30%35%40%45%50%55%

0

1

2

3

4

5

6

7

8

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

ΔP L

ED

_max

LED

Pow

er [W

]

Duty cycle D

P_LED_1

P_LED_2

Δ_P_LED_max

DCM CCM

ΔPLED_max

76 Chapter 4

dependent on the chosen topology and operational mode and allow the compensation of typical LED-forward voltage deviations.

However, current balancing at further increased forward voltage deviations ΔVLED could still be further improved, e.g. when LEDs are used without any voltage binning or when short-circuit LED failures appear. Furthermore, the developed topologies for inductive current balancing benefit from precise inductance values with low tolerances to obtain an optimum in brightness distribution, as exemplary shown in Appendix A and in [TP10a], [TP10b] for the flyback topology.

In the following, a coupled inductor approach will be applied to the inductive current balancing technique to overcome these limitations. The principle can be applied to LED-systems with n-branches by utilising coupled inductors with n-windings. Nevertheless, a two-branch system will be used in this section for reasons of simplicity and due to its high relevance for the final prototype implementation in this thesis (Chapter 7).

4.4.1. Basic idea

The basic idea of the proposed coupled inductor application is shown in Figure 4-25. The figure shows a single-switch boost converter with two parallel LED branches, as an example. However, the principle can be applied to system with n-branches. In contrast to the topologies in Section 4.3.2 with individual branch inductances Lx, a coupled inductor with self inductances L1 and L2 is used here. It is supposed to improve current balancing when compared to the basic boost topology of Figure 4-12 (b) – even at large forward voltage deviations. The remaining structure is kept identical and the converter is still operated in DCM.

Figure 4-25: Boost converter with coupled inductor for improved current balancing

An analysis has been performed for this two-branch topology to describe the current balancing technique and to calculate the system’s performance in equalizing the LED currents.

Vin

QD1

L2

D2

D3

D4

L1

V LED

V LED

+ΔV

LEDin

i2

i1


4.4.2. Analysis of current balancing behaviour

Similar assumptions, as in Sections 4.3.1 and 4.3.2 are used to describe the current balancing performance of the coupled inductor technique:

A converter with two LED branches is used for reasons of simplicity

The LED strings are modelled as ideal voltage sources: branch 1: VLED and branch 2: VLED+ΔVLED

The dependency of the LED forward voltage from the LED current is neglected for reasons of simplicity

Ideal inductors, capacitors and switching devices are assumed: conduction and switching losses are therefore neglected

Figure 4-26 shows the resulting basic current waveforms with the input current in and the two currents in the coupled inductor windings i1 and i2. As can be seen from the figure, 4 modes of operation are obtained when the converter is driven in DCM.

Figure 4-26: Converter current waveforms when operated in DCM

The winding-currents i1, i2 and voltages vL1, vL2 of the coupled inductor can be determined with the help of an equivalent magnetic circuit model, as described in [UP11]. The magnetic core circuit diagram is shown in Figure 4-27.

Figure 4-27: Magnetic circuit model of two-phase coupled inductor according to [UP11]

The figure shows a two-branch coupled inductor with a winding package n on each core leg. R1 and R2 are defined as equivalent lumped magnetic reluctances of each part of the magnetic

0

1

2

3

4

0 0.5 1 1.5 2 2.5 3

in(t)

i2(t)

i1(t)

t1 Ts

ΔI

2 43Converter modes:

ini1i2

78 Chapter 4

core. The reluctance Rμ is defined as the leakage path through the air. The core-fluxes Φ1, Φ2

are determined by the magnetomotive forces Θ1, Θ2 of each winding. As only a small air gap is embodied in the coupled inductor, the reluctance R1 is considered to be much larger than R2

and R2 is assumed to be negligible. With Rs=Rμ/n, the following equation is obtained:

R R RR R

Assuming negligible winding resistances, equal turns number and equal fluxes in all winding turns N, the equation can be rewritten by applying the law of inductance VL=N·dΦ/dt.

R R RR R R

The winding currents can now be obtained from matrix inversion R , with R = reluctance matrix. The voltages vL1 and vL2 across the coupled inductor windings can be written in matrix form as:

, where M is the mutual inductance and Ls represents the leakage inductance of the coupled inductor: M=N² ·Rs /( R1²+n· R1·Rs) and Ls=N² /( R1+n·Rs).

With the definition of the coupled inductor equation the four converter modes, shown in Figure 4-26, can be analysed in the following.

Converter mode 1

In mode 1, the power switch Q is turned on, and the input current in is rising linearly to its maximum value ΔI (Figure 4-26: mode 1). Figure 4-28 shows the resulting simplified circuit diagram; the active circuit parts are shown in black.

Figure 4-28: Simplified circuit diagram of converter mode 1

During mode 1, the voltages across the coupled inductor are equal: vL1=vL2=Vin – the inductor currents are therefore also identical i1=i2. Inserting these dependencies in (4.4.3) and solving for di1/dt and di2/dt leads to the following simplified equation:

VinQD1

L2

D2

D3

D4

L1

in

i2

i1

I.VLED VLED+ΔVLED


The input current is defined as in=i1+i2. With (4.4.4) valid, the input current can be written as:

It can be seen from (4.4.5) that the current is only dependent on the leakage inductance due to the reversed winding orientation.

Converter mode 2

At switch Q turned-off, mode 2 is entered and the current i1 and i2 will decrease linearly until the current of branch 1, with the lower forward voltage VLED reaches zero. By using the resulting simplified circuit diagram of Figure 4-29, with current node (1), voltage loops I. and II., the input- and branch-currents can be expressed, as follows.


The inductor voltage vL2 can be expressed according to voltage loop II. as:

, with vL1 obtained from voltage loop I.:

Inserting (4.4.6) and (4.4.7) in the general equation for the coupled inductor (4.4.3) and solving for di1/dt and di2/dt leads to:

Again, the input current in can be obtained with current node (1): in=i1+i2. Hence din/dt is defined as:

Converter mode 3

Mode 3 is obtained when the current i1 in branch 1 becomes zero. Hence, only branch 2 is active and in=i2. Now, the simplified circuit diagram of Figure 4-30 becomes valid.

Vin

L2

D3

D4

L1

in

i2

i1

I.

VLED VLED+ΔVLED

(1)

II.

80 Chapter 4


The inductor voltage vL2 can be expressed according to voltage loop I. as:

vL2 can also be expressed by means of (4.4.3), where i1=0:

The current in=i2 can now be determined by inserting (4.4.11) into (4.4.10) and rearranging:

It can be seen from (4.4.12) that din/dt is dependent on the voltage difference between input and output voltage. It is also influenced by inductance L2=M+Ls. Mode 3 is therefore typically very short for reasonable large values of Vin-VLED-ΔVLED and of L2.

Converter mode 4

Mode 4 is achieved, when the current i2 becomes zero and therefore no current will flow in the power section of the converter.

Resulting current balancing performance

Numerical combination of the individual conduction modes can be used to describe the system’s current balancing performance. The averaged LED currents Iavg1 and Iavg2 can be obtained by integrating the time-dependent inductor currents i1 and i2 in mode 2 and 3. The resulting relative current deviation between the two branches can then be calculated in analogy to sections 4.3.1 and 4.3.3, with ΔIrel:

A simplified analytical expression can be additionally obtained for ΔIrel when mode 3 is small and assuming it to be negligible for current balancing. With this assumption, ΔIrel_simp can be expressed as:

Vin

L2

D3

D4

L1

in

i2

I.VLED VLED+ΔVLED

(1)


Figure 4-31 shows the calculated resulting current deviations ΔIrel plotted over the size of the coupled inductor’s mutual inductance M. The charts have been created for different forward voltage deviations ΔVLED for reasons of comparison. The input parameters used in the calculation are given in Table 4-6.

The chart shows the values obtained from the analysis plotted as solid lines for ΔIrel, whereas the values calculated with the simplified expression (4.4.14) are plotted as dots.

Figure 4-31: Relative current deviation ΔIrel and ΔIrel_simp over mutual inductance M for different values of ΔVLED

It can be seen from the figure that already small values of M contribute to a increased current balancing performance compared to the basic boost converter topology (Figure 4-13 (b)), e.g. with ΔIrel<4 percent at ΔVLED=0.1•VLED and M=20μH. Increasing M further contributes to decreased ΔIrel, but at the cost of increased inductor size.

Table 4-6: Input parameters for Figure 4-31

Vin

[V]VLED

[V]Duty cycle

DSwitching frequency

fs [kHz]Ls

[μH]

12 30 0.425 300 9.4

A comparison of the accurate and simplified model shows a good agreement between ΔIrel andΔIrel_simp for values of M>20μH and ΔVLED≤0.17•VLED for the given input configuration.

The current deviation ΔIrel has also been calculated for different voltage ratios of Vin/VLED and for a variable ΔVLED. Ls has been kept identical to prior calculation, the mutual inductance has been selected as M=25μH. The converter’s duty cycle D has been adjusted to obtain an LED current of ILED=250mA for the different Vin/VLED.

0

1

2

3

4

5

6

7

8

20 40 60 80 100

Rel

ativ

e br

anch

curr

entd

evia

tionΔI

rel[%

]

Mutual inductance M [μH]

ΔVLED/VLED=7/30

ΔVLED/VLED=1/30

ΔVLED/VLED=3/30ΔVLED/VLED=5/30

82 Chapter 4

Figure 4-32 shows the results of the calculations with ΔIrel plotted over the forward voltage deviations ΔVLED/VLED.

Figure 4-32: Relative current deviation ΔIrel versus relative forward voltage deviation ΔVLED /VLED for different voltage conversion ratios

The charts show that increased forward voltage deviations have less impact on the resulting current deviations compared to the basic boost-topology with inductive current balancing (Figure 4-13), as already visualised in Figure 4-31. Furthermore, the influence of different voltage conversion ratios VLED/Vin is also less pronounced.

4.4.3. Operation with LED failures

Short- and open-circuit LED failures are critical operation modes that affect the performance of LED-lighting systems. Their influence on the LED-driver’s current balancing performance will be highlighted in the following.

Short-circuit failure

The coupled inductor approach can also be used to maintain stable LED output currents at LED failures with short circuit. A shorted LED leads to increased forward voltage deviations between the LED branches which are directly compensated by the coupled inductor. Hence, the same analysis, as in Section 4.4.2, can be performed for the resulting current balancing performance at short-circuit failures.

The shorted LED will lead to a reduced branch voltage, which can be expressed with anegative value of ΔVLED in the analysis. Again, the LED branch with the higher di/dt will define when mode 3 is entered. It has to be noted, that the forward voltage which gets reduced by ΔVLED will increase the length of mode 3 (as can be deduced from (4.4.12)) and converter operation in CCM could be possible and has to be avoided in the LED-driver design.

0

1

2

3

4

5

6

7

4 6 8 10 12 14 16 18 20

ΔIre

l[%

]

ΔVLED/ VLED [%]

8

10

12

15

17

VLED / Vin = 2.5

VLED / Vin = 1.76

VLED / Vin =3.75

VLED / Vin = 3

VLED / Vin = 2


An example configuration will be used in the following to visualise the current balancing behaviour after single LED failure with short circuit. The two-branch system of Section 4.4.2is used again for the calculations.

LED forward voltages of VLED1=30V and VLED2=33V appear in this configuration under normal operation. The worst case scenario which has to be compensated is a LED failure in branch 1, leading to a branch voltage of VLED1=27V. Hence, a voltage difference of ΔVLED=6Vhas to be compensated by the coupled inductor.

Figure 4-33 shows the calculated current deviation between branches 1 and 2 after short circuit failure plotted over the considered input voltage range Vin=8-17V. The charts have been generated for different values of mutual inductance M. The duty cycle has been adjusted to maintain an LED current of ILED1=250mA.

It can be seen that current deviations are reduced to below 10 percent over the entire input voltage, when a mutual inductance of M=25μH is used for current balancing. With these parameters, DCM operation is still ensured over the entire input voltage range.

Figure 4-33: Relative current deviation ΔIrel over input voltage at single short-circuit LED failure

It has to be noted that a single LED failure will lead to increased branch currents, when the converter duty cycle remains constant. The resulting current increases are comparable to the values introduced in Figure 4-33 and should therefore be uncritical in most applications.

Open-circuit failure

The presented two-branch topology can additionally be extended by a simple anti-parallel diode network to also compensate LED failures with open circuit. Figure 4-34 shows aprinciple schematic of the resulting topology with an additional diode network connected between the LED branches. For reasons of simplification, the diode network is illustrated with a series connection of a diode and a voltage source.

The diode network has to be designed so that its forward voltage Vx is larger than the forward voltage difference of the two LED branches. Hence, the diode network will be inactive under

0

2

4

6

8

10

8 10 12 14 16

Res

ultin

gbr

anch

curr

ent

devi

atio

nΔ I

rel[

%]

Input voltage Vin [V]

M=25uH

M=50uH

M=100uH

84 Chapter 4

normal converter operation. After an open-circuit failure, the diode branch connected in normal direction will start to conduct. Thus, the complete energy stored in the coupled inductor will be transported to the remaining LED branch when a lossless diode network is assumed.

Figure 4-34: Diode network to compensate open-circuit LED failures for two-branch systems

The system can be designed that the remaining LED-branch is operated with increased power after open circuit failure to obtain a comparable light output as before failure, whenever the LED’s maximum ratings allows this mode. In this case, the LED-driver would be operated with the same duty cycle as before failure. It has to be considered that systems with increased branch number cannot be adapted with a simple diode network for power transfer. More complex networks with active switches are required for this purpose.

Different possibilities exist to detect the open or short-circuit failures by utilising current sensing or (differential) voltage measurement. Their practical implementation in a 3D-MID-based LED-driver will be commented in the final case study prototype in Chapter 7.


A prototype two-branch LED-driver with coupled inductor has been built and tested to verify the theoretical predictions obtained from the analysis and results of sections 4.4.2 and 4.4.3.

Prototype 2: specification

The converter has been designed to be directly operated from the 14V automotive power net and a fixed switching frequency of fs=300kHz is used. Duty cycle control is used to compensate input voltage variations. Nevertheless, switching frequency adjustment could be a further option. Figure 4-35 shows the prototype topology.

Vin

QD1

L2

D2

D3

D4

L1 Vx

Vx


Figure 4-35: Prototype topology

Each of the two LED branches is realised with ten Luxeon K2 [Ph07a] high-power LEDs connected in series. The LED power consumption is approximately PLED=15W when operated at an LED current of ILED=250mA. The prototype has been realised on a single layer 3D-MID with a copper thickness of tCu=10μm. A discrete input inductance Lin is connected in series to the coupled inductor Lc to overcome issues in implementing a reasonably large leakage inductance Ls directly into Lc. Table 4-7 summarises the resulting LED-driver specification for the given automotive application and implemented in the prototype. The system will be called Prototype 2, subsequently.

Table 4-7: Prototype 2: specification and component values

Vin

[V]ILED

[mA]VLED1

[V]VLED2

[V]Switching frequency

fs [kHz]Lin

[μH]

L1=L2 Branch capacitors[μF]M [μH] Ls [μH]

8-17 250 29.81 29.99 300 4.7 25 0.2 4.7

Filter capacitors have been connected in parallel to the high-power LEDs to maintain approximately dc LED-currents.

The system is designed to compensate single short circuit failures without adjusting the output current, as only small current deviations are expected for the short circuit case. At open circuit failure, the complete input power is supposed to be transported to the remaining LED-branch to maintain a brightness level close to the system’s light output before LED failure.

Current balancing performance

Figure 4-36 shows measured prototype waveforms, with the MOSFET’s drain-source voltage as well as the currents i1 and i2 in the coupled inductor at minimum-input voltage Vin=8V and at nominal input voltage Vin=14V.

It can be seen that the system operates in DCM even at minimum input voltage and that the inductor currents are nearly identical leading to equal LED currents as well.

Vin

QD1 D2

D3

D4Lc

Lin

LED

-bra

nch

2

LED

-bra

nch

1

C1 C2

Cin

Dx

86 Chapter 4

Figure 4-36: Ch1: Switch-Voltage (20V/div), Ch3-Ch4: inductor currents i1 and i2 (1A/div), time scale 2μs/div

The current balancing performance of the LED-driver has been measured for different forward voltage deviations and over the entire input voltage range. In this case, VLED1 has been kept constant at VLED1=30V and VLED2 has been decreased by first shorting one LED and then two LEDs, leading to ΔVLED1=-2.7V and ΔVLED2=-5.4V. The results of these investigations are summarised in Figure 4-37, where the measured values are given as discrete points and values obtained from the analysis are given as lines. The duty cycle has been adjusted to maintain an LED current of ILED1=250mA.

Figure 4-37: Current balancing performance versus input voltage

The charts show that even large voltage deviations that have been caused by short-circuit LED failures, with ΔVLED2=-5.4V only cause LED current deviations of below 10 percent over the entire input voltage range, as expected from the analysis.

LED failures with short- and open circuit

Figure 4-38 finally shows exemplary LED current waveforms at (a) LED failure with short circuit and (b) at open circuit in one branch. In both cases, no duty cycle adjustment has been performed to compensate the output currents.

Vin=8V

Ch1

Ch3

Ch4

Vin=14V

Ch1

Ch3

Ch4

0

3

6

9

12

15

8 10 12 14 16

Rel

ativ

e cu

rren

t dev

iatio

n be

twee

n br

anch

1 a

nd 2

[%]


ΔVLED=2.7V ΔVLED=2.7V

ΔVLED=5.4V ΔVLED=5.4V

ΔVLED= -2.7V:

ΔVLED= -5.4V:

measured calculated

measured calculated


Figure 4-38: LED currents at failures (a) short circuit (b) open circuit – 100mA/div, time scale 500ms/div

It can be seen from (a) that the short circuit of a single LED only leads to a minor change of the total output currents (<10 percent), as expected from the analysis. The open circuit failure (b) shows that the diode network is immediately active and the LED current in the active branch has increased, as supposed from the given system specification. Thus, the converter’s duty-cycle has to be decreased to obtain the initial LED current if this mode is desired.

4.5. Integration of external PWM dimming

The previous sections described how to integrate the brightness distribution network into the LED-driver’s power converter. In a final step, the possibility of also integrating the external network for PWM brightness control of state of the art dimming solutions (Chapter 2.2.2 and Figure 4-39 (a), (b)) into the power converter topology itself will be discussed next.

The aim of this approach is to enable integrated dimming whilst maintaining a comparable dimming performance as with external PWM dimming. By generating the low frequency pulse-width-modulated LED current directly with the power converter switching cell, the extra dimming switch and required control components would get obsolete. Hence, only the power converter cell would serve as LED-driver. Consequently, also signal traces and hence wiring complexity could be further reduced, simplifying the realisation of LED-lighting systems on 3D-MIDs.

An integrated dimming approach is also beneficial for 3D-MID LED-lamps with LEDs attached on one surface and the power electronics on the opposite side (Chapter 3 – double sided configuration) because no dimming signals would have to be transported through the circuit carrier to the dimming components. Hence, additional vias required for dimming could get obsolete.

4.5.1. Basic idea and operation principle

Chapter 2 already introduced, that PWM-dimming (Figure 4-39 (a)) is used in the majority of LED-lighting applications, rather than linear dimming (Figure 4-39 (b)). Reasons for the PWM application are, that linear dimming suffers from a reduced accuracy at high-dimming

Branch 1

Branch 2Short circuit in 2

(b)

Branch 1

Branch 2

Open loop in 1

(a)

88 Chapter 4

ratios because of the non-linear current-voltage characteristics of the LEDs and further causes an LED colour shift, which can be noticed by the human eye [MSP022], [Os07]. In contrast to this, PWM dimming always operates the LEDs at a constant current and hence, precise brightness regulation and minimized colour shift are obtained. However, at low duty cycles PWM dimming suffers from a reduced luminous efficacy compared to dc current operation and requires external dimming networks [Sa06], [GH06].

Figure 4-39 (c) shows the proposed topology with integrated PWM dimming. The LED current waveform is modulated directly by the switching converter leading to the proposed integrated dimming approach [TP09a].

Figure 4-39: State of the art dimming methods (a),(b) and proposed approach with integrated dimming (c)

The output current of the converter is regulated via a reference dimming signal which is a low frequency PWM signal. The disadvantage of this method is the limited di/dt of the LED current due to the output filter components of the power converter, which are designed to allow nearly constant LED currents at 100 percent duty cycle. The limited di/dt may therefore lead to non ideal PWM current waveforms, which may cause an undesired colour shift of white LEDs when operated at reduced brightness.

Low current slopes are normally uncritical for designs with static light sources, as low modulation frequencies of 100 Hz would be sufficient for PWM dimming to avoid flickering. However, in applications with moving light sources, as in automotive exterior lighting, the turn-on and turn-off of the LEDs could be perceived as flickering at frequencies of up to the low kHz frequency range, and consequently higher dimming frequencies are needed.

Limited di/dts are therefore more critical and their influence on LED colour stability could be noticeable by the human eye. Hence, the degree of current slope dependent colour shift has to be quantified and is essential for an LED-driver design with modulated dimming.

4.5.2. Investigation of dimming related colour shift

In many LED data sheets colour coordinates are often only available at nominal dc current [Os07]. For some LEDs data is available concerning the chromaticity shift during linear dimming in Δx, Δy -coordinates according to CIE chromaticity diagram from 1931 [Sc03]. Hence, data concerning the colour shift caused by different waveforms of the LED current are not available and have to be determined experimentally.

Linear dimming signal

Vin

DC

DC

(a)

Switch-control

Vin

DC

DCQ

Dimmingsignal

(b)

Dimming signal

Vin

DC

DC

(c)


Investigations have been performed on the colour stability of the three possible dimming methods presented in Figure 4-39. The investigation contains typical white high-power LEDs used in automotive lighting applications.

Test configuration

Three different waveforms have been used in the experiments to quantify the influence of different current shapes on LED chromaticity values:

Signal I: dc currents regulated between 50mA and 350mA,

Signal II: pulse-width modulated current with 350mA as high level current

Signal III: trapezoidal currents with “duty-cycle” D and current slopes di/dt = 0.1•D

The waveforms are visualised in Figure 4-40.

Figure 4-40: Investigated LED current waveforms

The rising and falling times of signal III are defined to represent the limited current slope expected with the modulated dimming approach. The duty cycle D of signals II and III has been adjusted to keep the luminous flux constant and a programmable current source has been used to create the tested waveforms. All optical measurements have been performed in an integrating sphere and at constant junction temperature for comparable data. The LEDs have been mounted on a heat sink unit with peltier elements to regulate the LED junction temperature Tj. Therefore, the temperature sensitive LED-forward voltage has been used as feedback for the control of Tj.

Additional measurements with constant heat sink temperature and short-term current flow (ton<200ms), to reduce the self-heating of the LEDs, have been performed to verify prior results.

Test evaluation

Figure 4-41 shows the measured shift of the chromaticity values (Δx and Δy) of two comparable types of high-power LEDs – LED I [Os07] and LED II [Ph07a] – plotted over the average LED current.

I/INOM

0.5

1

00.2 0.4 0.6 0.8 1

Signals

I: DCII: PWMIII: Trapezoid

di/dt=0.1·D

D=0.1...1

di/dt

90 Chapter 4

Figure 4-41: Measured chromaticity shift of Δx and Δy due to different current waveforms for two different types of high-power LEDs

The following results can be deduced from the measurements of the investigated LEDs:

Dc current leads to the largest colour shift for both LED types, as reported in several publications [MSP02]. The results are in close correlation with the data sheet values given in [Os07].

PWM dimming also causes a measurable colour shift over the dimming range. These results are concordant to [MT05] which shows that there is a colour shift due to PWM operation of LEDs. The paper’s authors account this with a reduced efficiency of the phosphor layer at dimmed operation.

Different magnitudes Δx and Δy have been determined between LED types I and II for PWM control.

The trapezoidal signal (III) leads to higher chromaticity shifts than the PWM method. Its extent increases with larger dimming ratios and reaches values half of the linear dimming approach.

It can be derived from the foregoing results, that achieving modulated converter dimming with colour stabilities comparable to PWM colour stabilities shows the necessity to maximize the di/dt of the LED current.

A converter analysis is therefore required to determine the dynamics of the output LED-current when modulated dimming is used, and will be performed next.

4.5.3. Converter design for modulated dimming

A single branch buck-boost converter topology will be used in the following to describe the resultant di/dt in the LED current iLED when operated with modulated dimming. However, the analysis can be applied in a similar way for the multi branch buck-, boost- and flyback- topologies, developed in Sections 4.3 and 4.4 which offer inductive current balancing and power sharing.

0

0.001

0.002

0.003

0.004

0.005

0.006

40 140 240 340

Col

our

shiftΔx

(CIE

193

1)

Average LED current [mA]

Linear LED IPWM LED ITrapezoid LED ILinear LED IIPWM LED IITrapezoid LED II

0

0.002

0.004

0.006

0.008

0.01

40 140 240 340

Col

our

shiftΔy

(CIE

193

1)

Average LED current [mA]

Linear LED IPWM LED ITrapezoid LED ILinear LED IIPWM LED IITrapezoid LED II


Figure 4-42 (a) shows the power converter configuration used for analysis. The converter drives a series string of 5 LEDs and the output filter is supposed to provide approximately dc LED currents for a high optical efficacy [Sa06], [Sc07].

Dimming is provided by the external modulation signal M with adjustable duty cycle. Figure 4-42 (b) shows the dependency between the modulation signal M and the corresponding duty cycle D of the converter.

Figure 4-42: (a) Buck-boost converter topology with modulated dimming and (b) dependency between modulation signal M and duty cycle D

The duty cycle D is adjusted to provide nominal LED current, when the external modulation signal M is on high level. The duty cycle D is set to zero when the external modulation signal is on low level and the LED current will fall to zero.

The LED brightness can therefore be controlled by varying the duty cycle of the modulation signal. The converter must ideally be designed to provide a constant current with low ac component superimposed to the LEDs when the modulation signal is high, zero LED current when the modulation signal is low.

The input filter inductor

When the external modulation signal is switched to low-level, the MOSFET Q is turned-off and the total energy stored in the input inductor L is fully transferred to the output of the converter. Decreasing this energy will increase the converter dynamics at turn-off and will therefore decrease the fall-time of the LED current. The minimum energy stored in the inductor is achieved when the converter operates in DCM.

Operating the converter in DCM has the additional benefit that the inductor current is immediately in steady state when the external modulation signal is switched to high-level, as shown in Figure 4-43.

Figure 4-43: Inductor current at switch-on for DCM and CCM

CiVin

vLEDiLEDiin

L D

voDrive

Q outputfilter

M D

external modulation signal

duty cycle

t

t

D

M

(a) (b)

DCM

tD1

CCM

tD D‘

iL iL

LI LITon

D2

92 Chapter 4

This is a result of the relatively constant converter output voltage even when the external modulation signal is low because of the non-linear current-voltage characteristic of the LEDs. Hence, the output capacitor is not discharged to zero.

The input inductor of the proposed converter is designed to achieve DCM operation for the whole range of input and output voltage variation. Furthermore, DCM operation is essential for the developed inductive current balancing technology and makes the systems to be very suitable for integrated dimming.

The size of the input filter inductance can be determined by using the equations (4.3.12),(4.3.13) and with Vin as the minimum input voltage when the converter is operated at boundary of DCM D2=1-D. The energy stored in the input inductor is constant, as shown in Section 4.3.2. Increasing the input voltage will cause the duty cycle D1 to decrease and the converter operates "more discontinuous". As a consequence of the DCM converter operation, the dynamic behaviour of the LED current iLED is mainly determined by the output filter components.

The output filter

The design of the converter’s output filter for modulated dimming leads to two trade-offs which have to be considered:

Approximately dc currents at maximum power should be achieved for best optical efficacy of the LEDs. The output filter therefore has to reduce the ac components of the diode current flowing into the filter.

The step response of the output filter should be as fast as possible to allow the LED current to follow the external modulation signal.

Figure 4-44 shows the gate-drive signal, the corresponding inductor and diode currents and the averaged diode current when the external modulation signal is at high-level. The diode current waveform is independent of the converter input voltage. By assuming the output voltage approximately constant Δvo << Vo, the diode current can be modelled as an ideal current source.

The LED string is represented by an ideal voltage source with a resistance connected in series and the size of the input capacitor is assumed much larger than the size of the output filter capacitor.

Figure 4-44: Converter waveforms

Gate drive-signal

Ts

Inductor current

Diode current

Averageddiode current

Î

t

t

t

t


Figure 4-45 shows the resulting simplified model of the converter operating at DCM. Different output filters have been considered (C, C-L). The analysis’ aim is to find the most suitable output filter arrangement that is able to achieve a high di/dt at modulated dimming for a given high frequency LED current ripple îLED, which has no significant influence on the luminous efficacy of the LEDs, as shown in [Sa06].

Figure 4-45: Simplified converter model with different output filter structures (a) C-filter (b) C-L-filter

The analysis proceeds by calculating the magnitude of the fundamental diode current iD by applying Fourier-analysis and the magnitude of the LED current based on the frequency response of the output filters. In a second step the rise and fall times of the LED current have been calculated from the corresponding transfer-functions of the output filters and are compared for the different filter arrangements. The frequency responses of the C and C-Lfilter are as follows:

From equation (4.5.1) we obtain for the purely capacitive filter for a given attenuation A the required output filter capacitor Co:

From equation (4.5.2) we obtain for the C-L-filter:

, and

Where ξ is the damping ratio and should have values of about 0.5 to limit the over-current of the LED during time-response of a step input signal to values below 120 percent. The two filter designs of the purely capacitive output filter and the C-L output filter will now be compared in terms of their rise and fall times when the external modulation signal is applied. By averaging the diode current we may approximate the externally modulated diode current

vLED

RD

VD

Co

iLEDiD

filter

LED

(a)

filter

Co

Lo

(b)

94 Chapter 4

by a simple pulse function, as shown in Figure 4-44. The current step function is applied to the C and C-L filter.

Considering the initial conditions of the capacitor voltage and the inductor current we are able to calculate the rise and the fall times of the LED current for both output filters:

With,

The step response of the purely capacitive filter is an e-function. The rise and fall-times have been determined until 90 percent or 10 percent of the final value have been reached. Hence, β=0.1.

An example converter has been designed with specifications and component values given in Table 4-8 and will be used for comparison.

Table 4-8: Converter target specification and component values

InputvoltageVin [V]

OutputvoltageVLED [V]

LED current

ILED [mA]

Switching frequency

fs [kHz]

Inductance

L [μH]

C-Filter

Co [μF]

C-L Filter LED model

Co[μF]

Lo[μF]

VD

[V]RD

[Ω]

8-17 16.5 330 330 7.6 1 0.31 7.8 14.75 5

The input inductor of the converter has been calculated to achieve boundary of discontinuous mode of operation at minimum input voltage of 8V. The C- and the C-L-output filters have been calculated for an attenuation of A=0.1. The RMS value of the LED ripple current fundamental is therefore limited to approximately 50mA.

By using (4.5.6) and (4.5.7) the rise and fall-times of the LED current can be calculated, leading to the values presented in Table 4-9.

Table 4-9: Rise- and fall- times of LED current

FilterΔton turn-on [μs] Δtoff turn-off [μs]

Calculated Pspice Calculated Pspice

C 11.5 12.3 11.5 12.8

C-L 3.7 3.6 3.7 3.9


Values obtained from a Pspice simulation are given in addition. The table clearly shows the better performance obtained from the proposed converter with C-L output filter, supporting even high dimming frequencies of several kilohertz.


A prototype converter has been built and tested to verify the dynamic performance of the converter and the colour stability of the LEDs. The system consists of the proposed buck-boost topology with 5 Luxeon K2 LEDs (LED II) connected in series, as introduced in Figure 4-42. The prototype has the same specification as the example system defined in Table 4-8and will be called Prototype 3 in the following.

Values of Co=0.3μF and Lo=10μH have been selected for the converter’s C-L output filter for convenience. L has been set to 7.5μH to provide DCM operation over the whole input voltage range. The drive signal of the converter is obtained from a microcontroller which modulates the 330 kHz switching frequency.

Figure 4-46 shows the measured waveforms of the external modulation signal, the drive-signal of the MOSFET, the converter output voltage and the LED current at a modulation frequency of 5 and 20 kHz. The prototype achieves a Δton=5.6μs and Δtoff=5.0μs and a LED current ripple of ±45mA when turned on.

Figure 4-46: Prototype 3 waveforms: CH1: external modulation signal, CH2: MOSFET drive-signal, CH3: output voltage, CH4: LED current (200mA/div)

A comparison of chromaticity shift Δx, Δy over the modulation signal’s pulse width and hence, over the average LED current is shown in Figure 4-47. Here, the prototype is running at modulation frequencies of fmod=5kHz and fmod=20kHz. It can be seen that the colour shift during dimmed operation at fmod=5kHz is comparable to the colour shift of the measurements with an ideal PWM signal based on an external switch (Figure 4-41 LED II).

96 Chapter 4

Figure 4-47: Colour shift of LED II over pulse width at 5 kHz and 20 kHz modulation frequency

The measurement also shows that the higher modulation frequency of 20 kHz leads only to asmall increase in chromaticity shift, as expected from the large di/dt the output filter achieves.

The modulated dimming approach has additionally been applied to Prototype 2 and the flyback topologies (Section 4.3.3) [TP10a], [TP10b].

Figure 4-48 shows exemplary waveforms of Prototype 2 operated with modulated dimming atfmod=1kHz. The figure shows the modulation signal M and the resulting pulse width modulated LED currents of the two-branch system.

Figure 4-48: Measured waveforms of Prototype 2: CH1: external modulation signal M, CH3: LED current

branch 1 (200mA/div), CH4: LED current branch 2 (200mA/div), Time-scale: 500μs/div

It can be seen from the waveforms that Prototype 2 also achieves a good accuracy in PWM dimming with sufficiently high di/dt for the tested dimming frequency, contributing to stable LED colour values over the dimming range.

0

0.0005

0.001

0.0015

0.002

0.0025

0.003

0.0035

0.004

40 90 140 190 240 290 340 390

Col

or S

hift

Δx,Δy

(CIE

193

1)

Average LED current in mA

5kHz dx5kHz dy20 kHz dx20 kHz dy


4.6. Overview of developed LED-drivers for 3D-MID application

A new principle of passive current balancing in parallel LED networks has been introduced. This method combines the current balancing network with state of the art power converter topologies, which acts as an integrated solution of the power supply and the brightness distribution to high-power LEDs. As a consequence, a reduced system complexity and component count can be achieved in the resulting LED-driver.

Table 4-10 compares the existing LED-driver topologies for current balancing (already introduced in Table 4-3) with the developed inductive current balancing principle. Table 4-10: Comparison of conventional LED-driver principles with proposed inductor current balancing

Power converter *) with serial LEDs

Power converter with parallel LEDs and current balancing

Single converter

Multipleconverter(-cells)

Resistorapproach

Capacitorapproach

Activecontrol

Inductor current

balancing withintegrated dimming

No. of switching cells 1 ncell 1 1 1 1

No. of active switches 1 ncell 1 1 nbranch + 1 1

PWM dimming with topology

possible?√ √ √ O √ √

PWM dimming directly with

topology possible? **)

O O O O √ √

Suitability for high-power

LEDs√ √ O O √ √

Output voltage

No. of permanent

active LEDs

Routing complexity ++ + ++ - -- +

Dominating limitation for

target application

Output voltage

No. of components Power losses Light output Wiring

complexity /

√=yes, O=no *) For reasons of simplicity a single switch boost converter is assumed as power converter topology

**) Directly means that no additional external switching networks are required to obtain PWM-dimming

It can be seen from the table that the inductor current balancing principle with integrated dimming is able to compete with the active current control in terms of fulfilling required lighting functions with high-power LEDs.

98 Chapter 4

Moreover, the number of active components, e.g. switches and their control, are greatly reduced with the developed techniques of current balancing with integrated dimming feature. This is essential for a simplified LED-driver realisation on 3D-MIDs.

The proposed technology of current balancing is further able to work with a variety of power converters with step-up or step-down functionality and can also be applied to different topologies with and without galvanic isolation.

Table 4-11 finally summarizes the resulting current balancing performance ΔIrel of the investigated topologies, when systems with two LED-branches are supplied. The current balancing performance describes the relative deviation of the two average LED currents, as defined in (4.3.8). It is also noted in the table, when an equal power operation of the LEDs is possible with the investigated topologies.

Details on the individual operation principles and analyses are given in the individual sections, as indicated in the table.

Table 4-11: Comparison of brightness distribution performance

Mode Current-sharing performance ΔIrelEqual power

operation availableDescription in Section

Buck DCM O 4.3.2

Boost DCM O 4.3.2

Buck-Boost DCM X 4.3.2

Flyback

DCM X 4.3.3

CCM O 4.3.3

Boost with coupled inductor

DCM O 4.4.2

X=yes, O=no

4.7. Summary

The 3D-MID technology requires new concepts of power electronic LED-drivers to obtain a simplified and compact realisation on single- or double layer 3D-MIDs with low number of components and reduced wiring effort. The LED-drivers have to provide essential lighting functions, like precise brightness control and -distribution among a multitude of LEDs as well as LED-failure compensation


In this chapter, adapted LED-drivers that use a new passive brightness distribution principle for high-power LEDs combined with a simplified modulated dimming approach that are directly integrate able in the LED-driver are developed.

A compact survey of contemporary LED-drivers is performed in Section 4.2 and shows the necessity of adapted topologies with low circuit complexity for a 3D-MID realisation, as state of the art systems contain separately and independently designed current balancing- as well as dimming networks with high system complexity and component count. Especially, active current balancing techniques require extra sensing- as well as control-traces and furthermore suffer from unwanted inhomogeneous loss distributions at LED failure.

A novel principle of inductive brightness distribution which can be directly integrated into a variety of different isolated and non-isolated power converter topologies for simplified 3D-MID realisation is developed in Section 4.3. It allows low wiring complexity and low numbers of components required. The topologies’ operations in current balancing mode and equal-power mode are analysed and experimentally verified with prototype systems of different power classes. The results verify the principle’s good brightness distribution performance

Introducing inductor coupling to the proposed current balancing principle can be beneficially used to improve the LED-brightness distribution at large LED forward voltage deviations. It is further shown that the coupled inductance can be directly used to compensate single LED short-circuit failures, whereas a simple diode energy transfer network can be used in two-branch LED-systems to compensate open-loop failures whilst still maintaining a low wiring complexity (Section 4.4).

The integration of commonly used external PWM-dimming networks in the power converter has been identified as further means to decrease the component count as well as to reduce the wiring complexity (Section 4.5). Colour measurements are used to classify dimming related colour shifts and converter filter analyses are used to obtain a high converter dynamics at modulated dimming. The technique has been successfully applied to different power converters and has been verified with prototype systems. The presented technique achieves agood LED colour stability comparable to conventional PWM dimming but is able to work with reduced component count and wiring complexity. This makes the developed technique especially suitable for 3D-MID applications.

The developed topologies for current balancing and modulated dimming for high power LEDs cover are wide range of input voltage variations, as well as LED power levels, ranging from 5W LED power (Prototype 3) to 45W (Prototype 1) and are therefore usable in a variety of lighting applications with 3D-MIDs.

With the proposed principles, the LED-driver no longer contains extra networks for brightness control and -distribution; these functions are furthermore directly integrated in the essential power converter representing the entire LED-driver.

However, the circuit routing, the component realisation as well as the implementation of an effective thermal management on 3D-MIDs will further influence the practical realisation of

100 Chapter 4

3D-MID-based high-power LED-lighting systems. These domains will be discussed in the following chapters.

Bibliography [BZ04] Baddela, S.; Zinger, D.: Parallel connected LEDs operated at high frequency to improve

current sharing. In (Zinger, D. Ed.): 39th IAS Annual Meeting Industry Applications Conference Conference Record of the 2004 IEEE, 2004; pp. 1677 1681 vol.3.

[Cr08] Cree: Cree XLamp MC-E Binning and Labeling, CLD-AP20.002, 2008.

[Cr08b] Cree XLamp MC-E Datasheet, online available at: http://www.cree.com/products/xlamp.asp, 2008.

[De08] Decius, N.: Schaltungsanordnung zur elektrischen Ansteuerung eines Kraftfahrzeug-Scheinwerfers.

[DZ07] Doshi, M.; Zane, R.: Digital Architecture for Driving Large LED Arrays with Dynamic Bus Voltage Regulation and Phase Shifted PWM. In (Sauerlander, G. Ed.): Proc. APEC 2007 - Twenty Second Annual IEEE Applied Power Electronics Conference, 2007; pp. 287 293.

[DZ08] Doshi, M.; Zane, R.: Reconfigurable and fault tolerant digital phase shifted modulator for luminance control of LED light sources: Proc. IEEE Power Electronics Specialists Conference PESC 2008, 2008; pp. 4185 4191.

[GH06] Gu Y., N. N. D. T.; H. Wu: Spectral and Luminous Efficacy Change of High-power LEDs Under Different Dimming Methods: Sixth International Conference on Solid State Lighting, Proceedings of SPIE 63370J, 2006.

[LSL97] Lee, Y.; Siu, K.; Lin, B.: Novel single-stage isolated power-factor-corrected power supplies with regenerative clamping: Proc. 1997. Twelfth Annual Applied Power Electronics Conference and Exposition APEC ’97, 1997; pp. 259 265 vol.1.

[MM05] Marques, L. S.; Mineiro, E. S., JR: Step Down Current Controlled DC-DC Converter to Drive a High Power LED Matrix Employed in an Automotive Headlight: Proceedings of the 8th COBE, 2005; pp. p474-478.

[MSP02] Muthu, S.; Schuurmans, F.; Pashley, M.: Red, green, and blue LED based white light generation: issues and control: 37th IAS Annual Meeting Industry Applications Conference Conference Record of the, 2002; pp. 327 333.

[MSP022] Muthu, S.; Schuurmans, F.; Pashley, M.: Red, green, and blue LEDs for white light illumination. In IEEE J. Sel. Topics Quantum Electron., 2002, 8; pp. 333 338.

[MT05] M. Dyble, N. N. A. B.; T. Klein: Impact of dimming white LEDs: Chromaticity shifts due to different dimming methods: Fifth International Conference on Solid State Lighting, Proceedings of SPIE 594, 2005; pp. 291 299.

[NZ04] Narra, P.; Zinger, D.: An effective LED dimming approach. In (Zinger, D. Ed.): 39th IAS Annual Meeting Industry Applications Conference Conference Record of the 2004 IEEE, 2004; pp. 1671 1676.

[Os07] Osram Semiconductors: Osram Golden Dragon Datasheet ZW W5SG, 2007.



[PZ08] Patterson, J.; Zane, R.: Series input modular architecture for driving multiple LEDs: Proc. IEEE Power Electronics Specialists Conference PESC 2008, 2008; pp. 2650 2656.

[Sa06] Sauerlander, G.; Hente, D.; Radermacher, H.; Waffenschmidt, E. et al.: Driver Electronics for LEDs: 41st IAS Annual Meeting Industry Applications Conference Conference Record of the 2006 IEEE, 2006; pp. 2621 2626.


102 Chapter 4

[Sc07] Schmid, M.; Weiland, W.; Kuebrich, D.; Duerbaum, T.: Evaluation of Power LEDs and their Efficiency by Driving them with Currents typical to switch-mode power supplies: Proceedings of the Power Conversion Intelligent Motion Conference, 2007.

[TP09] Thomas, W.; Pforr, J.: A novel low-cost current-sharing method for automotive LED-lighting systems: Proc. 13th European Conference on Power Electronics and Applications EPE ’09, 2009; pp. 1 10.

[TP09a] W. Thomas; J. Pforr: LED-Driver with integrated dimming feature and its influence on chromaticity values: Proceedings of PCIM Europe 2009, 2009.

[TP09b] Thomas, W.; Pforr, J.: Buck-Boost converter topology for paralleling HB-LEDs using constant-power operation: Proc. The Eighth International Conference on Power Electronics and Drive Systems, PEDS 2009, 2009.

[TP10a] Thomas, W.; Pforr, J.: Isolated converter topology with integrated power-sharing for driving a large number of HB-LEDs. In 2010 14th International Power Electronics and Motion Control Conference (EPE/PEMC), 2010; pp. T6-45.

[TP10b] Thomas, W.; Pforr, J.: Power-transfer of isolated converter with integrated power sharing for LED-lighting system dependent on transformer coupling. In 2010 IEEE Energy Conversion Congress and Exposition (ECCE), 2010; pp. 449–456.

[UP11] Utz, S.; Pforr, J.: Operation of multi-phase converters with coupled inductors at reduced numbers of phases. In Proceedings of the 2011 14th European Conference on Power Electronics and Applications (EPE 2011), 2011; pp. 1–10.

[WLH961] Watson, R.; Lee, F.; Hua, G.: Utilization of an active-clamp circuit to achieve soft switching in flyback converters. In IEEE Trans. Power Electron., 1996, 11; pp. 162 169.

[XB0812] Xi, Y.; Bell, R.: Understand two-switch forward/flyback converters. In Power Design India, 2008.

[YIN92] Yoshida, K.; Ishii, T.; Nagagata, N.: Zero voltage switching approach for flyback converter: Proc. 14th International Telecommunications Energy Conference INTELEC ’92, 1992; pp. 324 329.

[Zh] Zhao, Q.: Performance Improvement of Power Conversion by Utilizing Coupled Inductors.

5. Integration of spatial and electrical functions

5.1. Introduction

The 3D-MID technology shows a high versatility in achieving complex three-dimensional designs and offers the ability to integrate mechanical functions into the circuit carrier, as introduced in Chapter 2. However, circuit routing and component realisation even on planar 3D-MID surfaces differ from conventional PCB technology for three reasons: the process of generating circuit tracks, differences among substrate materials and due to 3D-MID specific design rules.

In Chapter 4, power converters have been developed to supply a multitude of high-power LEDs with a low number of required components. External functions have been directly integrated into the power converters to minimize wiring complexity. The developed passive brightness regulation solutions further contribute to a decrease of layout effort as only a minority of peripheral components, e.g. back-up capacitors, or sensor traces are required for proper circuit operation. All of these countermeasures contribute to reduced effort concerning the 3D-assembly. However, several components still have to be attached and contacted by the 3D-MID which requires careful design of circuit traces, adapted power converter layout and optimised positioning of components.

The aim of this chapter is to systematically determine how the use of the 3D-MID technology influences the geometrical realisation of power converter layouts compared to conventional PCB technology, and how the electrical performance gets affected by resulting circuit track parasitics. Figure 5-1 gives an overview of the domains that will be investigated step by step.

Figure 5-1: 3D-MID example used to describe the domains investigated in this chapter

1. 3D-MID vs. PCB construction2. Contacting of components

5. 3D-routing possibilities and concepts

3. Spatial performance4. Electrical performance

of 3D-MID-based power converters

106 Chapter 5

The individual domains are highlighted as Segments I-III in the figure.

The chapter starts with a comparison of 3D-MID to PCB construction technology (Section 5.2) in order to derive first differences that will generally influence dimensions of the circuit artwork and the routing of power electronics on 3D-MIDs (Figure 5-1: segment I). This leads to current carrying capacity modelling that is performed next to calculate required circuit trace dimensions and allowed current values on 3D-MIDs. The results allow the determination of circuit track parasitics in dependence of 3D-MID conductor geometries (Section 5.3.3) and make a comparison to their PCB counterparts possible.

The influences of the 3D-MID technology on the realisation of power converters on two-dimensional substrates are investigated in detail in Section 5.4. This contains the influence of the 3D-MID technology on the spatial realisation of power electronics, i.e. in terms of component distances and volume utilisation. Furthermore, influences on circuit layout parasitics and on the electrical performance of power electronics on 3D-MID are evaluated by means of case-study converters of different power levels and spatial arrangements. The presented approaches are aimed to be used as means for evaluating the application of future power converter designs on 3D-MIDs. Further, solutions and concepts that can improve component positioning and routing by selective three-dimensional reshaping of the 3D-MID substrate (Figure 5-1:segment III) will be given in Section 5.5.

Finally, the chapter will be summarized in Section 5.6.

5.2. Comparison of 3D-MID and PCB construction

The 3D-MID and PCB technology both allow the contacting and mechanical support of (power-) electronic components as basic functionality. However, 3D-MIDs have been developed to fulfil an extended requirements profile that includes the integration of extended mechanical functions as well as enhanced 3D degrees of freedom. This leads to significant differences in their construction technologies.

In this section, the physical construction of 3D-MIDs will be compared to PCBs to derive how the increased requirements profile of MIDs influences the basic function of contacting electrical components. Figure 5-2 shows the sub-technologies that are involved in this comparison.

Integration of spatial and electrical functions 107

Figure 5-2: Overview of investigated sub-technologies for the comparison of 3D-MID and PCB construction

5.2.1. Substrate technology

Printed Circuit Board technology

The main tasks of substrate materials in printed circuit board technology are to provide electrical isolation and mechanical support to the components and to the copper traces located on the inner- and outer-layers of the PCB. A wide range of substrate materials has been developed in the past to meet application-specific requirements concerning mechanical stability, temperature range as well as material costs.

Typical representatives can be classified according to their variances:

Rigid printed circuit boards can be found as impregnated paper substrates, such as FR-2, serving as low-end solutions for cost-critical applications with low power density caused by a single copper layer and reduced requirements concerning stability. Fibre-glass reinforced substrates with the most common PCB substrate: FR-4 achieve a much higher flexural strength and allow the multi-layer stacking of thin copper layers, but at the expense of increased system costs.

Flexible printed circuit boards are used in applications with increased spatial requirements. The demand on complex designs on the one hand and the lack of constructed space on the other hand have evolved substrate materials that are completely or partially flexible. Polyester-film substrates are used in low-cost applications, whereas polyimide-film substrate materials allow increased flexibility, lower bending radii and dynamic stress capability at higher material costs. The drawback of flexible substrate materials, however, is that they require additional supporting structures as they do not keep in shape themselves.

An extensive treatment of available PCB substrate technology is given in [Jo07].

3D-Moulded Interconnect Device technology

As with the PCB technology, the substrate material of 3D-MIDs is utilized to create mechanical stability in the circuit carrier and to provide electrical isolation between the copper traces. Moreover, the thermoplastic polymers can be spatially arranged by means of the injection moulding process, leading to a higher variance in design and functionality compared to printed circuit boards, introduced in Chapter 2.

Substrate technology

Circuit layout production

Interconnection technology

108 Chapter 5

In analogy to PCB substrates, a variety of technical polymers has been developed during the past years [Fe04] to fulfil a broad range of application-dependent requirements concerning mechanical stability, temperature range and material costs.

These fundamental features will be addressed shortly in the following:

Mechanical stability: A variety of fibre-glass reinforced polymers has been developed that are compatible to the LDS process and allow increased mechanical stability compared to conventional polymers without fibre-glass fillers. The resultant flexural strength of typical MID substrates is therefore ranged from 50 MPa – for standard materials – to 170 MPa for fibre-glass reinforced substrates [Mi09], [Ti07], [LA11], [RT08]. Sturdy 3D shapes are therefore possible without any supporting structure.

Thermal stability: Due to the variety of thermoplastic materials usable in the LDS process, a wide temperature range can be covered with 3D-MIDs. Whilst low-cost materials, like standard PC-ABS, show a deflexion temperature of about 100°C [LA11], high temperature compatible substrates, e.g. thermally stabilized polyamides 6/6T exist, which can be operated up to temperatures of 265°C [DS07]. Therefore, high temperature applications, e.g. near the automotive combustion engine, and lead-free soldering are possible. However, the thermoplastic substrate materials show higher coefficients of thermal expansion, which has to be considered for robust design when different CTEs appear. Different industrial research projects are planned to reduce the CTEs of 3D-MID substrates and to create homogeneous CTEs independent of the filler orientation [HF11].

Electrical isolation: 3D-MID LDS thermoplastic materials are inherently electrical isolators. This behaviour is not changed with the additional material doping of LDS filler materials. Hence, typical electrical isolation characteristics of conventional polymers are still maintained, which show dielectric constants as well as loss tangents comparable to printed circuit boards made of FR-4. The isolation resistances are even higher than for typical FR-2 or FR-4 substrates [DS07], [Na12].

Table 5-1 gives a short comparison of two typical LDS-compatible substrates and conventional FR-4. The 3D-MID materials are a moderate performance polyamide 4 [DS07] and a more advanced temperature stabilised polyamide 6 Ultramid T4381 LDS [Ba07] to indicate the bandwidth of 3D-MID polymers. An overview of 3D-MID materials compatible with the LDS process is given in [HJB04], [Jo11].


Table 5-1: Comparison of selected material parameters of 3D-MID und PCB substrates: PA6T, PA4T and FR-4 [Ba07], [DS07], [Na12]

Material PA6 T LDS PA-4T FR-4

Mechanical Properties

Flexural strength cw/lw * [MPa] 160 245 345/450

Thermal Properties

Thermal coefficient of expansion in (x- and y-direction) [ppm/°C] 30 - 50 22-35 14 – 18

Glass transition temperature [°C] 295 125 135 - 250

Electrical Properties

Permittivity ε (1 MHz) 4.4 - 4.2 3.9 3.9 - 4.8

Loss tangent (tan δ, 1 MHz) ≤0.038 0.018 ≤ 0.035

Dielectric strength [kV/mm] ≥ 20 ≥ 33 ≥ 20

Electrical surface resistivity [Ω] ≥1∙1016 ≥1∙1015 ≥ 1∙1010

* cw=cross-wise, lw=length-wise

It can be summarized that no major limitations are identified when comparing existing PCB- and 3D-MID substrates in the light of providing mechanical- and thermal-stability as well as electrical isolation. The increased thermal coefficients of expansion of thermoplastic materials, however, have to be considered for robust design. Their influence on creating multilayer 3D-MIDs will be addressed in the following section.

Next to the prior addressed tasks, a variety of substrates is available with the PCB technology that allows adding electrical functionality directly inside the circuit carrier. This contains capacitive, inductive and resistive substrates that are aimed to directly replace discrete components. The ability of 3D-MIDs to integrate functional substrates will be commented in Section 5.3.2.

5.2.2. Circuit artwork assembly


PCBs are assembled as a stack of conductive-, core- and prepreg-layers arranged alternatively and laminated together. The core material has already been discussed in the foregoing section: a dielectric material, e.g. glass-fibre (FR-4), which mainly provides electrical isolation between the electrically conductive layers, is used. Prepreg layers are required in the lamination process to agglomerate the individual sheets with heat and pressure.

The copper layer is made of a pre-manufactured foil which is completely attached to the core surface by utilizing rolling or electro-deposition [Va02]. Different mechanical and chemical production methods exist to create the circuit structure on the copper foils: silk screen printing, photoengraving and PCB milling [Jo07]. All of these processes are subtractive methods that delete copper where it is not necessary.

110 Chapter 5

The printed circuit board technology delivers a wide range of available copper layer thicknesses which are available in standardised processes, e.g. 35μm, 70μm and 105μm.Additional PCB derivatives exist which have a copper layer thickness of several hundred micrometers up to the millimetre range. The latter, so-called high current PCBs, utilize solid copper bars instead of simple copper foils to maintain even higher current values of several hundred ampere [Le11].

It can be summarized that the multi-layer structure of PCBs not only allows complex routing with multiple layers (up to 48 [Ci12]), but also allows a wide range of amperage. Combining layers, carrying the same current, can be additionally used, to allow even lower circuit track resistances and hence increased current values.

3D-Moulded Interconnect Device Technology

In contrast to conventional PCB construction, the circuit layout of LDS 3D-MIDs is not created by a subtractive process but rather by a selective additive copper deposition.

The main production steps of the LDS process are summarised in Figure 5-3. In a first step, a thermoplastic polymer, filled with an organo-metallic complex, is processed in a 1-shot injection moulding process to create the 3D-substrate.

Figure 5-3: Main process steps of Laser-Direct-Structuring technology (3D-MID example: Source: MIDTRONIC)

The injection moulded part is processed in a second production step with a laser beam which roughens the polymer surface and releases the metal atoms from the organic complex. The exposed atoms on the surface can now act as nuclei in the following production step of electroless plating [SRKN02] where the copper precipitation only occurs at the activated surfaces – the circuit tracks.

1. Injection moulding of 3D substrate

2. Laser activationof substrate’s surface

3. Electroless plating4. Optional: electroplating

LEDs

Stiffeners

SMT components

Battery compartment

Casing

Mounting holes

3Dcircuit tracks


Due to the use of the laser system, minimum track widths and distances of ≥150μm and ≥250μm, can be achieved with LDS [LP11b] which allows the contacting of SMT components with low pad spacing.

The achievable copper layer thickness, however, is mainly determined by the electroless plating time. Figure 5-4 visualises the resultant copper layer thickness over the exposure time for chemical copper baths of different activity, as described in the literature [LP11a], [BM07].

Figure 5-4: Copper layer thickness over exposure time for different chemical copper baths derived from [LP11a], [BM07]

It can be seen from the charts in the figure that the copper deposition rate is dependent on the bath-activity with deposition rates of 3-6μm copper per hour. Creating a copper thickness comparable to PCB standard would therefore require exposure times of several hours, when only chemical copper deposition is used. This directly affects substrate costs, as the galvanic expenses are mainly determined by the time the baths are occupied. Another disadvantage is, that chemical copper shows an increased brittleness compared to electrolytic copper [Wi09] with only 0.6-2.2 percent breaking strain for chemical copper compared to 15-45 percent for galvanic copper. Hence, chemically generated copper layers do not exceed 10-15μm in practical applications [Ba07], [LP11b].

There exist two different alternatives to bypass this limitation:

Electroplating: Additional electroplating can be used to increase the copper thickness after initial chemical copper deposition. However, this requires a continuous circuit artwork to minimize the number of electrodes required for contacting. Finally, an additional process is required to modify the continuous “plating layout” to restore the original routing.

Increasing the circuit track width: Another solution to avoid extra plating effort is to maintain the required circuit track ampacity by increasing the circuit track width. The additive layout generation on 3D-MIDs, however, leads to a direct dependency between processing speed and circuit track surface, caused by the laser structuring time. This contrasts with the PCB technology where increased copper area usage does not directly cause increased process times.

00.5

11.5

22.5

33.5

4

5 10 15 20 25 30Cop

per l

ayer

thic

knes

s [μm

]

Exposure time [min]

fast working copper path slow working copper path

[BM07]

[BM07]

112 Chapter 5

However, typical LDS lasers show fast structuring speeds of 4000mm/s [LP11a] and allow a fast layout creation. For example, a sample trace with width wCU=0.58mm,thickness tCu=35μm and 25mm length can be structured in 0.24 seconds when assuming no extra time for component or laser beam movement and at a laser speed of 800mm/s. In comparison, an equivalent trace with tCu=5μm and wCU=4mm – to maintain the same cross section – can be structured in 1.67 seconds. It can be seen that the structuring time is about 7 times higher when compared to the original 35μmlayout which is directly proportional to the copper surface increase. Therefore, excess copper area usage is unwanted for optimised MID assemblies and has to be considered in the circuit routing and system design.

Nevertheless, the extra time for laser activation is significantly lower than the time required for chemical- or electroplating. Hence, increasing the track width is the most attractive solution to increase circuit track ampacity on MIDs, at the cost of prolonged laser time and increased space required circuit trace routing.

Layouting gets further complicated as no multilayer structures are available for practical 3D-MID applications, so far [LHS08]. The lack of lamination techniques and the higher coefficients of thermal expansion, e.g. 30-50 ppm of Ultramid 4381 LDS compared to 14-18ppm of standard FR4 (Table 5-1), highly challenge the creation of multi-layer 3D-MIDs and more research is required before multilayer 3D-MIDs become state of the art [LHS08].

So far, only the front- and backside of the 3D-MID is available for circuit routing. The resulting circuit density is significantly lower compared to multilayer PCBs and is amplified as mainly wide traces have to be used to create the desired ampacity with a minimum production effort.

In addition, the heat spreading performance of the structure will also be negatively influenced. Influences of 3D-MID usage on the routing of power electronics will be discussed in Sections 5.3 and 5.4. Effects on the thermal management of power converters on 3D-MIDs are analysed in Chapter 6.

5.2.3. Via interconnection technology

Electrical interconnection between copper layers is necessary to gain improved flexibility and options in circuit routing and hence component positioning. A short comparison of interconnection technologies available with PCBs and 3D-MIDs will be given in this section.


The electrical interconnection between PCB layers is typically realised with drilled through holes whose inner surfaces are electro-plated. A large variety of these so-called vias has been developed by research and industry to cover a broad range of interconnecting functions. [Jo07] already introduced a comprehensive comparison and explanation of via technologies


available with PCBs, therefore only the resulting improvements due to via technologies will be summarized here in a short way:

Low costs: Conventional through-hole vias allow a very simple signal routing between layers due to drilling and through-hole plating, leading to a low costs interconnection between layers.

High power density: Blind and buried vias are utilized to create interconnections only between the inner layers of PCBs, hence the outer copper layers can be completely used for component positioning and routing [Is98] allowing higher component packaging density.

Small structures: Micro vias have been developed to allow small surface vias in application with low component pad spacing, like microprocessors. Typical diameters below 150μm are created by means of laser-drilling or etching [Ho984], [KK00].

Heat transport: Enhanced heat transport from components to a heat sink or to a cold plate can be achieved by utilizing thermal vias that are directly placed under the component which has to be cooled. Additional metal filling of these vias can be used to create an even lower thermal resistance path through the PCB [BM00], [WN98]. Hence, thermal vias integrate the electrical contracting and heat transfer function in a single component.

The large variety of via types allows solving complex contacting demands, transferring the PCB into a very universal circuit carrier technique with layer numbers up to 48 [Ci12]. Figure 5-5 shows a short overview of vias usable in PCB technology, as discussed in [Jo07].

Figure 5-5: Overview of via interconnection technologies available with PCB technology [Jo07]

3D Moulded Interconnect Device Technology

3D-MIDs do not contain a stack of multiple copper layers, however the front- and backside of the plastic circuit carrier can be used for routing. The availability of through-hole vias can therefore be a significant improvement to allow more complex circuit artwork and improved component cooling with two interconnect able copper layers compared to a single layer without vias.

114 Chapter 5

However, via creation on LDS MIDs cannot be performed my means of mechanical drilling as the resulting via holes do no longer show a surface that can be activated by the laser beam. Two different solutions have therefore been developed in the industry to create vias on 3D-MIDs. Both of them are not as flexible, general available and easy to realise when compared to printed circuit board via technology:

Laser drilled vias: The conventional LDS laser can be utilized to directly drill vias into the substrate material, as the laser drilling causes a direct activation of the resulting via hole surfaces. The integration of via creation into the conventional LDS process chain allows a flexible positioning of vias, only dependent on the laser programming. However, several limitations appear for the practical application of laser drilled vias.

In [Ah06] laser drilling has been investigated for its application with different substrate materials. It is shown, that laser drilling increases the laser structuring time of the MID due to the extra time caused by the drilling scheme. In addition, vias could only be realised on expensive LCP substrate materials, whereas no laser parameters could be found for a successful via realisation on cheaper materials, like PA6/6T and PBT/PET. In addition, only quite thin substrates with a thickness of up to 800μm were processed.

Injection moulded vias: Vias can also be directly realised by the injection moulding process which allows an application to any LDS compatible substrate material. However, via position and geometry must be implemented in the injection moulding tool. Hence, changing any of these parameters requires a cost-intensive modification of tools and conflicts with the idea of flexible layout creation, given by the LDS process. Injection moulded vias are therefore no option for an extensive usage, but rather for occasional connection of front- and backside of 3D-MIDs when inevitable. The excess usage of thermal vias, as in PCBs, is therefore also not possible on 3D-MIDs, which will be addressed further in Chapter 6.

Further limitations appear due to the requirement that the inner surface of the via-holes has to be activated by the laser. The laser-beam is not able to activate faces oriented with an angle of <15° to the centre of the laser axis. Vias therefore have to be cone-shaped to allow structuring without turning the entire 3D-MID (Figure 5-6).

Figure 5-6: Maximum flank angles for successful Laser-Direct-Structuring according to [LP11b]

Figure 5-7 shows an additional comparison of vias in PCBs compared to 3D-MIDs for a better understanding of the via implementation differences. It can be seen from

90°75° 105°

not structable withoutturning the component

allowed flank angles


Figure 5-7 (a) that the conical MID via shape (right) is formed from two sides to reduce the via-diameter at the substrate surface and hence, the space required for the circuit artwork.

Figure 5-7: (a) Comparison of via realisation on PCBs and 3D-MIDs shown as cross section (b) cross-section polish of 3D-MID via with 70° flank angle [Ah06]

It can also be seen from Figure 5-7 that the outer diameter cvia_3D-MID of the 3D-MID vias gets dependent on the substrate thickness tsub caused by the conical shape. The resultant diameter can be calculated according to:

, where ci is defined as via diameter in the middle of the substrate. As a consequence, a significantly lower number of vias can be placed on the same area compared to PCBs. Additionally, the positioning of components is restricted by the fixed via positions.

It can be summarized that the general availability of vias on 3D-MIDs is highly limited in comparison to PCB technology due to increased production efforts. In addition, a high via density is not possible. Hence, power electronics design involving circuit routing and thermal management should be able to reduce the requirement on vias to a minimum on 3D-MIDs.

5.2.4. Summary on 3D-MID vs. PCB construction

The comparison of the 3D-MID technology to state of the art PCB technology shows that various limitations appear due to differences in the circuit carrier construction:

Substrate technology: Only minor limitations are caused by the available 3D-MID substrate materials. A variety of materials is available for MIDs, ranging from low-cost thermoplastics with a limited temperature range and low mechanical stability to sophisticated substrates with improved performance in both domains. The latter allow complex 3D constructions operated at even higher temperatures than PCBs withstand. However, the larger CTEs of polymers have to be considered for applications with large mismatch of CTEs and increased temperature range.

Circuit layout production: First limitations have been identified due to the selective additive generation of 3D-MID circuit tracks as layout production speed is directly proportional to laser time. The chemically-deposited copper layers show significantly lower thickness levels compared to PCBs, which is determined by reliability and cost

(a)

αcvia_3D-MID

ci

dvia

tsub

(b)

116 Chapter 5

issues. For this reason wide circuit tracks are mainly utilized to maintain the desired ampacity, leading to reduced power density and increased space requirement for the circuit artwork.

The lack of layer lamination techniques and increased coefficients of thermal expansion amplify routing challenges because no multilayer-technology can be implemented in 3D-MIDs, so far.

Via interconnection technology: A third limitation is identified in the via interconnection technology, as no mechanical drilling can be utilized for simple via creation as in PCBs. Laser drilling can only be applied to a limited number of substrates with small thickness levels. Vias created by injection moulding cannot be placed in a flexible way and likewise require increased space compared to PCB vias. This directly affects the realisation of the circuit routing and the thermal management.

Figure 5-8 visualises how the identified domains restrict MID layout flexibility when compared to PCBs.

Figure 5-8: Restricted layout flexibility of MIDs when compared to PCBs due to layout generation

Influences of the 3D-MID construction on the routing and component positioning of power electronics on 3D-MIDs will be discussed in the following sections of this chapter. Effects on the thermal management, including heat transport and heat spreading will be analysed in Chapter 6.

substrate technology

copper layer production

multilayer production

vias


5.3. Contacting challenges of components

5.3.1. Current carrying capacity of 3D-MID circuit tracks

The foregoing section has shown that increasing the circuit track width rather than the thickness is to be preferred for realizing traces with larger cross-sections on 3D-MIDs. Stacking of multiple layers is also not available in contrast to printed circuit boards.

Knowledge of the current carrying capacity (CCC) of single layer traces on 3D-MIDs is therefore an essential parameter to determine required circuit track dimensions. Furthermore, CCC modelling is necessary as first indication of power limits set by the 3D-MID technology.

The CCC is defined by the maximum allowed trace heating. It is therefore a function of the heat generated in a copper trace, defined by the resistive losses and the heat transfer to the environment.

The conduction losses in the circuit track are given by:

with I = current flowing through the conductor [A] Rel = resistance of the circuit trace

The dc resistance of the trace is temperature dependent and can be calculated with [Ad04]:

where ρ20 = Specific electrical resistivity [Ω mm²/m] L = Length of conductor [m] tCu = Thickness of conductor [m] wCu = Width of conductor [m] α20 = Linear temperature coefficient [1/K] T = Local temperature of conductor [°C] T20 = 20°C

It has to be noted, that the specific electrical conductivity of chemical copper on 3D-MIDs reaches only 60-70 percent of solid copper [LP11b] leading to increased resistances at same track dimensions and has to be considered for the determination of the CCC. A possible explanation of the reduced conductivity of electroless copper layers could be found in [RR95] which states that the chemical deposition creates a porous structure leading to a reduced effective cross sectional area, and therefore to increased resistance values compared to solid copper.

Current carrying capacity models

Different models and design guidelines exist which describe the CCC of PCB traces in dependency of the circuit track parameters. However, standard design rules, like the out-dated IPC-2221 [IP91], only consider the cross section of traces instead of their aspect ratio: α=wCu/tCu Other important aspects that influence the CCC, like the thermal footprint of the circuit tracks, the cooling conditions, the layer number and trace pitches are neglected; which has been criticized in several publications [Yu02],[Ad04],[YHF09],[CCW08]. A new revision of the old standard is the IPC-2152 guideline, which has been established to give orientation for an increased number of circuit carrier configurations than has been addressed with the

118 Chapter 5

preceding standard. The new experiments cover multilayer structures, different copper and base material thicknesses, as well as two base materials: FR-4 and polyamide [YHF09].

Due to the large aspect ratio of 3D-MID traces and their increased specific resistance, a more accurate model is, however, required to the calculate the allowed current values for given 3D-MID circuit track und substrate configurations.

Different models have been introduced in the literatures that consider the influence of circuit track dimensions and environmental conditions on trace heating. Curve fitting approaches, as in [Br98], were used to model the influence of the trace width and thickness. [Yu02] uses analytical solutions for two-dimensional heat conduction based on Fourier series. The investigations show that the use of the root mean square value of currents is sufficient to model ac transients. This is caused by the relatively large time-constants of circuit board heating. [YHF09] shows that the influence of trace pitches and the use of multiple layers also have a strong impact on the CCC of PCBs, especially in power electronic applications with high power density, but does not present a model that covers the addressed issues.

In [Ad04] different board configurations were simulated, corresponding design charts were given and a simplified analytical mathematical CCC model has been introduced. The heat transfer model considers the physical boundary conditions including substrate and trace geometries as well as the heat flux to the ambient. This allows a comparison between the current carrying capacities of 3D-MID to PCBs traces and is therefore used in this thesis to calculate the CCC of single copper traces on 3D-MIDs. The influence of neighbouring traces is neglected here, as the analysis’ focus is to give a comparison of how the aspect ratio and the conductivity of MID traces influences the CCC compared to PCBs.

The analysis uses a two-dimensional heat transfer model with a single copper trace centred on a square board, as shown in Figure 5-9.

Figure 5-9: Two-dimensional heat transfer model for current carrying capacity calculation

According to the model, the heat transfer from the copper trace and circuit carrier can be calculated by dividing the geometry of Figure 5-9 in two sections, as further described by [Gu98]. Section 1 is the trace area, where the heat is generated due to the conduction losses Pcond. The substrate that is not covered by the trace is defined as Section 2.

Sect

ion

_1 P

[W]

L

B tsub

Sect

ion_

2a

Sect

ion_

2b

wCu

x

y

z

Tambient

RII

Pcond

=

RI


The heat, generated in the trace, is spread in x-direction in the board, where the majority of the total heat transfer to the ambient will be performed for thin traces (w<<B) that only have a low surface area. The model therefore assumes the substrate to act as two-fin heat sink, with fin height B/2, fin length L and fin thickness tsub. Utilising the heat sink equation derived in [KB83], the thermal resistance of the two parallel fins can be written as:

with

where λ = Thermal conductivity [W/m K] h = Heat transfer coefficient [W/m² K] L = Length of conductor [m] B = Width of board [m]

tsub = Thickness of substrate board [m]

The thermal resistance RI from section I to the ambient is defined by the trace surface, as well as the heat transfer coefficient h:

, where the factor ½ is used, as RI represents the parallel connection of the trace thermal resistance and the thermal image of the trace’s footprint on the backside of the board.

The total thermal resistance Rtot of the circuit carrier to the ambient is then approximately:

The resulting trace temperature rise ΔTtrace can then be calculated by:

Δ

Solving (5.3.1) for I, with Pconduction and Rtot, defined in (5.3.6), (5.3.7), the maximum allowed trace current can be calculated for a given trace temperature Tmax:

with Tmax = Tambient + ΔTtrace

where ΔTtrace = Specified temperature increase of trace [K]

The influence of the conductor geometry on the current carrying capabilities has beencalculated by means of equation (5.3.8) for 3D-MID and PCB traces. Figure 5-10 shows the boundary conditions and assumptions made for the calculations.

120 Chapter 5

Figure 5-10: Definition of parameters used in CCC calculation

The calculation assumes a single conductor system on the rectangular substrate board of Figure 5-10. Besides a temperature rise of 40K was allowed. In addition, the temperature-dependency of the heat transfer coefficient h has been neglected for simplicity and was calculated to be h=5 W/m²K. The calculation of h has been performed according to [Re01] by assuming a vertical oriented plate of dimensions L=150mm, B=40mm at an ambient temperature of Tambient=60°C. The plate width B has been calculated sufficiently large that no restrictions in heat spreading appear.

In Figure 5-11, the calculated maximum current values are plotted over the conductor width and for different trace thicknesses. The solid lines show the calculated values for the 3D-MID traces, whereas the pointed lines represent the values for the PCB structures.

Figure 5-11: Calculated maximum trace current I over trace width for allowed temperature rise of 40K

It can be derived from the charts that, e.g. a conductor width of about 1.5mm is required for a 10μm copper layer to maintain a CCC of 2A on 3D-MID. A PCB trace with the same geometry, in contrast, is able to carry a current of about 2.6A. This is mainly determined by the higher specific resistivity of the 3D-MID traces compared to standard PCB copper. A further decrease of the trace thickness increases the demand on wide traces to maintain the

wCutsub =1.5mm

ρ20_Cu_PCB ρ20_Cu_MID

h=5W/m²K

I

λPCB=0.25W/mKλ MID=0.28W/mK

Radiation neglected: εr=0

0

1

2

3

4

5

6

7

8

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Max

imum

cur

rent

I [A

]

Trace width w [mm]

PCB 35um copper PCB 10um copper PCB 5um copper

MID 35um copper MID 10um copper MID 5um copper


same CCC, e.g. 5μm thin tracks require a width of 2.8mm which corresponds to an increase of occupied space by 87 percent.

Results obtained from the foregoing analytical model have been compared to thermal-electrical FEM analyses configured with the same problem arrangement to verify calculations. Results of the comparison are shown in Figure 5-12. Here, the temperature increase of prior structures has been simulated with a dc current excitation of I=2A. The simulations were performed utilizing the electrical conductivity of PCB copper: .

The results calculated with the analytical model are plotted as solid and dashed lines for the MID and the PCB structures, respectively. Numerical results obtained from the FEM analyses are shown as discrete points with black outline. It can be seen, that the utilized analytical model fits the results of the FEM analyses very well.

Figure 5-12: Comparison temperature rise over traced width of analytical model to FEM simulation

In addition, 3D-MIDs substrates have been built and tested to prove the accuracy of the simplified analytical CCC model. Figure 5-13, shows an excerpt of the test board used, where different conductor trace widths have been applied to a planar MID substrate by means of the LDS process. Trace- and substrate parameters are given in the figure.

Figure 5-13: Test board for CCC model comparison

0

10

20

30

40

50

60

70

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Tem

pera

ture

ris

e ΔT

[°C

]

Trace width w [mm]

PCB 35um copper PCB 10um copper PCB 5um copper

MID 35um copper MID 10um copper MID 5um copper

PCB 35um copper (FEM) PCB 10um copper (FEM) PCB 5um copper (FEM)

Substrate Ultramid LDS 4381 T [BA07]

tsub [mm] 2

tcu [μm] 15

wcu [mm] 2.3 1.2 0.8 0.6 0.4

lcu [mm] 50

122 Chapter 5

A dc current of 2A has been applied to each trace and resulting temperatures have been measured. Figure 5-14 shows thermal images of the traces with wCu_1=2.3mm and wCu_2=1.2mm with natural convection applied. A maximum temperature increase of ΔT1=18Kand ΔT2=40K has been measured. The values are in close correlation to those calculated with the analytical CCC model. The analysis predicts temperature increases of ΔT1_calculated=21K and ΔT2_calculated=42.5K for the given input parameters.

Figure 5-14: IR measurement: single trace heating on 3D-MID substrate wCu_1=2.3mm (left) and wCu_2=1.2mm (right) @ 2A dc current excitation

The simplified model is therefore a first option in the initial design phase of power converters to compare the current carrying capabilities of 3D-MIDs to PCBs. It can be furthermore used to derive how trace dimensions, and hence routing space, are affected when 3D-MIDs are used.

It has to be noted, that effects caused by narrow trace spacing, as described in [YHF09], have to be determined experimentally or by means of numerical approaches (e.g. FEM analyses) to accurately model the cross coupling of traces.

DC current density distribution

The foregoing sections have shown that increasing the circuit track width can be an option to increase the CCC on 3D-MIDs. However, the current density distribution is also dependent on the geometrical distances, orientation and positions of components that have to be contacted.

Figure 5-15 visualises this in an exemplary current density simulation (FEM Maxwell 3D [AN12a]) on four conductor geometries with the same cross section but different aspect ratios.

Figure 5-15: Influence of component position and trace width on dc current density distribution in circuit tracks

1.5E+8

8.3E+7

1.5E+7

J [A/m²] (a) (b) (c) (d)

35μm Cu 10μm Cu 5μm Cu 5μm Cu


A current of 3.5A is applied to a SMT resistor (package 0805) by using copper thicknesses of 35μm, 10μm and 5μm. In contrast to case (a)-(c), the resistor in (d) is not placed in the middle of the conductor. It can be seen, that the out of centre alignment of the resistor causes current density deviations of up to 50 percent in the surrounding region of the resistor.

In this case, no major deviations in the temperature distribution have been determined with natural convection applied, due to the high thermal conductivity of copper. Similar results are therefore expected in applications with convective cooling of the 3D-MID only, as considered in the concept introduced in Chapter 3. Furthermore, the resulting increases of trace resistances due to the partial use of the cross sectional area is negligible in this case.

Bigger limitations appear when the required trace widths wtrace exceed the pad spacing of components wpad and neighbouring pads carry different signals, because larger regions appear where only narrow traces can be used. Local overheating of traces can therefore be a risk which should be considered. However, the physical boundary conditions, like current density, trace routing, thermal conductivity of traces and substrate as well as the entire thermal pathway will influence possible overheating, as addressed in Section 5.3.1 and [YHF09].

Thermal pathway optimisation and the choice of suitable component packages with improved orientation of contacting pads and optimised pad distribution could be used to reduce local overheating but has to be investigated for the individual application case due to the huge variety of possible combinations. Hence, parametric numerical simulations can be an option to determine an optimised solution for these particular cases when using coupled thermal-electric simulations [AN12b].

5.3.2. Integration potential of passive components with 3D-MIDs

Beyond providing mechanical stability, electrical isolation and component contacting, modern circuit carrier technologies, as PCBs, are able to integrate additional electrical functionality by using enhanced substrate materials. This contains substrates with modified dielectric constants, magnetic permeabilities as well as resistances. Thus, additional electrical functions can be directly realised with the circuit carrier and can be beneficially used to replace discrete components.

A reduction of the number of discrete components that have to be mounted on the 3D-MIDs would be very beneficial, as complex assembly steps performed in three-dimensions could be reduced. The potential of 3D-MIDs to integrate additional electrical functions, i.e. the integration of passive components in the end, is however greatly limited due to the low number of routing layers and low copper layer thickness of 3D-MIDs [TP11], as will be discussed next:

Integrated capacitances are created by the use of two conductive layers that encapsulate a dielectric material, e.g. the MID-substrate. The capacitance value is dependent on the dielectric constant and the substrate dimension. 3D-MID substrates, however, only have low dielectric constants like FR-4 used for PCBs.

124 Chapter 5

In contrast to PCBs, where several dielectrically enhanced substrates exist [Fe02], [WAF05], [Sc08], no improved substrates have yet been derived to be compatible with the LDS technology. The lack of multi layer structures and via limitations further decreases the realisation of significant capacitances on 3D-MIDs, as no parallel connection of multiple capacitive cells is easily achievable. This could be solved with progresses made in the development of enhanced substrate materials with low coefficients of thermal expansions, contributing to the availability of multi-layer 3D-MIDs. Further, the development of materials with enhanced dielectric constants that are still compatible with 3D-MID assembly processes could also greatly increase the potential of 3D-MID integrated capacitances.

Integrated resistances can be realised on PCBs by using resistive substrate materials or additional thin film techniques to create resistors buried between the layers [Jo07], [Sc08]. So far, no successful implementation of usable resistivity in LDS compatible substrates has been reported. A two shot-moulding process of LDS-substrate and resistive polymer might be possible, but greatly increases the manufacturing effort with questionable benefit compared to discrete component use.

Integrated inductances in 3D-MIDs suffer from identical limitations as capacitances and resistances, if an implementation of soft-magnetic layers is considered. The issues could be addressed in a similar manner, as for integrated capacitances when new materials with enhanced magnetic permeability get available which are compatible with 3D-MID substrate technology. In addition, the compatibility of commercially available ferrite polymer composites and of 3D-MID substrate materials for 2-shot injection moulding has not been investigated so far, but could further offer the potential for injection moulded integrated inductances on 3D-MIDs – comparably to the approaches made in [EgFl10]. Today, the simplest form of inductor realisation on 3D-MIDs is to combine standard planar core technology with the 3D-MID technology. As in state of the art PCB-based power converters, the windings can be directly realised as traces on the MID surfaces, whereas the planar core is still attached as discrete component (Figure 5-16).

Figure 5-16: Planar core integration on 3D-MID substrate

The considerably low circuit density of 3-MIDs, caused by the lack of multi-layers and low CCC of traces, allows only low core fill factors which negatively influences the planar core integration on 3D-MIDs. In Appendix B, the realisation possibilities of planar core inductances on 3D-MIDs are further discussed. A comparison of the power

Substrate

Planar core

Integrated 3D-MID windings


losses of MID- and PCB-based planar core inductances as well as discrete SMT inductances is performed, additionally. It accounts the 3D-MID-based planar core integration a very restricted usability for power converter filter inductances.

5.3.3. Circuit trace parasitics

Section 5.3.1 has shown that the low copper layer thickness on 3D-MIDs demands increased trace widths to maintain the same current carrying capacity as on PCBs. Hence, significantly different aspect ratios of conductor cross sections are used on 3D-MIDs. Parameters that might be affected by the changed CCC and aspect ratios are the parasitic

resistance inductance capacitance

of the copper traces on 3D-MIDs.

The influences of 3D-MID trace parameters on trace parasitics will be discussed for simple single conductor geometries under dc as well as ac current excitation, in the following. The results will be compared to PCB equivalents for a better understanding.

Circuit traces with thickness of tCu = 35μm, 10μm and 5μm will be used in the following. The model of Section 5.3.1 is used to determine the trace widths for given current values – the resulting dimensions can directly be seen from Figure 5-11. The calculation of the current carrying capacity has been performed to maintain a temperature rise of ΔT=40K for the copper traces.

DC-resistance

The dc resistances of the different conductor geometries on PCBs and 3D-MIDs can be directly calculated with equations (5.3.1), (5.3.2) and (5.3.8), given in the foregoing section. Figure 5-17 shows the resulting trace resistances per length over the applied current for PCB and MID traces with 35μm, 10μm and 5μm copper thickness. The copper trace width has been adjusted to maintain the same temperature rise ΔTtrace=40K.

126 Chapter 5

Figure 5-17: Calculated trace-resistance per length for different conductor geometries realised on PCB and 3D-MID substrate

The plots show that 3D-MID traces exhibit a higher resistance at same CCC as their PCB counterparts. The reason is the decreased conductivity of 3D-MID traces that demands wider traces which in turn have an increased surface area that helps to improve convective cooling. However, resistive losses are increased. A comparison of the resistances of the 35μm PCB and the 5μm MID traces shows an about 30 percent higher resistance at a given input current of 2.5A.

The increased trace width will also influence the contacting of single components (-pads) as well as routing and layout of complete circuits and will be discussed later in this chapter.

DC-inductance

Different methods exist to determine the dc inductances of simple conductor geometries. The concept of partial inductances introduced by [Ro082] and further developed by [Gr46] helps to derive the inductance of single traces. Adapted analytical equations for rectangular conductors were developed by [Ru725] which allow a fast digital computation with improved accuracy for long and thin conductors and have therefore been used to calculate the self inductances of prior 3D-MID and PCB traces.

The results are shown in Figure 5-18 which visualises the resulting self-inductances per length versus the trace CCC. For this illustration, the copper trace width has been adjusted to maintain the same temperature rise ΔTtrace=40K.

1.355

1.725

0

1

2

3

4

5

6

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Trac

e re

sist

ance

s pe

r le

ngth

[mΩ

/mm

]

Current carrying capacity [A]

PCB 35μm copper PCB 10μm copper PCB 5μm copper

MID 35μm copper MID 10μm copper MID 5μm copper


Figure 5-18: Calculated trace-inductance per length for different conductor geometries realised on PCB and 3D-MID substrate

Comparing the inductance of MID and PCB tracks of the same CCC shows a lower inductance for the prior, due to their increased width compared to the PCB equivalent. A comparison of a typical MID trace with tCu=5μm to its PCB counterpart (tCu=35μm) shows that the MID inductance is reduced to 53 percent of the PCB value when a CCC of 2.5A is desired. However, the footprint of the MID trace is nearly nine times higher.

DC-capacitance

To calculate the DC capacitance of the single conductors a system with ground plane present has been assumed. A closed form analytical model developed by Bogatin [Bo883] is used to calculate the capacitances of the individual trace configurations. The model combines the analytical approaches derived by Wheeler [Wh778] and Schneider [Sc695] and provides accurate capacitance values for the given geometries, as compared by [Bo883].

The same trace dimensions as for the resistance and inductance calculations have been used as input parameters, here. A substrate thickness of tsub=1.55mm and a dielectric constant of εr=4.4 has further been assumed.

Figure 5-19 shows the calculated parasitic capacitances per trace length. The largest capacitance values appear for the widest trace width, as expected from the idea of a simple plate capacitor. For example, a 3.5-times higher capacitance can be identified for the 5μm 3D-MID trace when compared to a state 35μm thick trace realised on a PCB designed for a CCC of 5A.

0

0.2

0.4

0.6

0.8

1

1.2

1.4

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Para

sitic

self

indu

ctan

ce p

er le

ngth

[n

H/m

m]




128 Chapter 5

Figure 5-19: Calculated trace-capacitance per trace length for different conductor geometries realised on PCB and 3D-MID substrate with ground plane

When no ground layer is considered for the single conductor configuration no capacitance can be derived for single traces. Instead, the self-coefficients of potential of the traces can be derived by using the analytical model shown in [Ek01]. It allows the calculation of the partial self- and mutual-coefficients of potentials in single layer substrates. However, the results are not as meaningful as prior visualisation of the parasitic capacitances.

AC-behaviour of 3D-MID traces

The ac resistance of single conductors is influenced by the skin effect which describes the phenomenon that an alternating current causes the current density to be maximum at a conductor’s surface [LM66]. This current density distribution is described with the skin-depth: a material dependent value which represents the penetration depth [Fe941] of the current density in a conductor. The skin depth δ is defined as the distance from the conductor surface to its inside, where the current density is higher than one eth of the surface’s current density [Co10] (with e equals Euler’s number). The skin-depth δ is calculated as follows:

where μ0 = magnetic permeability of vacuum: 4π•10-7 H/m σ = specific electrical conductivity of conductor material [S/m]f = frequency [Hz]

Figure 5-20 visualises how the skin effect influences the current density distribution in a round copper conductor when exposed to a sinusoidal current excitation of different frequencies. The simulations have been performed using FEM modelling with the software Maxwell 2D [AN12a].

0.00

0.02

0.04

0.06

0.08

0.10

0.12

0.14

0.16

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Para

sitic

cap

acita

nce

per

leng

th

[pF/

mm

]





Figure 5-20: Current density distribution in round conductor at different frequencies

The skin depth is not only frequency-dependent, but it is also determined by the specific electrical conductivity σ of the conductor material (Equation (5.3.10)). Consequently, the skin-depth of 3D-MID traces is affected, because chemically-deposited copper tracks have a substantially lower conductivity as the PCB equivalent (Section 5.3.1). Figure 5-21 visualises the calculated skin depth for PCB and MID copper conductivities plotted over a frequency range of 100kHz to 100MHz. It can be seen from the chart that the reduced copper conductivity on 3D-MIDs leads to larger skin-depths in the frequency range of interest for the power converter application, as introduced in Chapter 2.

Figure 5-21: Skin depth calculation for MID and PCB copper traces

Influence of conductor geometry

When the frequency gets increased, the skin depth gets decreased and consequently the ac resistance is increased due to the current flowing through a smaller cross section. This leads to the effect that conductors with the same cross section but different shape and aspect ratios exhibit different current density distributions and hence, ac-resistances. Figure 5-22 visualises this behaviour. Here four different conductor configurations have been simulated at a current frequency of f=10MHz.

f=100kHzf=1 kHzDC f=1 MHz

1.5E+6

5.0E+5

1.5E+5

J [A/m²]

0

50

100

150

200

250

300

1.E+05 1.E+06 1.E+07 1.E+08

Skin

dept

h [μ

m]

Frequency [Hz]

δMID δPCB

Frequency range of interest

130 Chapter 5

Figure 5-22: Current density distribution in conductors of different shape and aspect ratio for excitation frequency of f=10MHz, identical current density scale for all cases

The ac resistances and inductances of rectangular geometries with different aspect ratios are therefore not simple to calculate analytically. Adapted numerical solutions have therefore been developed in the past to determine circuit-trace- and component-parasitics of arbitrarily shaped configurations. [Ek03], [BSS072] give an overview of usable simulation techniques.

The method of Partial Elements Equivalent Circuit (PEEC) [Ru743] modelling is used in this thesis to model the influence of the skin-effect on the high frequency impedances of circuit tracks on 3D-MIDs and PCBs. The software FastHenry [KSW96] is used here, which has been developed by the Massachusetts Institute of Technology (M.I.T) for the solution of Maxwell integral equations and for the fast calculation of parasitic inductance and resistances of components and interconnection structures. Many scientific publications have been presented by the developers and researchers contributing to the software, allowing a high transparency and quality of the equations and models used in the software [MI12]. Furthermore, fast simulation speeds are achieved with the PEEC approach compared to FEM simulations, which also demands complex modelling of the boundary region for correct simulation.

PEEC modelling of ac resistance and ac inductance of single 3D-MID traces

Different circuit track configurations have been investigated to derive differences in the ac impedances of 3D-MID circuit traces and their PCB counterparts. Circuit track dimensions to maintain a CCC of 2.5A at a temperature rise ΔT=40K were used to investigate the influence of the trace geometries on the ac resistance and inductances for a frequency range of 200kHzto 2MHz. This span was selected as it contains the fundamental as well as the first harmonics of the switching frequency of contemporary and investigated power converters for LED-lighting systems, shown in Chapters 2 and 4. The trace dimensions have been calculated by means of the analytical model presented in Section 5.3.1. A sufficiently low filament size has been used in the simulation for a proper modelling of the skin-effect in the desired frequency

Conductor dimensionsCase (a) (b) (c) (d)

Radius[μm]

82 - - -

Height[μm]

- 145 70 35

Width[μm]

145 300 600

Crosssection[mm²]

0.021

(a) round

(d) thin rectangular

(b) square

(c) thick rectangular


range. In addition, segmentation was performed dependent on the skin-depth for improved modelling accuracy and computation speed [KSW96].

Results of the PEEC simulations are shown in Figure 5-23 for single copper traces on 3D-MIDs. The circuit track dimensions are given in the legend of the diagrams. The charts show the resistances and inductances normalized to their dc values plotted over the excitation frequency.

Figure 5-23: Frequency dependence of parasitic resistance and inductance for single traces on 3D-MID –different aspect ratios and CCC of I=2.5A

It can be seen from the charts that the influence of the skin-effect on the ac resistance and inductance of the investigated traces is sufficiently small to be neglected in the frequency range of interest. The maximum deviation of the ac resistances from the dc values can be found for the trace with the largest copper thickness tCu=35μm and is still below 10 percent at a frequency of f=2MHz.

Influence of ground plane

A further aspect that has to be considered when determining the ac-resistance and -inductances of circuit traces is the influence of a present ground plane. 3D-MIDs are often designed without a ground plane due to production constraints, as laser time would be greatly increased. In addition, the backside of MIDs is not always available for the circuit grounding, e.g. when the MID is used as circuit carrier and component housing.

The influence of a conductive plane on circuit loop inductances has been investigated in [Sc953] and has shown that a conductive plane – e.g. copper layer on the backside or a heat sink – can lead to a reduction of the loop inductances at higher frequencies. The effect is dependent on the distance from the trace to the plane, the plane dimensions compared to the trace and on the thickness of the conductive plane.

Hence, comparative PEEC simulations have been performed to compare the frequency dependent trace inductances of system with and without ground plane. Figure 5-24 shows the resulting trace resistances and inductances for a sample geometry with: tCu=5um, wCu=4.2mm,lCu = 30mm plotted versus the frequency. The ground plane has a dimension of 40 x 30 x 0.005mm and can be considered to be infinitely large compared to the trace,

1

1.1

1.2

1.3

1.4

1.5

1.E+05 1.E+06 1.E+07 1.E+08

Nor

mal

ized

res

ista

nce

Rac

/Rdc

Frequency in Hz

w=0.75mm h=35um w=2.3mm h=10um w=4.2mm h=5um

Trace dimensions for I=2.5A

wCu=0.75mm tCu= 35μm


wCu=4.2mm tCu= 5μm

0.960

0.965

0.970

0.975

0.980

0.985

0.990

0.995

1.000

1.E+05 1.E+06 1.E+07 1.E+08

Nor

mal

ized

indu

ctan

ce L

ac/L

dcFrequency in Hz

w=0.75mm h=35um w=2.3mm h=10um w=4.2mm h=5um

Trace dimensions for I=2.5A

Frequencyrange of interest



wCu=4.2mm tCu= 5μm


132 Chapter 5

considering the results shown in [Sc953]. The ground plane is located at a distance of 1mm to the trace, corresponding to a typical substrate thickness of 3D-MIDs.

Figure 5-24: Influence of ground plane on frequency dependent resistance and inductance for test structure derived from PEEC simulation

As expected from the results in [Sc953], a clear influence of the ground plane on the ac inductance has been determined, shown in Figure 5-24 (right). In contrast to this, the single layer MID shows nearly constant trace-inductances over the investigated frequency range. Hence, the dc values will be used in the following sections for the determination of parasitics in the converter layouts.

It can be summarised that increased inductances have to be considered in the design of power converters on single layer 3D-MIDs. Especially, the layout of the converter’s power loop requires low parasitic inductances for improved switching behaviour. Their influence on the electrical performance of power converters on 3D-MIDs will be discussed in Section 5.4.

0102030405060708090

100

1.E+04 1.E+05 1.E+06 1.E+07 1.E+08Free

quen

cyde

pend

entr

esist

ance

[mΩ

]

Frequency [Hz]with ground-plane without ground-plane


10

15

20

1.E+04 1.E+05 1.E+06 1.E+07 1.E+08Freq

uenc

y de

pend

ent i

nduc

tanc

e [n

H]

Frequency [Hz]

with ground-plane without ground-plane



5.4. Spatial- and electrical performance of 3D-MID-based power converters

It has been shown in Section 5.2.2 and 5.3.1 that increasing the circuit track width is the simplest approach to maintain a higher current carrying capacity on 3D-MIDs. However, these wide structures influence the spatial arrangement and electrical performance of power electronics as larger component distanced might be required and, hence parasitic layout inductances will be increased. The influence on both domains will be addressed in this section by means of case study power converters.

Figure 5-25: Overview routing of multi component systems on (quasi-) planar 3D-MID surfaces

In a first step, a compact circuit layout with low component count is investigated on an unoccupied 3D-MID surface, i.e. no obstacles exist for component placing, like the doublesided spatial configuration in Chapter 3. The aim is to determine whether spatial and electrical limitations arise already when power converters with simple complexity are realised on 3D-MIDs. Comparisons to single layer PCBs will be performed, additionally.

In a second step, the compact MID layouts are modified by adding extra parasitic inductances to determine the converter performances in applications with more restrictions on the positioning of power electronic components, as shown with the single sided spatial configuration (Chapter 3). Routing challenges will be addressed and limitations set by the maximum process able currents for proper power converter operation will be investigated.

In both cases switching transients, signal quality and converter efficiency will be determined in dependency of the power converter parasitic inductances.

5.4.1. Case study introduction

A power converter switching cell will be used in the following as case study to identify spatial- and electrical-influences that arise in the realisation of power-converters on 3D-MIDs.

The idea of the case study is to realise identical power converters on planar substrates with different copper layer thicknesses, whilst the circuit track width is adjusted to maintain the

(quasi-) planar surfaces usable for routing of (power) electronics

134 Chapter 5

same CCC. Completely unoccupied 3D-MID surfaces are provided for routing to prove how compact a power converter can be realised on single layer 3D-MIDs and how changed trace dimensions, and hence parasitics, will influence power converter performance. This scenario corresponds to the double sided spatial configuration introduced in Chapter 3: the power converter and the LEDs are realised on opposite sides of the substrate.

The circuit complexity is chosen as simple as possible, to derive the optimum performance of power converters on 3D-MIDs and to compare those layouts to PCB counterparts.

Power converter topology

A simple, single switch boost converter is used in the case study. Figure 5-26 shows the circuit schematic and the relevant components considered in the comparison. The layout contains the input filters, the power converter switching cell and the power MOSFET driver circuit.

Figure 5-26: Boost converter schematic as utilized for the case study comparison

In total, eight components are required for the case study converter. Discrete SMT components are used in the case study to create a use-case where several numbers of components have to be attached to a 3D-MID. This also allows a high flexibility in the component choice when compared to a solution with fully integrated circuits (ICs). Further, a distributed layout can be used to obtain a homogeneous loss distribution over the entire layout when compared to an IC-based solution. Nevertheless, an integrated solution can be beneficial for application on 3D-MIDs when IC-contacting is uncritical.

Table 5-2 summarises the converter’s component values as well as their related packages.Table 5-2: Components used for case study converter

Passives Semiconductors

Component Value Package Component Type Package

Cin 10μF/ 25V 0805 Q FDS5680 [Vi08] SO-8

Cout 4.7μF/ 50V 1206 Dr MCP1407 [Mi12] SO-8

Cb 4.7μF/ 25V 0805 D STPS2L60 [ST11] SMA

L 10μH IHLP 2020 [Vi12]

Rgate 1Ω 0805 / 2010

L

DQDr

Rgate

Cin Cout

Cb


Case study assumptions and realisation

It was previously shown that a single layer 3D-MID is beneficial from a manufacturing point of view (Section 5.2.4). The case study circuit layout is consequently based on a single copper layer without vias to minimize the layout’s footprint and to maintain a high flexibility concerning layout changes, as the entire circuit artwork can be realised with the laser beam only.

Four layouts with different copper layer configurations have been assembled to identify the influence of increased trace width on the layout as well as the spatial- and electrical-performance of the case study converters.

The following assumptions are made for the layout generation:

The focus is on the power cell’s layout in the following sections, therefore the layout containing the driver (Dr) and its peripheral components (Rgate, Cb) are only shown for reasons of clarity in Figure 5-26 and Figure 5-27. They won’t be shown in the subsequent figures.

The trace widths are determined with the equations introduced in Section 5.3.1. They are calculated to maintain a CCC of 2.5A at a temperature rise of ΔT=40K in each trace for reasons of simplicity

The minimum trace width is given by the CCC calculation, however larger widths are implemented when inevitable due to component positioning

The layouts are designed for minimum component distances

Figure 5-27 shows the origin layout; it uses a single layer PCB with a copper layer thickness of tCu=35μm. A trace width of wCu=0.5mm is determined for the PCB configuration. This leads to an aspect ratio (aCu=wCu/tCu) of about 14. The resultant circuit artwork, as well as the component positions can also be derived from Figure 5-27.

Figure 5-27: (a) 35μmCu_min layout, (b) arrangement of components and (c) complete circuit

On the basis of the initial setup, three additional layouts were created with different copper trace aspect ratios:

Layout 2 is also designed for a copper thickness of tCu=35μm, but the trace width has been increased to fill the free space between the components. This layout represents a

(a)

L

D

Q

CbCin

Dr

RgateCout

(b) (c)

136 Chapter 5

realistic implementation of a power converter, as trace inductances and resistances are decreased to a minimum without negatively changing the optimum component position. The layout is named as 35μmCu_max in the following.The remaining two layouts have been designed for copper layer thicknesses of 10μmand 5μm. In addition, the reduced electrical conductivity of chemical copper on 3D-MIDs was considered for the calculation of the required trace width (Section 5.3.1). The layouts will be abbreviated with 10μmCu and 5μmCu.

Figure 5-28 gives an overview of the four resulting case study layouts – without driver sections –shown from the top perspective without components attached.

Figure 5-28: Overview of used case study layouts and nomenclature defining the copper areas

It can be seen from the line-up that a significantly larger footprint area is required to maintain the same CCC for the 3D-MID layout 5μmCu when compared to the 35μm PCB layouts. The occupied footprint areas equate to 180mm² for the PCB layout and 430mm² for the 5μmCu

3D-MID layout.

In the following section, influences of the different aspect ratios on the geometrical and spatial design of the switching cell layouts will be discussed. Effects on circuit trace parasitic inductances and on the electrical performance of the converters are presented in Section 5.4.3.

5.4.2. Spatial performance

Copper area consumption

Figure 5-29 gives a detailed overview of the resulting copper area sizes in the four different layouts, broken down to the individual contacting surfaces. The definitions of the copper areas: IN, Drain, Diode and GND are shown in Figure 5-28 and are identically used for all four layouts.

5μmCu

IN

Drain

Diode

GND

35μmCu_min 10μmCu35μmCu_max


Figure 5-29: Absolute comparison of copper areas required in the four case study layouts

It is not surprising that the 35μmCu_min structure shows the lowest copper area demand, whereas the 5μm layout demands the largest surfaces. The 10μm circuit artwork can be found in between.

The copper area size can be used as a indication for the laser structuring time, as the process time can be estimated as linearly dependent on the floor space required (Section 5.2.2).Increased process times for laser activation of factor 2.5-5.7 can be calculated when comparing the 5μmCu layout with the 35μmCu_max and 35μmCu_min, respectively. This estimation assumes that additional time for component- and laser-movement can be neglected for the case study dimensions.

Component distances

The increased trace width on 3D-MIDs will also influence the distances between the individual components, as more space is required, and gets amplified by routing on a single layer only. Power converters, however, have sensitive sections that should be realised as compact as possible to achieve improved switching performance. This issue is mainly related to the power converter switching loop, which is required to have as low parasitic inductances as possible, demanding low copper trace lengths in the layout [Me08], [Ba06].

Two factors that influence the component distances on 3D-MIDs have been identified during the realisation of the case study layouts: the trace width and the jumper components that have to be placed to solve signal crossings. Both aspects can be identified in the 5μmCu layout and are visualised in Figure 5-30 (a).

0

20

40

60

80

100

120

IN Drain Diode GND

Cop

per

area

[m

m²]

Copper Surface

35um Cumin 35um Cu_max 10um Cu 5um Cu

138 Chapter 5

Figure 5-30: (a) Component position of 5μmCu layout, (b) comparison of relative component position of 5μmCu layout compared to 35μmCu equivalent

It can be seen from the layout that the components are arranged in a way that a good connection of the broad traces to the SMT pads is maintained.

As a consequence of the wide traces, the components cannot be attached closely to each other without violating the demand on equal trace widths for identical CCC. Moreover, a large sized gate resistor Rgate (SMT 2010 package) is required to act as a jumper between gate and driver contacting pads and the ground trace gets ripped up by the resistor pad – indicated in red in the figure. In addition, the output capacitor Co had to be moved outwards of the layout, leading to a increased distance to the MOSFET. Figure 5-30 (b) summarizes the effects in a comparison of the relative component distances between the 5μmCu and the standard PCB layout (35μmCu_Min). The pillars symbolize the distance between the components plotted on the chart’s x- and y-axes. Only one half of the resulting distance chart is shown for a better visibility, as the distances correspond to a symmetrical matrix.

It can be clearly seen from the diagram that the distance between MOSFET Q and the output capacitance Co is increased by roughly 80 percent due to necessity of the previously described jumper usage for the driver connection.

The other component distances are increased in the range of 30 to 40 percent which is caused by the uniformly increased trace widths. These are wider than the component dimensions.

Two main contributors that influence component distances in single layer 3D-MID routing can therefore be summarized:

The trace width exceeds the component width: Increased routing space is required when the trace width exceeds the component size. This effect gets amplified when multiple neighbouring pads have to be connected, depending on the pad configuration.

Jumper components have to be placed: When signal crossings are inevitable, jumpers, e.g. zero ohms SMT resistors, must be used on single layer MIDs to solve signal crossings. When wide traces are used, large jumper packages have to be used to bridge traces, which in turn requires increased space caused by increased component

DQ

CoDr

1

1.25

1.5

1.75

2

DQCoDr

1.4

1.8

1.3

rela

tive

com

pone

nt d

ista

nce

5μmCu

DQ

Co

Required contacting area

(a) (b)

Rgate


footprints. Figure 5-31 visualises the trace width that can be bridged with SMT resistors and furthermore shows their required footprint width, to illustrate the dependency.

Figure 5-31: Usable SMT jumper component for different trace widths and required footprint width of given jumper packages

Both aspects contribute to the fact that the resultant 3D-MID layout is no longer ideal when compared to conventional 35μm PCB layouts. The resultant impact on switching cell loop- and source-inductances, as well as their influence on the converter’s electrical performance will be discussed in Sections 5.4.3 and 5.4.4.

Converter volume and volume utilisation

The change of the component distances will also influence the total space consumption and hence, the converter volume. Here, the converter volume is defined as the circuit footprint area times the converter height. The height is given by the maximum component height – the SMT inductance has a height of hInductance= 3mm [Vi12] – and the substrate has a thickness of tsub=1.5mm.

In contrast to the total volume, the component dimensions will remain the same as identical packages are used. Table 5-3 shows a breakdown of the component-, substrate- and air- volume in the four case study converters. The two 35μm layouts have the same footprint area, because component positions have not changed.

It can be seen that the component volumes Vcomp slightly differ, which is caused by the changed gate resistor package in the 5μm layout (SMT 2010 instead of 0805) required for contacting the MOSFET’s gate.

0

1

2

3

4

5

6

7

8

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Max

imum

cur

rent

I [A

]

Trace width w [mm]

MID 35um copperMID 10um copperMID 5um copper

0603 080512061210 1812 2010 25120603 0805

12061210 1812 2010 2512 0

0.5

1

1.5

2

2.5

3

3.5

0603 0805 1206 1210 1812 2010 2512

Pack

age

wid

th[m

m]

SMD package

140 Chapter 5

Table 5-3: breakdown of converter volume for case study systems

Layout Number of used packages N and

single package volume Vp [mm³]

Volumes

[mm³]

SO-8 SMASMT0805

SMT1206

SMT2010

IHLP2020

Component Vcomp

Substrate Vsub

Air Vair

Total Vtotal

N Vp N Vp N Vp N Vp N Vp N Vp

35μmCu_min

2 27.7 1 32.53

3.1 1 8.20

7.7 1 84

188 371 553 111235μmCu_max

10μmCu 188 452 715 1355

5μmCu 2 1 194 712 1231 2137

A comparison of the converter volumes Vtotal shows a 92 percent higher space requirement for the 5μm layout compared to the 35μm converter. The breakdown of the converter volumes in Figure 5-32 shows that the increase in Vtotal directly leads to more unused air in the power converter, with 57.6 percent for layout 5μmCu compared to 49.8 percent for 35μmCu_Min.

Figure 5-32: Break down of case study converter volume composition

This is reflected in the so-called Relative Volume Utilisation of the converters. The figure of merit has been introduced in PCB-based power converter design and shows how components are packaged into an assembly compared to the assembly volume [Ge05]. The Relative Volume Utilisation is defined as:

where ζ = relative volume utilisation factor Σψcomponent = total component volume in the assembly [m³]ψunused = total unused volume in the assembly [m³] ψtotal_assembly = total assembly volume [m³]

By means of the Relative Volume Utilisation, an indication can be given how the tracethickness affects the power converter design on 3D-MIDs. Furthermore, a comparison to PCB based power converters can be performed.

MOSFET2.5%

Driver2.5%

Diode2.9%

C12060.7%

C08050.3%

C08050.3%

R08050.1%L

7.6%

Substrate 33.3%

Air 49.8%

35μmCu_Min

C0805C08050.3%

R08050.1%L.6%

MOSFET1.3%

Driver1.3%

Diode1.5%

C12060.4%

C08050.1%

C08050.1%

R20100.36%

L3.9%

Substrate 33.3%

Air 57.6%

5μmCu


Figure 5-33 shows the calculated Relative Volume Utilisations of the case study converters. The 35μm layouts achieve a value of about 50 percent. The layouts with increased trace width – representing a 3D-MID realisation – show lower values for the Relative Volume Utilisation, e.g. only 42 percent for layout 5μmCu. It can be derived that the increased trace width suggested for the 3D-MIDs layouts already causes recognisable differences in the converter volume utilisation for very simple circuit layouts. This effect is expected to be even increased with more complex circuit layouts which will be further addressed in the case study 3D LED-lighting system in Chapter 7.

Figure 5-33: Comparison of Relative Volume Utilisation of case study converters

Power converters that can be found in the literature which exhibit a high degree of component- and function-integration show Relative Volume Utilisations of 37.6 to 67 percent [Ge05], [Po05], [Jo07] for the entire power converter, i.e. including EMI-filter, housing and thermal-management.

Summary of spatial influences on power converter realisation

Several spatial differences appear when power converter design is considered on 3D-MIDs instead of conventional PCB design. The main reasons are the low copper layer thickness, the highly limited layer number and the decreased electrical conductivity of copper traces on 3D-MIDs.

The major effects on spatial converter design that have been determined in this work are summarized in the following:

Increased copper trace widths lead to longer laser structuring times and increase the distances between components. The effect is dependent on the required ampacity levels and causes a quite uniform growth of component distances, when all components are operated at the same RMS currents.

When jumper components are inevitable to solve signal crossing, a local increase of component distances of surrounding parts can be observed. The resulting component spacing is mainly determined by the jumper component footprint.

The total volume usage gets increased by wide copper tracks leading to more unused air in the converter which results in a reduced Relative Volume Utilisation.

50.2% 47.2% 42.4%30%

35%

40%

45%

50%

55%

35 10 5

Rel

ativ

e V

olum

e U

tilis

atio

n ς

copper thicknes in μm

142 Chapter 5

The influence of the foregoing spatial demands on the power converter design on 3D-MIDs can be rated according to the considered application:

Applications that have to be constructed as compact as possible are strongly influenced by increased routing space demand. Hence, component density and total system volume will be significantly influenced, as shown with the case study example.

Systems without strict requirement concerning high power density are less influenced by the extra space requirements for routing. A typical example is the target application of 3D LED-lighting systems, when LEDs and power converter are realised on a common circuit carrier. Here, optical functions and lamp design define the circuit carrier’s size, as introduced in Chapters 1 and 2.

It has to be noted that the comparison above has been performed for two-dimensional substrate areas without utilising extra 3D routing surfaces applicable with the 3D-MID technology. Solutions to improve routing by using the option to shape the substrate material in three dimensions will be given in Section 5.5.

5.4.3. Electrical performance

Circuit track parasitic –resistances, -inductances and -capacitances are defined by the copper trace geometry, material properties of the conductive plane, layer configuration and the presence of dielectric material.

The parasitics are therefore dependent on the physical converter layout and they can negatively influence the power converter performance [Sc953], [Me08], [ZBB10], [Xi04]. This contains the switching transients, waveform quality and in general the EMC. Especially, the power converter switching cell is prone to influences of parasitic inductances and its layout should be properly designed to achieve an optimised switching behaviour with fast switching time and low overvoltage, as addressed in a several publications [Xi04], [Ba06].

Section 5.3 has shown that increasing the circuit track width is the most flexible and cost effective option to maintain sufficiently high current carrying capabilities on 3D-MIDs. However, it has also been shown, that this measure will increase the layout footprint leading to larger component distances and therefore to increased circuit track lengths. As a consequence, circuit track parasitic resistances, -inductances and -capacitances will be influenced in dependency of the available copper layer thickness on 3D-MIDs.

This section will be used to determine how the electrical performance of power converters gets influenced by changed parasitics due to a 3D-MID realisation. Limitations defined by parasitics, containing converter efficiency and waveform quality, will be derived.

Static- and dynamic-losses determined by conduction and switching processes will be considered. The waveform quality will be rated by evaluating the power converter switching waveforms. This contains overvoltage and voltage ringing.


The circuit track parasitics will be extracted from the case study layouts, whereas static and dynamic losses will be determined by calculation, simulation and practical measurement.

Parasitic resistances

Figure 5-34 (a) shows the 10μm copper layout without the gate driver circuit. The corresponding circuit schematic is shown in (b), whereas the resistances R1 to R6 are inserted to represent the parasitic trace resistances of the layout. The values can be determined by means of numerical methods for complex structures or with analytical equations for simple structures, as previously discussed.

In this case, PEEC modelling was used again to derive the layout resistances of the four case study converters.

Figure 5-34: (a) Example case study layout with symbolic components and (b) corresponding circuit schematic with parasitic resistances

Figure 5-35 summarizes the resulting resistances of the different variants. The power converter loop resistance and the total trace resistances are shown as extra pillars for reasons of comparison. The specific conductivity of copper was adjusted for the MID layouts 10μmCu and 5μmCu.

Figure 5-35: Parasitic trace resistances of case study converters derived by PEEC modelling

It can be seen from the charts, that there is a relatively uniform increase in the trace resistances between the different layouts, as expected from the results on component distances

Lin

D Q

Cin

Co

Q

Lin R3

R5

Co

R4DR2R1

Cin

R6

(a) (b)

0

10

20

30

40

50

60

R1 R2 R3 R4 R5 R6 Rloop Rtotal

Res

ista

nce

[mΩ

]

PCB 35um Cu Min PCB 35um Cu MaxMID 10um Cu MID 5um Cu

35μmCu_max

10μmCu 5μmCu

35μmCu_min

144 Chapter 5

and copper surfaces (Figure 5-29 - Figure 5-33). In addition, the selective influence of the gate drive resistor connection is also clearly visible in the 5μm layout. It leads to a disproportional increase of resistance of R5 and of the loop resistance Rloop, consequently. The influence of the increased trace resistances on the converter losses and on the efficiency of the systems will be discussed later in this section.

Parasitic capacitances

As no ground layer is used in the case study layouts, only minimal parasitic layout capacitances are expected. The capacitances have been derived in analogy to the resistance extraction by means of PEEC modelling. Figure 5-36 shows the parasitic layout capacitances (Cpi) between the individual copper layers and further gives a comparison of the total capacitances in the case study layouts. As expected, only small capacitances appear in the layouts. For reasons of comparison, layout capacitances have also been calculated for identical layouts but with a ground plane present. It can be seen, that the 5μmCu layout shows the highest parasitic capacitance determined by the large copper surface required to achieve the desired ampacity.

Figure 5-36: Parasitic capacitances of case study converters with and without ground-plane derived from PEEC modelling

Parasitic inductances

The influence on the parasitic layout-inductances can be determined in a similar manner as for the layout-resistances and -capacitances. The parasitic inductances are decisive for the switching behaviour of the power converter. In the following, the switching cell will therefore be focused for the parasitic extraction and for the comparison of the layouts.

Figure 5-37 shows the switching cell schematic with gate drive circuit and the parasitic layout-inductances added. The power loop inductance formed by the copper traces is defined as: Lloop=Ld1+Ld3+Ld4 and Ls1. The latter represents the common source inductance shared by the power- and gate loop of the structure [ZBB10].

0

1

2

3

4

5

6

Total capacitance without GND plane Total Capacitance with GND plane

Cap

acita

nce

[pF]

35um Cu Min 35um Cu Max 10um Cu 5um Cu35μmCu_max 10μmCu 5μmCu35μmCu_min

Q

Lin

Co

D

Cin Cp1

Cp2

Cp3

Cp4

Cp5

Cp6


Figure 5-37: Switching cell schematic with the parasitic inductances included

In addition, the component lead inductances of the MOSFET Q and of the free-wheeling diode D are visualised, as these parameters also contribute to the power loop and source inductance. The effective layout inductances have been derived from the foregoing PEEC models and are presented in Figure 5-38. The complete inductance matrices of the case studies containing the self- and mutual-inductance are presented in Appendix B.

Figure 5-38: Effective parasitic inductances in the power loop

It can be seen from the charts that the 35μmCu_min and 35μmCu_max layout define the cases with the highest and lowest loop inductance. This is caused by the low trace width for the prior and by the wide circuit tracks at 35μm copper thickness for the latter. The 10μm layout shows only a slight increase in the parasitic inductance as the trace width and hence, component distances are only slightly changed when compared to layout 35μmCu_max. The significantly lower trace thickness, however, shows no strong influence on the inductance values, as previously described in Section 5.3.3.

Layout 5μmCu shows the second largest loop inductance which is mainly caused by the longer copper traces required for contacting. All inductances are increased in comparison to layouts 35μmCu_max and 10μmCu. The largest inductance value can be identified in Ld4, which is again caused by the large gate resistor, required to connect the driver with the MOSFET’s gate (Figure 5-30).

VinQ

Vg

Lin Ld1

LD2

Ld3

Ld4 Rloop

Ls1

RgCo

LA LK

D

Cin

012345678

Ld4 Ld3 Ld1 Lloop

Indu

ctan

ce[n

H]

35um Cu Min 35um Cu Max 10um Cu 5um Cu35μmCu_max 10μmCu 5μmCu35μmCu_min

146 Chapter 5

A total trace loop inductance of 4.8nH has been determined for layout 5μmCu which corresponds to an increase of 33 percent compared to the state of the art PCB layout 35μmCu_max that shows only 3.6nH.

The component packaging inductances add further inductance to the power loop. Their package parasitic inductances, caused by lead- and bond-wires are shown in Table 5-4, as derived from typical values given in manufacturer datasheets [Pa03], [Le05].

Table 5-4: Component packaging inductances

Component Package Package inductance [nH]

Component Package Package inductance [nH]

MOSFET Q SO-8Drain: 0.6

Diode D SMAAnode: 1

Source: 1 Cathode: 1

It can be seen, that an additional inductance of 3.6nH is added to the loop inductance by the leads and bonding wires of the semiconductor packages. By taking the extra inductances into account, total loop inductances of 7.2nH (35μmCu_max) and 8.4nH (5μmCu) exist in the layouts. This corresponds to an increase of only 17 percent when comparing the single layer PCB with the 3D-MID layout. Therefore, no significant influence on the loop inductance can be observed, when compared to the increase of copper trace surfaces of up to 150 percent and thus to enlarged component distances of up to 80 percent.

It has to be noted, that when a ground layer would have been used for the PCB layout, parasitic trace inductance would be greatly reduced in contrast to the single layer 3D-MID, as already indicated in Figure 5-24.

Switching performance

Parasitic inductances in the power loop influence the switching transients and consequently converter efficiency and EMI behaviour, as addressed in several publications [Xi04], [Me08],[ZBB10],[Sc953].

In [ZBB10],[Sc953] the influence of the common source inductance on MOSFET switching speed has been investigated and shows that the source inductance mainly determines the turn-off speed of the active switch, and therefore has a significant influence on switching losses. [Yu062] developed analytic models that describe the switching losses dependent of power loop- and source- inductances.

Several papers also address the resultant overvoltages at power-switch turn-on and turn-off for two-switch converters [Xi04],[Me08],[ZBB10],[Sc953], which account the loop inductance for having a significant influence on overvoltages at switching events. Experimental results were generated by [ZBB10] which underline the influence of the loop- and source-inductances on switching performance of the investigated converter cell.


The foregoing results and models will be used in the following sections to investigate the influence of different parasitic inductances on the switching behaviour and efficiency of power converters on 3D-MIDs.

Simulation and experimental verification

Practical measurements and circuit simulation, using Pspice, have been performed to determine the influence of the increased parasitic inductances of 3D-MID layouts and to compare the results to state of the art PCB layouts. The case study converters have been realised as practical prototypes with trace width and circuit parameters according to the foregoing sections. Standard PCB technology with 35μm copper layer thickness has been used due to the better availability of PCBs compared to MIDs and has been utilised as no significant inductance changes are expected due to the change of the conductor thickness for the used configuration.

This assumption has been verified by means of PEEC simulation to compare the inductance differences of identical layout but with different copper layer thickness. For example, the inductances of layout 5μmCu, have been compared to the values obtained for the same layout but realised with 35μm copper instead of 5μm. The simulations show a negligible higher inductance (<1 percent) for the lower copper thickness.

For the investigation of the electrical performance all layouts have been assembled with components from the same production lot and were operated at identical boundary conditions, as presented in Table 5-5. The circuit simulations were performed with identical input values.

Table 5-5: converter operating conditions

Input voltageVin [V]

Switching frequencyfs [kHz]

Gate resistanceRg [Ω]

Duty cycle D

Î [A] VLED [V]

14 300 1 0.43 2 28

Figure 5-39 shows a comparison of the switching behaviour of the different switching cell layouts. The left diagram presents results derived from Pspice simulations whereas the right picture shows the measured waveforms of the prototype converters. In Appendix B, more details on the simulation schematic and its parameters will be given.

148 Chapter 5

Figure 5-39: Comparison of turn-off behaviour of switching cell layouts – left: simulation with 10V/div and 10ns/div times-cale; right: measurement Ch.1-Ch.4: drain source voltage 10V/div, time-scale:

10ns/div

The simulation and the practical measurements show only a small difference in the electrical behaviour of the case study converters. The turn-off time toff stays nearly constant (toff ≈ 9.5ns)because the source inductance is almost not changed among the layouts. Comparing the overvoltages also shows only negligible small differences which could be either caused by the increased loop inductances or by tolerances of the component (parasitic) values. Consequently, no major changes are apparent in the voltage ringing after turn-off and, hence, in the EMI characteristic could be observed.

Power converter efficiency

As the case study converters have identical component values and no change of the switching speed has been observed, no decisive differences in the converter efficiency are expected. Primarily, the resistive losses will be changed due different trace resistances, as has been shown in Figure 5-35.

A comparison of the losses in the case study converters is performed in Appendix B and shows that all converters achieve an efficiency of 93 percent. Figure 5-40 shows a breakdown of the converter losses of the 5μmCu layout and the correspondent thermal image of the converter at nominal input voltage, as an example.

-20

-10

0

10

20

30

40

1.8E-04 1.8E-04 1.8E-04 1.8E-04 1.8E-04Dra

in-S

ourc

e V

olta

ge V

ds [V

]

time [μs]35um Min Cu 10um Min Cu5um Min Cu

10μmCu5μmCu

35μmCu_min


Figure 5-40: Loss breakdown for case study converter: 5μmCu

The diagram shows that about 5 percent of the total converter losses can be addressed to the resistive losses in the copper traces. They are therefore negligible small concerning their influence on the efficiency of the investigated compact case study converters, as shown in Appendix B.

Summary of electrical influences on power converter realisation

The following effects concerning the electrical design and the behaviour of compact 3D-MID-based power converters can be summarized by utilising the results of the case study investigation:

A low circuit complexity contributes to small loop areas, and hence, to reduced parasitic loop inductances, even on wide 3D-MID copper traces used for the case study

Only a small increase in the total loop inductance has been observed due to the increased trace width and trace length as parasitic inductances of component packages remained unchanged and were in the same order of magnitude as the loop inductance

No significant change in the switching behaviour has been observed for the case study systems, as compact layouts with comparably low parasitic inductances were still realisable. Furthermore, only low di/dt appear in the considered application: currents of only 2 amperes are switched in about 8ns

Negligible small changes in the converter efficiencies were observed for the given input parameters due to the possibility to realise compact layouts for all case study layouts supported by the low complexity and unrestricted routing space

It can be concluded, that optimised layouts are possible for power converter cells on 3D-MIDs, when low circuit complexity exists, routing space is available, simple schematics are used and only low di/dt appear in the system.

However, these boundary conditions are not always valid nor even wanted in certain applications, e.g. due to limited routing space or increased power levels. Therefore, systems

Winding losses19%

Core losses28%

MOSFET Conduction

losses1%

MOSFET Switching

losses6%

MOSFET Gate charge

losses13%

Diode28%

Copper Traces

5%

Lin

D Q

Cin

Co

Dr

150 Chapter 5

with increased loop inductances and higher di/dt will be investigated in the following section to prove their feasibility on 3D-MIDs and to determine limitations set by the electrical behaviour of the switching cell.

5.4.4. Estimation of power limits of 3D-MID-based power electronics

Systems with limited space demand higher routing versatility to achieve optimised circuit layouts as those with sufficient space. The foregoing sections, however, have shown that already compact layouts require increased trace lengths when realised on (single) layer 3D-MIDs when compared to PCB counterparts, which is determined by the 3D-MID’s limited routing options.

Limiting factors which obey compact routing on single layer 3D-MIDs are:

Limited routing space: the 3D-MID does not deliver sufficient space for optimised component arrangement and hence routing, e.g. if LED-system and power electronics must be placed on the same side of the MID: the LED positions are fixed due to the optical design. The power electronic components must consequently be placed on the remaining space (Chapter 3 single sided configuration)

Increased circuit complexity: the topology requires an increased number of components or signal traces, leading to increased jumper usage or excess routing on single layer 3D-MIDs, i.e. the trace length will be increased to fulfil contacting demands

Increased copper areas for thermal management: enlarged copper areas are required for improved heat spreading from lossy components, causing increased component distances. The heat spreading performance and resulting space requirements will be treated in detail in Chapter 6.

Non-compact circuit layout

The influence of a non-compact circuit layout on the electrical performance of power converters will be exemplary shown, in the following. Basis is the foregoing switching cell layout: 5μmCu. Identical operating conditions as defined in Section 5.4.1 will be used, but the loop inductance will be increased to simulate routing restrictions of 3D-MIDs.

The non-optimised switching cell layout is achieved by increasing the trace length between the MOSFET’s drain tab and the free-wheeling diode, leading to a change of parasitic inductance Ld1 (Figure 5-37). Table 5-6 summarises the added inductance values and the percentile increase of the total loop inductance.


Table 5-6: Modified switching cell layouts with increased loop inductances

Original layout layout_1 layout_2 layout_3

Inductance increase [nH] +0 +6.5 +25 +50

Percentile increase [%] 0 77 298 595

Figure 5-41 shows the measured MOSFET drain source voltage at switch turn-off for the four layout versions described in Table 5-6. The remaining boundary conditions were kept identical to the earlier measurements on compact layouts, defined in Table 6.

Figure 5-41: Comparison of MOSFET drain source voltage at turn-off for case study layout with additional loop inductance added - Ch.1-Ch.4: drain source voltage 10V/div, time-scale: 10ns/div

It can be seen from the measurements that the turn-off speed remains constant until the output voltage is achieved, as the source inductance has not been changed in the experiments [Me08],[Xi04],[ZBB10]. The change of the loop inductance ΔLloop, however, affects the overvoltage at turn-off and consequently the overvoltage ringing after the switching transient. Figure 5-42 shows the measured and simulated overvoltages at turn-off plotted over the increase of the loop inductances.

Figure 5-42: Comparison of measured and simulated overvoltages at turn-off for different loop inductances

The figure underlines that the practical measurements and simulation values are in close correlation. In addition, large overvoltages of >15V appear in layout_2 and layout_3. Here, loop inductances were increased by factor of 3.5 to 6 compared to the original layout. This

0

5

10

15

20

25

30

0 10 20 30 40 50Res

ultin

gO

verv

olta

geΔV

ds[V

]

Increase of loop inductance ΔLloop [nH]

Measured ΔVds_SPICE_real

Original layout

layout_1 layout_2 layout_3

Overvoltage measured ΔVds_m [V]

7.7 12 17.5 21.5

Overvoltage simulated ΔVds_sim [V]

6.7 11 15.5 21.4

Simulation

152 Chapter 5

corresponds to an increase of only a few centimetres in the power loop length when realised on the 3D-MID. It has to be noted that a current of only 2 amperes is switched off in this comparison.

The measurements and simulations indicate that already low power applications can cause high overvoltages on 3D-MIDs when compact layouts are not possible, leading to increased loop inductances.

Limitations of 3D-MID-based power converters

Like in conventional PCB-based power converters, fast switching speeds amplify the challenge of avoiding high overvoltages when parasitic inductances appear, as determined by the law of induction.

However, both domains are notably affected when power converters are realised on 3D-MID:

Parasitic inductances: 3D-MID-based power converters often show larger loop inductances than PCB-based systems – even when optimum routing space is available, as shown in the previous section. However, when spatial limitations appear, e.g. due to fixed component positioning or enlarged circuit complexity, parasitic inductances get increased due to the strongly limited routing options of 3D-MIDs. Systems without ground-plane are even more affected, because higher parasitic inductances are present when compared to layouts with a ground surface (Section 5.3.3).

Switching speed: High switching speed is required to keep switching losses as low as possible, like in most power converter designs. However, the 3D-MID circuit carrier is not able to transport heat as good as PCBs due to the limited availability of vias and lack on multi-layers, which will be discussed in detail in Chapter 6. Avoidable losses should therefore be reduced to a minimum.

Analytical overvoltage and loss modelling

The foregoing investigations have already shown that the proper determination of evolving layout parasitics can be used to create circuit simulation models that predict the electrical behaviour of prospective circuit layouts on 3D-MIDs very well.

However, maximum values of allowed currents (di/dt) and of parasitic inductances have not yet been given as further orientation. The main limitations that arise in the switching cell performance are given by MOSFET overvoltages and losses during switching transients.

An analytical model that calculates the MOSFET switching behaviour under inductive load and with parasitic inductances present will be used in the following to give an estimation of the electrical limitations of 3D-MID-based power electronics. The results can further be used to judge if a prospective design can be realised on 3D-MIDs when maximum currents and resulting layout parasitics are known.


The model has originally been developed by [Xi04] to describe the turn-on and turn-off switching transients of power MOSFETs at the presence of parasitic inductances. The model considers the loop inductance and the common source inductance to obtain switching losses, voltage overshoot and oscillation caused by switching operations in dc-dc converters. The analysis has also been extensively described by [Me08] and has been further applied to loss calculations of high frequency dc-dc converters.

Figure 5-43 shows the configuration used in the analytical model, which considers the parasitic layout inductances as well as the MOSFET’s parasitic capacitances Cdg, Cgs and Cds.

Figure 5-43: Switching cell schematic with parasitic inductances and MOSFET parasitic capacitances included

In this thesis, only the turn-off behaviour of MOSFETs will be concerned, as the power converter topologies used in this work are operated at DCM, leading to zero-current-switching conditions at MOSFET turn-on. However, the models can be adapted to the switch-on transient.

Details on the switching model implementation, modelling of the MOSFET non-linear parasitic capacitances and component parameters are presented in Appendix B.

Example configuration

An example configuration will be discussed in the following to give an indication of the current limits of single layer 3D-MID-based power converters.

Table 5-7 shows the key input values used in the switching model. Variable loop- and source-inductances have been used to determine overvoltage and turn-off losses at a drain current of 7A. The layout inductances chosen represent typical values observed from power converter realisations on single layer 3D-MIDs, as derived in the foregoing sections.

VinQ

Vg

Lin Ld1Ld2Ld3

Ld4 RloopLs1

Rg Cds

Cdg

Cgs

Co

Rdson

D

154 Chapter 5

Table 5-7: Input parameters used in overvoltage model

Loop inductance

[nH]

Source inductance

[nH]

Gate resistance

[Ω]

MOSFETThreshold voltage

[V]

Loop resistance

[mΩ]

Drain current

[A]

Outputvoltage

[V]

2..30 1..10 1 3.5 150 7 28

Figure 5-44 shows the results of the analytical calculation for the pre-defined input parameters. The charts visualise the expected overvoltages at turn-off and the resultant losses during the switching transient. A switching frequency of fs=300kHz has been used for the loss calculation.

It can be seen from the contrasting that significant overvoltages of 20V already appear at loop inductances of 10nH, if a current of 7A is switched with a source inductance of 2nH present. In turn, fast switching speeds and considerably low switching losses are achieved under these operating conditions.

Figure 5-44: Comparison of overvoltages and switching losses at MOSFET turn-off at increased power level with typical 3D-MID parasitics inductances present

An increase of the source inductance contributes to lower switching speeds and therefore to lower overvoltages at turn-off, but significantly increases the switching losses, as given in the charts.

It has to be noted that the model is only valid when the MOSFET channel determines the switching speed, i.e. the drain current is significantly larger than the current flowing in the parasitic MOSFET capacitances [Xi04].

Experimental verification

The results obtained from prior overvoltage estimation model have been compared to practical measurements with the 5μmCu case study converter. Again, loop inductances were increased and the resultant turn-off overvoltages were measured. Figure 5-45 shows the measured MOSFET’s drain source voltages at turn-off with different loop inductances, as

01020304050607080

0 10 20 30

oerv

olta

ge Δ

vds [

V]

Loop inductance [nH]ΔVds Ls=1nH ΔVds Ls=2nH

ΔVds Ls=5nH ΔVds Ls=10nH

0

0.2

0.4

0.6

0.8

1

1.2

0 10 20 30

Turn

-off

loss

es [

W]

Loop inductance [nH]Psw Ls=1nH Psw Ls=2nH

Psw Ls=5nH Psw Ls=10nH


indicated in the figure. It can be seen that the values obtained from the analytical calculation are in close correlation with the measured voltages. For example, the analytical model delivers an overvoltage of Δvds_calculated=28V at a loop inductance increase of ΔLloop=6nH (total Lloop=14.4nH), whilst a value of Δvds_measured=25.2V has been measured across the MOSFET drain source.

Figure 5-45: Comparison of MOSFET drain source voltage at turn-off for case study layout @ Idrain=7Awith additional loop inductance added - Ch.1-Ch.3: drain source voltage 20V/div, time-scale: 20ns/div

The analytical model can therefore be helpfully used to determine power limits of 3D-MID-based power converters, when circuit trace parasitics and current values are known. Furthermore, the model can be used to find optimised 3D-MID layouts for given power levels.

Summary on limitations of 3D-MID-based power converters

The foregoing investigations underline that already low power applications can cause high overvoltages on 3D-MIDs as these are more prone to increased loop inductances whilst high switching speeds are required to keep losses low.

It is also noticeable that higher current values as the investigated (I >7A) will have even stricter demands on a compact power loop design on 3D-MIDs. This issue gets further amplified as wider traces are required to achieve the current carrying capacity, which in turn will negatively influence parasitics, and so converter performance.

A careful trade-off between overvoltages and resulting losses is therefore necessary for 3D-MID applications. This can be determined by the extraction of circuit parasitics combined with calculation or simulation of resulting overvoltages and losses, as demonstrated with the foregoing case study approach.

ΔLloop=20nH

ΔLloop=6nH

ΔLloop=0nH

156 Chapter 5

In addition, the implementation of an effective thermal management will challenge the physical realisation of power electronics on 3D-MIDs, when heat spreading-, conduction- and convection- surfaces have to be enlarged. This issue will be addressed in more detail in Chapter 6.

5.5. 3D-routing possibilities and concepts

Next to planar routing, three-dimensional routing is generally available with 3D-MIDs, because the substrate can be nearly arbitrarily shaped as long as laser activation is possible. The versatilities in three-dimensional surface orientation and substrate shaping are therefore very high, which can be used to enhance converter power density in a similar manner as has been done in flexible PCB-based power converter design, investigated in [Jo07]. However, smooth and planar surfaces are preferred on 3D-MIDs wherever a 3D-shape is not necessarily required to fulfil the target design. Reasons are to keep manufacturing efforts and hence cost, e.g. for injection moulding-tools, low. In addition, planar surfaces allow a higher flexibility for component positioning and routing in contrast to non planar structures, without tool changes.

No major differences appear in the basic layout generation in three dimensions, as several planar surfaces can be combined to achieve the 3D shape. The routing and component placement on these surfaces has been investigated in Sections 5.4.1-5.4.3 and shows that the largest differences in routing and component positioning appear due to the limited layer number and the effort of using vias when compared to PCB technology. Limitations and design trade-offs in the spatial and electrical realisation of power converters on 3D-MIDs have been discussed and can be used to get an indication if a 3D-MID realisation of a prospective power converter is feasible. The results are therefore still valid in a broad range of routing scenarios in 3D.

However, different special cases exist that allow influencing the circuit layout as well as component positioning in three-dimensions by modifying the 3D-MID’s surface (Figure 5-46).

Figure 5-46: Examples of 3D substrate modification usable available with 3D-MIDs

3D modification of substrate surface to improve circuit layout and component positioning


A variety of concepts have been worked out that use the 3D circuit carrier to improve component density, to reduce circuit footprint and to add additional layout versatility in contrast to routing on planar surfaces. The concept ideas can be understood as basic building blocks available for 3D-MID shaping and can be combined to improve three-dimensional routing.

Table 5-8 gives an overview how the 3D-MID substrate can be modified to improve the prior addressed problems. The positive aspects of the implementation as well as their drawbacks are summarized. Wherever it is possible, the conventional two-dimensional solution that can be realised on planar substrates, e.g. with PCBs or 3D-MIDs, is given for reasons of comparison.

The individual solutions will be described in the following. The ideas are sorted by the key functions the substrate shaping performs to obtain improved layouting and component positioning on 3D-MIDs.

5.5.1. Increasing the circuit- and the component-density

Circuit density

The 3D-MID substrate surfaces can be shaped in three-dimensions to create non planar circuit trace cross sections, as exemplary shown in Table 5-8 No. 1. The benefit of the 3D trace cross sections are reduced footprint requirements at increased ampacity when compared to their 2D counterparts. For a simple laser structuring process, cross sectional areas that allow the lasing without component turning are preferable, i.e. laser shadows should be avoided [LP11a]. The drawback of this approach is that increased efforts have to be made for creating injection moulding tools and that the circuit layout flexibility is greatly reduced when compared to a pure circuit track realisation with the LDS process.

Component density

Next to the reduction of circuit trace footprints, 3D-MID substrate shaping could be used to decrease the volume occupied by components. Component stacking and -alignment in three dimensions are available means to increase the low circuit- and component-density given by 3D-MID technology. Table 5-8 No.2 shows two different examples how the substrate can be used to obtain improved volume utilisation with 3D-MIDs when compared to a conventional planar component orientation, discussed in Section 5.4.

The substrate could be shaped in a manner, that components can be stacked in three-dimensions, e.g. to add back-up capacitors below large ICs, or to add additional routing surfaces in 3D to decrease footprint requirements. In this approach, components with contacting pads on their bottom have to be avoided; and in general special care has to be taken of the components’ thermal management. Another option is to align components in a way that only low areas with unused air remains in electronic system, which would be a similar approach as done with power converter optimisation using flexible PCBs, shown in [Jo07]. In both cases lasing and component contacting could still be manageable by 3D contacting

158 Chapter 5

processes available for 3D-MIDs, e.g. with 3D-pick & place, -solder paste dispensing and -vapour phase soldering. However, the same challenges including increased tool efforts and reduced layout flexibility have to be considered.

5.5.2. Integration of additional functions

Extended routing and contacting surfaces

In contrary to PCBs, the side surfaces of 3D-MIDs can be used for circuit routing, as well. This could be beneficially used to contact the bottom and the top layer without requiring via technology and it further extends routing functionality compared to 2D circuit carriers, as shown in Table 5-8 No. 3. In addition, heat spreading areas could be increased in a similar manner and could also be used in small sections if the 3D-MID to increase heat-spreading areas without increasing footprint requirements, which will be commented further in Section 6.3.2.

It has to be noted that increased laser structuring times might be required for using all sides of the substrate for routing but has to be considered individually for the given substrate geometry.

Component orientation and levelling

The possibility to align components in 3D is not only a proper means to increase component density; it can moreover be used to enhance component orientation for increased performance, as indicated in Table 5-8 No. 4 (top). One application example could be the exact positioning of LEDs to obtain an exact light output distribution without requiring additional components.

Further, countersinking of components can be achieved by optimising the substrate shape to create an even height level among different components (Table 5-8 No. 4 (bottom)). This can be beneficially to decrease the overall assembly height and can moreover be used to simplify the connection of heat sinks on the top of components, e.g. when standard two-dimensional heat sinks can be attached. Further, only thin thermal interface materials are required when similar height levels are present. This leads to decreased thermal resistances and hence increased cooling performance.

The component orientation and levelling requires adapted injection moulding tools and has to be considered.

Housing and shielding of (individual) components

Next to component alignment and stacking of components, those can also be inserted into entire mounting holes, as illustrated in Table 5-8 No. 5. This can be used for 3D component stacking and could be used to implement partial shielding areas around the component, e.g. surrounding unshielded power inductors or even power sections of switched mode systems.

To obtain this, the mounting holes have to be created by means of injection moulding, first.Laser activation followed by chemical copper deposition is required to create shielding


surfaces on the sidewalls of the mounting holes. For this, laser activation and component positioning must still be possible at the existing space.

In a further extent also the over moulding of entire components could be considered for 3D-MIDs when the used components are able to withstand the injection moulding process that involves high temperatures and high pressure levels. The approach, has been applied to lead frame based ultra-flat LED-taillights, as described in [GB06] and could be available for future MID-based applications.

Integration of routing- and optical-components in 3D-MID substrate

Finally, the 3D-shaping of the substrate can be used in a variety of ways to directly integrate routing components in the 3D-MID itself. Table 5-8 No. 6 shows the example of a connector that is directly shaped with the substrate as one representative example. The substrate can be shaped by in the injection moulding process to define the connector dimensions and laser structuring followed by copper deposition can be used to create the required electrical contacting pads on the 3D-MID-based connector. These connectors can be further used to attach additional PCBs to the 3D-MID, e.g. to solve complex routing tasks, as done in [Ho08]. Further, jumper components could also be replaced when signal crossings are solved by selective substrate shaping.

Finally, electro-optical systems could get available when laser-structured 3D-MID materials and transparent polymers, like PMMA, are successfully combined in 2-shot injection moulding processes. Hence, the 3D-MID itself could be used as lighting component that is enlightened, e.g. when transparent optical fibres are integrated in the 3D-MID. This could further extend the function integration of future 3D-MIDs and is especially desirable to obtain compact LED-lighting systems.

5.5.3. Summary on 3D-routing

It can be summarized that a variety of routing and component positioning problems that appear on simple two-dimensional substrates (discussed in Section 5.4) can be improved by modifying the 3D-MID substrate in three-dimensions. This requires changes of injection moulding tools in dependency of the circuit layout in nearly all of the introduced concepts. Hence, layout flexibility given by the LDS process gets undermined.

Thus, a trade-off between the effort of conventional routing and three-dimensional substrate modification is required, although 3D-MIDs inherently allow high complexity levels in three-dimensions.

160 Chapter 5

Tabl

e 5-

8:O

verv

iew

of s

ubst

rate

mod

ifica

tion

conc

epts

to im

prov

e la

yout

and

com

pone

nt p

lace

men

t on

3D-M

IDs

No.

Des

crip

tion

Sket

chB

enef

its o

f im

plem

enta

tion

Dra

wba

cks

of im

plem

enta

tion

Con

vent

iona

l 2D

solu

tion

1

Mod

ifica

tion

of

subs

trate

geo

met

ry

for i

ncre

ased

am

paci

ty

Red

uctio

n of

foot

prin

t are

a

Incr

ease

of C

CC

at s

ame

foot

prin

t

Incr

ease

d ef

fort

in c

onst

ruct

ion

of

inje

ctio

n m

ould

ing

tool

Dec

reas

ed la

yout

flex

ibili

ty

2

Mod

ifica

tion

of

subs

trate

geo

met

ry

for i

ncre

ased

co

mpo

nent

den

sity

com

pone

nt s

tack

ing

Red

uctio

n of

foot

prin

t are

a

Incr

ease

of c

ompo

nent

den

sity

Incr

ease

d ef

fort

in c

onst

ruct

ion

of

inje

ctio

n m

ould

ing

tool

Dec

reas

ed la

yout

flex

ibili

tyad

ding

of e

xtra

surfa

ces

3U

seof

add

ition

al

surf

aces

for r

outin

g

Avo

idan

ce o

f via

s

Incr

ease

of

usab

le ro

utin

g ar

eaIn

crea

sed

lase

r tim

eor

43D

com

pone

nt

orie

ntat

ion

and

leve

ling

Exac

t 3D

com

pone

nt o

rient

atio

n

Com

pone

nt p

ositi

on n

ot c

hang

eabl

e w

ithou

t too

l cha

nge

not p

ossi

ble

Gen

erat

ion

of u

nifo

rm h

eigh

t le

vel o

f com

pone

nts

5H

ousi

ng o

f co

mpo

nent

s(L

imite

d) 3

D st

acki

ng

poss

ibili

ty o

f com

pone

nts

Incr

ease

d ef

fort

in in

ject

ion

mou

ldin

g pr

oces

sno

t pos

sibl

e

6

Rea

lisat

ion

of

rout

ing

com

pone

nts

with

su

bstra

te

e.g.

3D

-MID

con

nect

orR

educ

tion

of c

ompo

nent

num

ber

and

spac

e re

quire

d

No

pick

& p

lace

nec

essa

ry

Incr

ease

d ef

fort

in in

ject

ion

mou

ldin

g pr

oces

s and

lase

r tim

eno

t pos

sibl

e


5.6. Summary

In this chapter, merits and limitations that arise when power converters are aimed to be realised on 3D-MIDs are determined. This contains influences of 3D-MID circuit track dimensions and layer availability on the spatial realisation of circuit traces, which in turn influences circuit track parasitics and hence, affects the electrical performance of the switched mode power converters.

It is identified in this chapter that especially the construction technology of (LDS) 3D-MIDs limits the available circuit routing variances as well as the Current Carrying Capacity (CCC) of circuit tracks, which is mainly determined by the selective additive generation of the copper traces, the limited layer availability and the lack of a generally applicable via-technology when compared to conventional PCB technology (Section 5.2). It is also observed that increasing the trace width rather than the copper thickness, by using additional electroplating processes, is the simplest solution to obtained increased CCC of 3D-MIDs. The required circuit trace dimensions can be obtained by CCC modelling, analysed in Section 5.3.1. However, increasing the trace width decreases the circuit density manifesting in rising contacting challenges of components, increased component distances and enlarged parasitic layout inductances. The latter is especially pronounced when no ground layer can be implemented on 3D-MIDs (Section 5.3.3).

The influence of increased trace inductances on the electrical performance of power converters is investigated systematically in Section 5.4, starting with optimised layouts at low power to power converters with increased power level and large parasitic inductances present. Circuit trace parasitic extraction combined with analytical modelling or simulation of the expected electrical behaviour is used as means to determine the feasibility of prospective power converters on 3D-MIDs. The results obtained from the analyses and simulations are experimentally verified with various case-study layouts to prove the used methods (Section 5.4.3 and 5.4.4).

It is shown in the electrical design, that the successful realisation of power electronic systems on 3D-MIDs requires optimised circuit layouts with low complexity, as already low-power applications are prone to considerably high overvoltages across switching devices. Reasons are increased component distances on 3D-MIDs and the susceptibility to increased loop inductances. This gets further amplified, as fast switching speeds are required to obtain low losses for a simplified 3D-MID-based thermal management. A careful trade-off between overvoltages and resulting losses is therefore necessary for 3D-MID applications.

The limitations in circuit routing and component positioning that appear on planar surfaces of 3D-MIDs can be overcome in special cases by using 3D-shaping of the substrate, discussed in Section 5.5. However, changing the substrate’s surface topology comes at expenses of modifying injection moulding tools in dependency of the circuit layout. Hence, the layout flexibility of the 3D-MID LDS process gets undermined and a trade-off between the effort of conventional (2D) routing and three-dimensional substrate modification is required.

Bibliography [Ad04] Adam, J.: New correlations between electrical current and temperature rise in PCB

traces: Proc. Twentieth Annual IEEE Semiconductor Thermal Measurement and Management Symposium, 2004; pp. 292-299.

[Ah06] Ahrendt, D.; Gherlach, I.; Stich, R.; Weser, S.: Untersuchungen zu Micro-Vias bei Laser-Feinst-Pitch-MID für die Mikrosystemtechnik (Vorhaben AiF 14282 N), 2006.

[AN12a] ANSYS, Inc: Maxwell 3D, 2012a.

[AN12b] ANSYS, Inc: ANSYS, 2012b.

[Ba06] Balogh, L.: Design And Application Guide For High Speed MOSFET Gate Drive Circuits. In Power Supply Design Seminar SEM-1400, Topic 2, 2006.

[Ba07] 3D-MID Bayer Kunststoffe, 2007.

[BM00] Blattner, R.; McDaniel, W.: Thermal Management in On-Board DC-to-DC Power Conversion, 2000.

[BM07] Mess- und Prüftechnik für die laserbasierte Fertigung von multifunktionalen 3D- Packages - MELAM-3D, 2007.

[Bo883] Bogatin, E.: Design rules for microstrip capacitance. In Hybrids Components, 1988, 11; pp. 253-259.

[Br98] Brooks, D. Ed.: Temperature Rise in PCB Traces, 1998.

[BSS072] Bruns, H. D.; Schuster, C.; Singer, H.: Numerical Electromagnetic Field Analysis for EMC Problems. In IEEE Transactions on Electromagnetic Compatibility, 2007, 49; pp. 253–262.

[CCW08] Coppola, L.; Cottet, D.; Wildner, F.: Investigation on current density limits in power printed circuit boards: Proc. Twenty-Third Annual IEEE Applied Power Electronics Conf. and Exposition APEC 2008, 2008; pp. 205-210.

[Ci12] CircuitMart Inc.: PCB Capability, 2012.

[Co10] Cougo Franca, B.: Design and Optimization of InterCell Transformers for Parallel MultiCell Converters, Institut National Polytechnique de Toulouse, 2010.

[DS07] DSM Engineering Plastics: Stanyl® ForTii™ - Datasheet, 2009.

[EgFl10] S. Egelkraut, L. F. M. R. A. S. M. M.: Polymer bonded soft magnetics for EMI filter applications in power electronics. In Institute of Electrical and Electronics Engineers -IEEE-: Twenty-Fifth Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2010: Palm Springs, California, USA, 21 - 25 February 2010. Piscataway/NJ: IEEE, 2010, pp. 231-238, 2010.

[Ek01] Ekman, J.: Simplified PEEC Models for PCB Structures and Comparison to Experimental Data: Proceedings of the Progress in Electromagnetic Research Symposium, PIERS, 2001.

[Ek03] Ekman, J.: Electromagnetic modeling using the partial element equivalent circuit method. Univ. of Technology, LuleÃ¥, 2003.

[Fe02] Ferreira, J.; Waffenschmidt, E.; Strydom, J.; van Wyk, J.: Embedded capacitance in the PCB of switchmode converters. In 2002. pesc 02. 2002 IEEE 33rd Annual Power Electronics Specialists Conference, 2002, 1; pp. 119-123.

[Fe04] Feldmann, K. Ed.: Technologie 3D-MID. Räumliche elektronische Baugruppen ; Herstellungsverfahren, Gebrauchsanforderungen, Materialkennwerte. Hanser, München, 2004.

[Fe941] Ferreira, J.: Improved analytical modeling of conductive losses in magnetic components. In IEEE Transactions on Power Electronics, 1994, 9; pp. 127–131.

[GB06] Gausemeier, J.; Bigl, T.: Integrative Entwicklung räumlicher elektronischer Baugruppen. Hanser, München [u.a.], 2006.


[Gr46] Grover, F.: Inductance Calculations: Working Formulas and Tables. Van Nostrand, 1946.

[Gu98] Guenin, B.: Convection and radiation heat loss from a printed circuit board: Electronics Cooling; p. 33.


[HJB04] Heininger, N.; John, W.; Boßler, H.-J.: Manufacturing of Molded Interconnect Devices from Prototyping to Mass Production with Laser Direct Structuring: 6. International Congress Molded Interconnect Devices MID, 2004.

[Ho08] Holst, J.-C.: Micromechatronic Integration Using MID-Technologies: Highly Integrated Micro-Robot: 8th International Congress Molded Interconnect Devices.

[Ho984] Holden, H.: Microvias: the next generation of substrates and packages. In IEEE Micro, 1998, 18; pp. 10–16.

[IP91] IPC - Association Connecting Electronics Industries: IPC-2221 - Generic Standard on Printed Board Design, 1991.

[Is98] Ishida, T.: Advanced substrate and packaging technology. In 2nd 1998 IEMT/IMC Symposium, 1998; pp. 18-24.


[Jo11] John, W.: Approved plastics for the operation of a LPKF MicroLine 3D Laser System, 2011.

[KB83] Kraus, A. D.; Bar-Cohen, A.: Thermal analysis and control of electronic equipment, Washington u.a. Hemisphere Publ. Corp. u.a, 1983.

[KK00] Kiani, S.; Khusid, M.: A new method to interconnect PCB layers in GHz frequency range. In 2000. 2000 Proceedings. 50th Electronic Components & Technology Conference, 2000; pp. 432-438.

[KSW96] Kamon, M.; Smithhisler, C.; White, J.: FastHenry USER’S GUIDE Version 3.0, http://www.fastfieldsolvers.com, 1996.

[LA11] LANXESS Deutschland GmbH: Pocan DP 7102 000000 - Datasheet, 2011.

[Le05] Lee, B.: Package Parasitics Influence Efficiency. In Power Electronics Technology, 2005; pp. 14–21.

[Le11] Lehnberger, C.: High current PCBs - system integration of busbars and electronics. In 2011 1st International Electric Drives Production Conference (EDPC), 2011; pp. 63-64.

[LHS08] Leneke, T.; Hirsch, S.; Schmidt, B.: A multilayer process for fine-pitch assemblies on molded interconnect devices (MIDs), 2008; pp. 663-668.

[LM66] Lammeraner; Milos, S.: Eddy currents. Iliffe Books, London, 1966.

[LP11a] LPKF Laser & Electronics AG: LPKF Fusion 3D 6000 - High Volume Production with Multiple Laser Heads - Datasheet, 2011a.

[LP11b] LPKF Laser & Electronics AG: LDS Design Guidelines, 2011b.

[Me08] Meade, T.; O'Sullivan, D.; Foley, R.; Achimescu, C. et al.: Parasitic inductance effect on switching losses for a high frequency Dc-Dc converter. In 2008. APEC 2008. Twenty Third Annual IEEE Applied Power Electronics Conference and Exposition, 2008; pp. 3–9.

[Mi09] Mitsubishi Engineering-Plastics Corporation: XANTAR® LDS 3710 - (PC+ABS) - Datasheet, 2009.

[Mi12] Microchip Technology Inc.: 6A High-Speed Power MOSFET Drivers, 2012.

[MI12] MIT: Summary of white papers and publications related to FastHenry software, 2012.

[Na12] National Electrical Manufacturers Association: Industrial Laminated Thermosetting Products - NEMA LI 1-2011, 2012.

[Pa03] Pavier, M.; Sawle, A.; Woodworth, A.; Monteiro, R. et al.: High frequency DC:DC power conversion: the influence of package parasitics. In 2003. APEC ’03. Eighteenth Annual IEEE Applied Power Electronics Conference and Exposition, 2003, 2; pp. 699-704.


[Re01] Remsburg, R.: Thermal design of electronic equipment. CRC Press, Boca Raton, Fla, 2001.

[Ro082] Rosa, E. B.: The Self and Mutual Inductance of Linear Conductors. In Bulletin of the National Bureau of Standards, 1908, 4; pp. 301–344.

[RR95] Radoeva, M.; Radoev, B.: Ohm resistivity of electroless copper layers as a function of their thicknesses. In Journal of Materials Science, 1995, 30; pp. 2215–2219.

[RT08] RTP - Imagineering Plastics: Polyphthalamide (PPA) RTP 4099 X 117359 D - Product Data Sheet, 2008.

[Ru725] Ruehli, A. E.: Inductance Calculations in a Complex Integrated Circuit Environment. In IBM Journal of Research and Development, 1972, 16; pp. 470-481.

[Ru743] Ruehli, A.: Equivalent Circuit Models for Three-Dimensional Multiconductor Systems. In IEEE Transactions on Microwave Theory and Techniques, 1974, 22; pp. 216-221.

[Sc08] Schuh, S.: 3D-Integration in der Leistungselektronik. PhD Thesis, 2008.

[Sc695] Schneider, M.: Microstrip lines for microwave integrated circuits. In Bell system technical journal, 1969, 48; p. 1421.

[Sc953] Schanen, J. L.; Guerin, C.; Roudet, J.; Meunier, G.: Influence of a conductive plane on loop inductance. In IEEE Transactions on Magnetics, 1995, 31; pp. 2127–2130.

[SRKN02] Schlueter, R.; Roesner B.; Kickelhain L.; Naundorf G.: LPKF-LDS-technology - a laser supported fully additive process to manufacture three dimensional circuit boards for mechatronic applications: International Congress on Molded Interconnect 2002.

[ST11] STMicroelectronics: STPS2L60 - Power Schottky rectifier, 2011.

[Ti07] Ticona GmbH: Vectra - Flüssigkristalline Polymere (LCP), 2007.

[TP11] Thomas, W.; Pforr, J.: Design of power converters on 3D-MIDs for driving three-dimensional LED-lamps. In 2011 IEEE Energy Conversion Congress and Exposition (ECCE), 2011; pp. 325-332.

[Va02] Varteresian, J.: Fabricating printed circuit boards. Newnes, New York, 2002.

[Vi08] Vishay Siliconix: SUD23N06-31L, N-Channel 60 V (D-S), 175 °C MOSFET, Logic Level: Datasheet, 2008.

[Vi12] Vishay Dale: Low Profile, High Current IHLP® Inductors, 2012.

[WAF05] Waffenschmidt, E.; Ackermann, B.; Ferreira, J.: Design method and material technologies for passives in printed circuit Board Embedded circuits: IEEE Transactions on Power Electronics, 2005; pp. 576–584.

[Wh778] Wheeler, H.: Transmission-Line Properties of a Strip on a Dielectric Sheet on a Plane. In IEEE Transactions on Microwave Theory and Techniques, 1977, 25; pp. 631-647.

[Wi09] Wilde et al., J.: Modellunterstütze Optimierung der Stiftkontaktierung bei MID (MOSKOM), 2009.

[WN98] Ward, A.; Nelson, D.: Development of a heat spreader for high power electronic modules using thermal vias. In 1998. ITHERM ’98. The Sixth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, 1998; pp. 520-523.

[Xi04] Xiao, Y.; Shah, H.; Chow, T.; Gutmann, R.: Analytical modeling and experimental evaluation of interconnect parasitic inductance on MOSFET switching characteristics. In 2004. APEC '04. Nineteenth Annual IEEE Applied Power Electronics Conference and Exposition, 2004, 1; pp. 516–521.

[YHF09] Yi Wang; Haan, S. W. H. de; Ferreira, J. A.: Thermal design guideline of PCB traces under DC and AC current: Proc. IEEE Energy Conversion Congress and Exposition ECCE 2009, 2009; pp. 1240-1246.

[Yu02] Yun Ling: On current carrying capacities of PCB traces: Proc. 52nd Electronic Components and Technology Conf, 2002; pp. 1683-1693.

[Yu062] Yuancheng, R.; Ming, X.; Jinghai, Z.; Lee, F.: Analytical loss model of power MOSFET. In IEEE Transactions on Power Electronics, 2006, 21; pp. 310-319.

[ZBB10] Zheng, C.; Boroyevich, D.; Burgos, R.: Experimental parametric study of the parasitic inductance influence on MOSFET switching characteristics. In 2010 International Power Electronics Conference (IPEC), 2010; pp. 164–169.

6. Integration of thermal management functions

6.1. Introduction

Thermal management plays a dominant role for the reliability of power electronic components, as the majority of components degrades due to temperature related effects which has been addressed in several publications [ZJL97], [Hi076]. A careful implementation of heat removal solutions is also an essential cornerstone in the design of LED-lighting systems with integrated LED-driver as not only component lifetime, but especially LEDs’ optical efficacies are directly related to their junction temperatures [Sc03] (Chapter 2).

Chapter 5 has already shown that circuit routing flexibility is greatly decreased on 3D-MIDs when compared to technologies like PCBs. This also challenges the realisation of improved (circuit carrier-based) thermal management on 3D-MIDs, as routing demands will contradict with the implementation of thermal pathways on 3D-MIDs.

In this chapter, the implementation of an effective thermal management for 3D-MID-based LED-lighting systems will be discussed. This contains the determinations of technical constraints that restrict the practical realisation of heat removal solutions and which limit the maximum power that can be dissipated.

The chapter starts with the identification of the dominant heat transfer modes and of the challenges that appear for 3D-MID-based LED-lighting systems with LED-driver (Section 6.2).

3D-MIDs’ heat transport capabilities and limitations are analysed in Section 6.3. Furthermore, possibilities to introduce alternative cooling solutions to extend 3D-MID power levels are discussed.

Section 6.4 is used to describe a possible design of 3D-MID-based component cooling by means of a case study LED-driver. In Section 6.5, a novel thermal management approach is introduced to directly remove heat from high-power LEDs located on 3D-MIDs, which extends processable power levels of MIDs.

The chapter is summarized in Section 6.6.

6.2. Identification of dominant heat transfer modes in LED-lighting systems

Three different modes of heat transfer exist in nature: conduction, convection and radiation. Their fundamental characteristic, boundary conditions and interdependencies are described in detail in the literature, e.g. [Re01],[HRC98].

An effective thermal management process for electronic equipment, and hence of LED-lighting systems with LED-driver, however is not related to a single heat transfer mechanism.

168 Chapter 6

It is a comprehensive and multilayered approach that has to be performed on different levels to maintain effective component cooling. The following levels can be classified in the thermal management of a power converter [Jo13]:

Component level: the heat transport within the component package

Converter level: heat transport from the component surface to the converter surfaces (e.g. circuit carrier, heat sink)

System level: heat transfer from converter surfaces to ambient, i.e. cooling- and environmental- conditions

Figure 6-1 shows the different levels involved in the thermal management within a converter.

Figure 6-1: Levels involved in thermal management process

Thermal management on the component level is not focused in this thesis, as discrete standard SMT components are used. However, it is required that the dominant heat transfer mechanism of the individual components is known for a proper thermal design of the entire power electronic system.

6.2.1. LED-driver components

Figure 6-2 (a) gives an overview of how the heat transfer modes contribute to component cooling for typical packages used in PCB-based power converters, as investigated in [Er00]. It can be seen that conduction is the dominant mechanism for components placed on PCBs, whereas particularly SMT devices are optimised for conductive heat transport. This is mainly related to improvements in their packaging with reduced thermal resistances [SBM02].

(a) Component level

Device

Q

(b) Converter level

Board

Device

Q

(c) System levelEnvironmental conditions:cooling, mounting, mechatronic integration

Integration of thermal management functions 169

Figure 6-2: Breakdown of how the heat transfer modes contribute to (a) power converter component cooling [Er00] and (b) to cooling of different light sources [Pe04] under natural convection

6.2.2. High-power LEDs

A comparative breakdown on heat transfer modes of different light sources has been performed by [Pe04] which shows that high-power LEDs are strongly dependent on conductive heat transfer when compared to conventional light sources, as visualised in Figure 6-2 (b). The reasons for this development are the very high heat fluxes (>80W/cm²) that appear in high-power LEDs exceeding those of microprocessors [Fa12]. Hence, the power dissipated in the small LED-chip area (typical Achip=1mm²) has to be transported effectively, which requires low resistive thermal paths. Therefore, LED packages have been highly improved in the past to achieve low junction to case resistances, with typical values of Rth=3-8K/W for high-power LEDs. An overview of this development is given in [Sc03].

6.2.3. 3D-MID challenges

The optimisation of SMT-devices in the LED-driver and of high-power LEDs towards heat conduction requires low resistance pathways on the converter level for effective heat transport. Chapter 5 has already indicated that the low copper layer thickness and the limited layer number of 3D-MIDs will negatively affect the heat conduction when compared to state of the art PCB technology. Conventional MID substrates show perpendicular thermal resistances of 35K/W, if a thickness of 1 mm and a plate area of 1 cm² are assumed. Achieving low component temperatures for high-power LED-lighting systems – power losses Ploss ≥10W – therefore becomes very challenging using the 3D-MID substrate only.

The capabilities and limitations of the converter level thermal management on 3D-MIDs, consequently, come into focus and have to be investigated, which will be performed next.

0%

25%

50%

75%

100%

Dual in line Surface mounted device

Hybrid circuit with metal case

(a) Heat transfer for components mounted on glass-epoxy PCB

0%

25%

50%

75%

100%

Incandescent Fluorescent High Intensity

Discharge

LED

Radiation

Conduction

Convection

(b) Heat transfer of selected light sources

170 Chapter 6

6.3. Converter level thermal management

In this section, heat removal solutions and limitations using the 3D-MID circuit carrier as well as the application of additional cooling structures combined with 3D-MIDs will be focused.

Whenever a technique is also available with state of the art PCB technology, comparative values will be given to clarify the thermal management performance of 3D-MIDs. In addition, 3D-MID specific thermal-management options will be discussed.

Different possibilities exist how to enhance the converter level thermal management of 3D-MIDs:

Geometry- and layout-enhancement to optimise the component arrangement and the circuit layout in two- or three-dimensions as well as to modify the substrate geometry for enhanced heat transport

Additional heat sinks on component- or converter-level to decrease the thermal resistance of the 3D-MID to the environment

Integration of extra thermal pathways of highly conductive material to circumvent the low thermal conductivity of the 3D-MID thermoplastic substrate materials

Substrate material modification to increase the thermal conductivity of the substrate materials for decreased in-plane and perpendicular thermal resistances

These feasibility and performance of these solutions will be discussed in the subsequent sections. In a first step, the heat transport performance in the 3D-MID will be focused on, as this will determine the effectiveness of the thermal management enhancements.

6.3.1. Perpendicular heat transport and heat spreading

Section 6.2 has shown that conduction is the dominant mode of heat transport in LED-lighting systems with LED-driver. For the conduction inside the circuit carrier, two 1-dimensional heat transfer paths can be identified, in principle:

Heat transport perpendicular to the circuit carrier

In plane heat transport, especially in thermally high conductive layers: heat spreading

The heat transport within the 3D-MID circuit-carrier will be described in the following.

Perpendicular heat transport

Good perpendicular heat transport of the circuit carrier is required to transport heat generated by a heat source, e.g. power electronic components, through the circuit carrier layers with minimum temperature rise. Chapter 5 has already shown that standard PCB and 3D-MID substrate materials behave as thermal isolators, whereas only the copper layers provide a high


thermal conductivity. Figure 6-3 shows the influence of the substrate material thickness on 3D-MIDs’ and PCBs’ perpendicular thermal resistance.

Rectangular single layer 3D-MID and PCB plates with and without thermal vias as well as with variable substrate thickness have been used. The plates’ surface area has been set to Aplate=1cm² and standard material parameters have been used, as given in the figure [TP11]. The entire surface Aplate is used for the calculation of the thermal resistances. The figure shows the circuit carrier configuration with and without vias and related material parameters, respectively. In Figure 6-3 (a), the resulting perpendicular thermal resistances are plotted over the substrate thickness.

Figure 6-3: Comparison of perpendicular thermal resistance of 3D-MIDs compared to PCBs with and without thermal vias used

It can be seen from the charts that the isolating character of the substrate materials dominates the perpendicular heat transport for both circuit carrier techniques, with a slightly better performance for the 3D-MID substrate due to the higher thermal conductivity.

With PCB technology, thermal vias are used to compensate the poor substrate conductivity, as described in Chapter 5.2.3. However, it has also been shown that vias are not easy to implement on 3D-MIDs and less vias can be placed on the same surface area.

The influence of thermal vias on the perpendicular heat transport of both circuit carriers has been calculated for the input parameters, defined in Table 6-1.

Table 6-1: Input parameters used for calculation of via influence on perpendicular heat transport

Copper thickness

[μm]

Top and bottom

layer used

Area for vias available

[mm²]

Via distance

[mm]Via diameter

[mm]Number of

vias

PCB 35 yes 7x7 0.6 0.3 50

3D-MID 10 yes 7x7 0.6 Dependent on substrate thickness

0

10

20

30

40

50

0.5 1.0 1.5 2.0The

rmal

res

ista

nce

[K/W

]

Thickness of substrate tsub [mm]

PCB single 35μm PCB double 35μm w. 50 viasMID single 10μm MID double 10μm w. vias

15

25

35

0.5 1.0 1.5 2.0

No.

ofM

IDvi

as

Thickness of substrate tsub [mm]

number of 3D-MID vias

αcvia_3D-MID

ci tsub

Configuration with vias(introduced in Chapter 5)

PCB technology:

3D-MID (LDS) technology:

Number of vias n=f(tsub) [TP11]

Configuration without vias

dvia

λsub

λCu

Aplate=1cm²

PCB3D-

MID

Copper layer

tcu [μm] 35 10

λCu [W/mK] 394

Substrate layer

tsub [mm] variable

λsub [W/mK] 0.25 0.28

(a)

(b)

172 Chapter 6

The thermal resistance calculation further assumes unfilled vias with identical copper thickness as the copper layer for simplicity. The total thermal resistance is considered as parallel connection of the individual via- and the substrate-resistance [Li98].

The results of the calculation can also be seen from Figure 6-3 (a). Additionally, the integer numbers of vias that can be placed on the 3D-MID are plotted in Figure 6-3 (b). It can be derived from the charts that the effect of vias on 3D-MIDs is limited when compared to PCBs as only a reduced number of vias can be implemented on the same footprint area, e.g. only 28 vias can be applied in contrast to 50 vias on PCB at a substrate thicknesses of tsub=1mm. This strongly influences the perpendicular heat transport. Moreover, the efforts and limitations in creating 3D-MID vias, which have been discussed in Chapter 5.2.3, still remain.

From a thermal management point of view it is therefore desirable to use low substrate thicknesses with 3D-MIDs to achieve low perpendicular thermal resistances. This stands in contrast to requirements on mechanical stability and, hence a trade-off decision is necessary.

Heat spreading

Heat spreading is used to counteract the appearance of hot-spots, when heat is generated in concentrated volumes with a significant power loss, e.g. in high-power LEDs. Heat spreaders therefore consist of highly thermally conductive materials, like copper, to spread the concentrated heat into a considerable larger surface area, as shown in Figure 6-4. Thus, the thermal resistance can be decreased significantly when the heat has to cross layers with high thermal resistances, e.g. air or other thermal isolators.

Figure 6-4: Heat spreader principle

As with the PCB technology, the already present copper layer can be used on 3D-MIDs to improve heat spreading from components. The heat spreading efficiency, however, is dependent on thickness and thermal conductivity of the heat spreading material. Especially, the copper layer thickness of 3D-MIDs is considerably lower than those of PCBs and will restrict heat spreading.

Figure 6-5 shows the influence of 3D-MIDs’ copper layer thickness on the in plane thermalresistance. In addition, values for standard PCBs have been calculated for reasons of comparison (tsub=1.55mm and tCu=35μm). The calculation uses the geometries, defined in Figure 6-3. However a constant temperature difference between the sidewalls and a uniform wall temperature has been assumed for simplicity.

High heat fluxQDevice

Low heat fluxHeat spreader (λhs= high: e.g. copper layer)

Heat path (λpath= low: e.g. substrate)

Cold plate or heat sink


Figure 6-5: Comparison of in-plane thermal resistance of 3D-MIDs compared to PCBs

It can be seen from the charts that the substrate thickness positively influences the in plane thermal resistance at very low copper layer thicknesses determined by the high resistance of thin sheets. At copper thicknesses of >10μm, the substrate influence gets negligible, because heat spreading is now performed nearly completely in the high conductive copper layers. A comparison of typical 3D-MID and PCB configurations account the prior a significantly higher thermal resistance, e.g. a factor of three lies between 3D-MIDs with 10μm copper compared to standard PCBs with 35μm. Multiple copper layers combined for heat transport, also applicable with PCBs, will amplify these differences.

Determination of heat spreading performance and limits of 3D-MIDs

The foregoing comparison already indicated that heat spreading on 3D-MIDs is worse than on PCBs. However, a thermal management design, which focuses on the circuit carrier for component cooling, requires a more accurate modelling of the heat transport.

The 3D-MID is supposed to transport heat only by means of convection and radiation to the ambient environment, as is visualised in Figure 6-6. The heat spreading and constriction behaviour of 3D-MID copper layers, consequently, has to be investigated under convective and radiative heat transfer, only.

Figure 6-6: Heat transfer from 3D-MID circuit carrier by convection and radiation

50100150200250300350400450500

5 10 15 20 25 30 35

The

rmal

res

ista

nce

[K/W

]

Thickness of copper layer tCu [μm]

tsub=0.2mmtsub=1mmtsub=1.55mmtsub=2mm

tsub= 0.20mmtsub= 1.00mm

tsub= 2.00mmtsub= 1.55mm

tsubtCuQRth_Cu

Rth_sub

Conduction

Convection& Radiation

3D-MID

DeviceQ

Tambient

174 Chapter 6

Heat spreading model

The influence of the low thickness of the 3D-MID copper layers on the heat spreading and, hence on the convective heat transport to the ambient has been calculated. The calculation uses the thermal spreading resistance model derived by Lee et al. [LSM95] which describes the heat spreading and constriction resistances for rectangular copper plates, shown in Figure 6-7.

Figure 6-7: Configuration of heat spreading model

A uniform heat flux enters the top surface A1 and leaves the copper plate A2 through one surface where a uniform heat transfer coefficient hc is applied. The remaining surfaces are assumed to be adiabatic in the model. The substrate material is neglected for simplicity. The plate’s total thermal resistance under the foregoing assumptions is now obtained as Rtot=Rsp+Rconv. Where Rsp is the maximum spreading resistance derived by Lee and Rconv is the convective thermal resistance Rconv=1/hc·A2.

The maximum temperature increase at face A1 has been calculated for the different edge length s of the heat spreader A2 and for different copper thickness levels tCu. The results are shown in Figure 6-8, where the temperatures have been normalized to the maximum temperature of a 35μm thick copper plate A2 of infinite size for a better visibility. The calculation uses a concentrated heat source A1 of edge length 1x1mm with a load of P=1W.Two mean heat transfer of hc1=6W/m²K and hc2=12W/m²K have been used for this illustration and a vertical heated plate is assumed as spatial orientation [Co02].

The chart shows that large maximum temperature increases appear when thin copper tracks with 5μm and 10μm thickness are used instead of the 35μm copper layers, which is caused by the increased spreading resistance of the thinner copper plates. However, it is also noticeable that a significant decrease of the maximum temperature can be achieved by increasing the copper surface of the 10μm plate. An increase from an edge length of 20mm to 40mm reduces the temperature by a factor of two when using the prior model.

A2

s

A1

qtCu


Figure 6-8: Normalized temperature increase of plate model over heat spreading area for different copper layer thicknesses

It can further be noticed, that the influence of the heat spreader size is more pronounced with improved convective heat transport to the ambient as can be seen from Figure 6-8 (b).

Numerical and experimental results

Additional practical measurements and stationary thermal FEM simulations have been used to determine the influence of the copper layer variation on real substrates by considering natural convection and radiation on vertical plates oriented in free space. The input parameters of the experiments are given in Table 6-2.

Table 6-2: Test specimen configuration for heat spreading investigation

Plate dimensions

[mm²]

Substrate material

Substrateconductivity

[W/mK]

Copper thickness

[μm]

Copper conductivity

[W/mK]

Loadconfiguration

Specimen parameters

30x3040x4060x60

FR-4 0.25103570

394SMT 2512 power resistor

Pload=1W

A load of P=1W has been applied to the centre of each specimen. Temperature dependent heat transfer coefficients have been used and radiation has been applied with an emission coefficient of ε=0.88, to match the measurements’ boundary conditions. Figure 6-9 shows a sample configuration with the power resistor attached to a 40x40mm² PCB with 35μm copper. The left picture shows an IR picture of the practical measurement and the corresponding FEM simulation is given on the right hand side.

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

10.0

10 20 30 40 50 60 70 80

Nor

mal

ized

max

imum

tem

pera

ture

in

crea

se a

t pla

te A

1

edge length s of heat spreading area [mm]

5um Cu

10um Cu

35um Cu

tCu=5μm

tCu=10μm

tCu=35μm

(a) h=6 W/m²K (b) h=12 W/m²K

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

10.0

10 20 30 40 50 60 70 80

Nor

mal

ized

max

imum

tem

pera

ture

in

crea

se a

t pla

te A

1

edge length s of heat spreading area [mm]

176 Chapter 6

Figure 6-9: Test specimen used for heat spreading, left: practical measurement; right: FEM simulation (35μm Cu, 40x40mm²)

The results of the investigations are summarized in Figure 6-10, which shows the maximum temperature rise ΔT plotted over the copper layer thickness for the different PCB samples. The discrete points represent the measured values and results obtained from the FEM are given as lines. The charts show a significant influence of the copper thickness on the maximum temperature, as expected from the analytical model.

Figure 6-10: Maximum temperature rise ΔT over copper thickness for different copper areas

It can also be seen that enlarging the copper area decreases the maximum temperature, even for the specimen with low copper thickness of tCu=10μm, also identified with the analytical model (Figure 6-8).

However, large copper surfaces are already required for cooling single power sources ofP=1W which negatively influences the ability to maintain low component distances for compact circuit layout, discussed in Chapter 5. It can also be seen from the charts, that a further increase of copper areas only slightly contributes to decreased component temperatures at tCu=10μm, determined by the increased spreading resistance. It can be concluded that multiple components with these losses can no longer be reasonably cooled with the 3D-MID surfaces only.

Summary

The following limitations can be summarized for the heat transport with standard 3D-MID circuit carriers:

Tambient=27°C

60°C

50°C

40°C

30°C

10

30

50

70

90

110

0 20 40 60 80Tem

pera

ture

ris

e ΔT

in K

Copper thicknes in μm30x30 mm² 40x40 mm² 60x60 mm²


Perpendicular heat transport: Low substrate thicknesses are required for improved perpendicular heat transport, but counteract with the demand on mechanical stability of the 3D-MID.

In plane heat transport: Increased copper layer thickness is needed for low in-plane thermal resistances but is normally not available on 3D-MIDs. Power sources of P=1W already need large heat spreading areas (A>9cm²) which conflicts with the demand on compact circuit routing on a single plane, required to handle increased power levels on 3D-MIDs (Chapter 5). Further, cooling of systems with increased loss densities is not available with the 3D-MID only.

Both aspects will also influence the implementation of other thermal management solutions on 3D-MIDs. Hence, 3D-MID specific approaches are required and their thermal boundaries have to be derived. This will be performed in the sections to follow.

6.3.2. Layout and geometry optimisation

Layout optimisation

The foregoing section has shown that there is a clear limitation in the heat transport with the 3D-MID circuit carrier only. However, optimizing the component placement and circuit layout can be used to influence the temperature of individual devices to some extent, which has already been addressed in a variety of PCB-based applications.

Different solutions to reduce hot-spots by means of the circuit artwork design and component arrangement have been presented in the literature [Jo07], [FL09], [Pa05]. One is to locate components with excess losses in close proximity to external heat sinks [Jo07] or cold plates. Other solutions try to modify component positions and circuit layout to maximize copper areas for improved convective cooling of the circuit carrier with given layout space available [FL09] (Figure 6-11). [Jo07] uses performance indicators to identify components with high loss- and low loss-density and locates them in close proximity whenever it is possible to use the latter components to act as heat exchanger, e.g. the chassis of a large passive electrolytic capacitor is used as heat sink.

Figure 6-11: Example 3D-MID layout options to influence converter level thermal management

The presented approaches require knowledge of losses in the crucial components and the interactions between components, i.e. the thermal pathways, have to be known as well.

(a) Compact layout (b) Distributed layout

178 Chapter 6

Component losses can be determined by loss analysis or with the help of practical measurements. The component interaction depends on the circuit layout and on the material properties of the circuit carrier and is therefore quite complex to model. Numerical approaches, like Finite Element Modelling or the Finite Difference Technique, can be used as effective tools to model the resulting thermal pathways dependent on the physical circuit layout [FL09], [AN12], [Pa05], [Ja94].

Applying any of the prior presented approaches to 3D-MIDs one has to consider the limited heat spreading and conduction performance as well as the reduced flexibility in the layout generation. Chapter 5 has already shown that component positioning and layout changes might influence the electrical behaviour and EMC of power converters when trace parasitics are affected, especially when fast transients, e.g. high di/dts at MOSFET switching, appear.

A trade-off between circuit layouts for improved electrical- as well as thermal-performance is therefore required when the circuit layout is utilized to improve the converter level thermal management. This trade-off analysis can be supported by combined thermal- and electrical simulations that determine component temperatures and circuit layout parasitics simultaneously, which have been demonstrated for power electronic modules applications in [Ch01], [Jo02].

Geometry Optimisation

Not only the circuit artwork influences the heat transport between components and the environment, but also the entire geometry of the circuit carrier does.

3D-MIDs offer different options to influence component temperatures by changing the substrate geometry. The simplest solution is to change the circuit carrier’s aspect ratio to influence component positions and temperature distributions on the circuit carrier, as also possible with rigid PCB technology [Jo07], [ZJL97].

Besides, the entire shape can be modified in three-dimensions for improved heat transport between components or to create cooling ducts directly with the substrate. A similar approach has already been discussed for flexible PCBs in [Jo07].

Figure 6-12 gives an overview of possible geometrical changes to influence component positions on 3D-MIDs.


Figure 6-12: Overview of 3D-MID geometry shaping possibilities to influence converter level thermal management

Ultimately, the circuit carrier surface geometry can also be (selectively) re-shaped for improved heat transport. Chapter 5.5 has already introduced solutions how to modify the substrate surface for improved current carrying capacity by increasing the surface area in 3D, shown in Table 5-8: case 1. The same principle can be applied for thermal reasons and has recently been investigated by [Le1206]; the authors achieved a 40 percent increased copper surface compared to a flat structure, leading to improved heat transfer to the ambient. An example is shown in (Figure 6-13 (a)).

In addition, the entire substrate cross section can be modified with 3D-MIDs to improve cooling. For example, [Le1206], [LHS08] propose an implementation of water cooling channels directly in the substrate material (Figure 6-13 (b)) for the cooling of a high-power LED.

Figure 6-13: 3D Modification of substrate (a) surface, (b) cross-section

It has to be noted, that the re-shaping of the 3D-MID substrate requires adapted and often more complex moulding tools and the resulting manufacturing efforts have to be considered. Hence, layout flexibility given by the LDS process gets undermined and a trade-off between cooling performance, tool-costs and layout flexibility is required.

The extent of influencing component temperature with the 3D-MID circuit carrier geometry and its layout will be discussed by means of a case study power converter in Section 6.4.

(a) 2D-geometry: aspect ratio (b) 3D-geometry

(a) 3D-surface shaping (b) 3D-substrate shaping

180 Chapter 6

6.3.3. Integration of extra thermal pathways

Extra thermal pathways, like solid copper bars or heat pipes that are over moulded are in general an option with 3D-MIDs. These structures provide high thermal conductivities due to their material characteristics or because of the heat pipe principle, with evaporation and condensation [Zu01].

However, both methods require a complex over-moulding of solid metal structures that have to be placed and shaped in three-dimensions which again limit the variance of the 3D-MID geometry and significantly increase production efforts. Alternatively, those could be mounted as extra cooling structure on the 3D-MID surface, whereas similar constraints as for external heat sink attachments appear, as will be discussed in Section 6.3.5.

The integration of extra thermal pathways is therefore not considered here.

6.3.4. Substrate material modification

In Chapter 5.2.1 a comparison has been drawn between conventional PCB substrate materials and substrates available for 3D-MIDs in the light of mechanical and electrical properties as well as thermal stability.

However, the thermal conductivity of the base material has not yet been discussed. PCB substrate materials do not provide significant contribution to heat removal, as already shown in Section 6.3.1. Whenever enhanced heat transport is required the copper layers, thermal vias or extra thermal pathways are used (Section 6.3.1-6.3.3). A substrate material enhancement has thus not been considered in the PCB technology for a long time.

This has changed with the widespread availability of high-power LEDs which has lead to the intensified use of Metal-Core-PCBs (MC-PCBs), because of the high loss density of high-power LEDs [Fa12]. Enhanced dielectric materials with thermal conductivities of λ=0.8-2.2 W/mK [ORA09], [Pe04] have been developed to maintain lower thermal resistances than FR-4 based MC-PCBs. However, MC-PCB dielectrics are only used as very thin substrates and are not designed for the usage in conventional PCB technology with considerably larger substrate thickness.

Enhancing the thermal conductivity of 3D-MID substrates is in principle possible by using thermally conductive polymers with ceramic fillers instead of standard polymers. In [HF11], [Ho11] Polyamide 6 (PA6), Polyamide 66 (PA66) and Polyphtalamide (PPA6) with thermal conductivities of λ=0.6-2 W/mK have been successfully investigated for their use with the 3D-MID hot-embossing technology. The material enhancements contributed to enhanced solder stability, reduced CTEs and improved heat transport from components, e.g. high-power LEDs.

To the author’s knowledge, no thermally conductive polymers have been introduced to be compatible with the LDS 3D-MID process, so far. Reasons are the relatively high filler


contents required for enhanced thermal conductivity which stands in contrast to required fillers for the LDS process and those for providing mechanical stability.

Consequently, no thermally enhanced substrate materials are usable with the LDS process, so far.

6.3.5. External cooling structures: Heat sinks

Heat sinks are external structures which are used to transport heat by means of convection and radiation to the ambient environment. The basic idea behind a heat sink is to build a structure made of thermally conductive material that provides large surface areas to improve convective and radiative heat transport but without occupying large amount of space. Heat sinks can either be attached to individual components as small SMT parts (Figure 6-14(b)) or they can be used on the converter level thermal management when connected to the entire geometry (Figure 6-14(a)).

In conventional PCB based solutions, heat sinks are typically connected to the backside of the board and thermally connected with thermal vias and a thermal interface material to provide low thermal resistances and electrical isolation (Figure 6-14 (a)). Other solutions exist where heat sinks are attached to the side surfaces of the PCB, with circuit layers or extra heat spreading layers connected to the heat sink for low thermal resistances [JPJ93]. [Ge05] uses a full enclosure heat sink to maximize conductive heat transport from the power sources.

Figure 6-14: Heat sink application solutions in printed circuit board technology

The attachment of heat sink structures on 3D-MIDs is generally more restricted than with PCBs, due to the limitation in conductive heat transport (Section 6.3.1) and gets further challenged when complex three-dimensional shapes are present. This leads to the following issues when conventional heat sink technology is considered for 3D-MIDs:

(a) Board heat sinks (b) Component heat sinks

182 Chapter 6

Heat conduction: A low thermal resistance connection of heat sinks is challenged by the lack of multi-layer technology to add heat spreading layers and the restrictions in using vias with 3D-MIDs.

Assembly: Complex three-dimensional designs make the application of conventional extruded metal heat sinks nearly impossible. Using multiple heat sinks on the substrate, however, implies increased part costs and assembly efforts. This limitation also appears when small SMT heat sinks are considered for the cooling of individual components. The realisation of adapted metal heat sinks is therefore a difficult and costly task.

A novel concept to use converter level heat sinking on 3D-MIDs that circumvents the increased perpendicular thermal resistance of 3D-MIDs and that allows a simplified attachment even on complex three-dimensional geometries will be presented in Section 6.5.

6.3.6. Constraints for 3D-MID-based LED-lighting applications

The foregoing discussion has shown that different constraints appear for the realisation of an effective thermal management solution for LED-lighting systems with power converter on 3D-MIDs.

They can be classified according to technology- and application-based constraints:

Technological based constraints: The successful application of 3D-MID requires a high level of functional integration and the realisation of novel functions in a single “multi-functional” 3D-MID, as introduced in Chapter 2 and 3. It is therefore essential, to keep the number of components as low as possible. However, reduced in plane heat conduction limits the ability to use the 3D-MID circuit carrier as single thermal management component. External heat sinking is challenged by considerably large substrate thicknesses, required for mechanical stability, limitations in using thermal vias and the complexity of creating complex three-dimensional heat-sinks.

Application based constraints: Modern three-dimensional LED-lighting systems are planned to fulfil photometric and spatial design requirements defined by the lighting application. The number and distribution of the LEDs is therefore given and influences the implementation and physical construction of the thermal management. Although LEDs exhibit high efficiencies compared to incandescent light sources, still 70-80 percent of the LED power is exhibited as losses (Chapter 1.1) and challenge the thermal management implementation. In addition, full surrounding heat-sinks, as presented by [Ge05], are not usable for an optical system where light has to be emitted.

Table 6-3 summarizes the identified design constraints that contradict with the available thermal management solutions. The table shows the available thermal management solutions on the left side and constraints that exist in their practical realisation on the top side.


Table 6-3: Influences of constraints on available thermal management solutions

Thermal Management

Solution

Technology constraints Application constraints

Circuit layoutproduction

Interconnectiontechnology

(3D-)assembly

LDS processrequirements

Exteriordesign

Opticalrequirements

Heat flow perpendicular Via availability

Heat spreading

Layer thickness&

Layer number

Soldering without solder

resist

Laser structuring

time

Thermal pathway

enhancementMoulding tools

Layout optimisation Layer number Via availability LED

position

Geometry Optimization Moulding tools LED

position

Component heat sinks Pick & Place Light-output &

-distribution

Converter heat sinks

Layer thickness&

Layer numberVia availability LED

positionLight output &

-distribution

Substrate material

enhancement

Filler compatibility

6.4. Thermal management with the 3D-MID circuit carrier –a case study

The choice of the cooling solution is strongly related to the apparent losses and the loss density in the application. In the following, the case study boost-converter introduced in Chapter 5.4 is used to identify crucial components that exhibit the highest losses. In addition, the LEDs that are driven by the power converter are included in the loss analysis. In this case, eight high-power LEDs with a total power consumption of PLED=14W are supplied.

A breakdown of the complete system losses is shown in Figure 6-15. The converter specification has been introduced in Table 5-5 and the loss analysis is performed in Appendix B. Further, the LED efficiency has been assumed to be ηLED=15 percent [QLH09].

184 Chapter 6

Figure 6-15: Loss breakdown of case study converter with LED-section

The loss breakdown delivers the following aspects which determine the selection of thermal management solutions:

High-power LEDs: The LED losses highly exceed the losses that appear in the LED-driver. Section 6.3.1 has shown that heat spreading is strongly limited on 3D-MIDs, even for single 1 Watt power sources. The basic 3D-MID is therefore no reasonable cooling option for high-power LEDs. Other solutions, like substrate material modification are not possible with LDS based 3D-MIDs and extra thermal pathways can only be implemented at cost of production efforts and restriction of design flexibility. The remaining option is to use external cooling solutions for the LED section.

LED-driver: In contrast to the LED-section, the power converter losses are low and they are in a range still manageable with the 3D-MID as single thermal management component. However modified circuit layouts with increased heat spreading areas are required, as the case study layouts of Chapter 5 have been optimised to achieve compact layouts with low loop inductance.

Hence, LED-driver layouts with enlarged copper areas around crucial components are required to maintain a sufficient heat- spreading and -transport to the ambient environment. In the following, the use of the 3D-MID circuit carrier to maintain LED-driver cooling will be described on the basis of a case study system.

An approach to use an adapted external cooling structure that directly transports dissipated heat from the components will be presented in Section 6.5. It extends the power limits set by 3D-MID-based cooling whilst keeping the number of components low.

0.49 0.21 0.29 0.051.03

11.90

0

2

4

6

8

10

12

Inductor MOSFET Diode Copper Traces

Totalconverter

LEDs

Com

pone

ntlo

sses

[W]


6.4.1. Design of circuit carrier based thermal management

The thermal management design of a 3D-MID with a single copper layer is based on heat spreading, as a function of layout and geometry (Sections 6.3.1 and 6.3.2), and on convective- as well as radiative- heat transport to the environment. It is also the thermal management realisation that can be realised with least manufacturing efforts on 3D-MIDs.

Figure 6-16 summarizes the boundary conditions and heat transfer modes that appear in the considered system configuration.

Figure 6-16: Boundary conditions for circuit carrier based thermal management

A case study LED-driver will be used to derive the possibilities of 3D-MID-based component cooling and to determine its limitations.

The thermal-design that is used here contains the following stages:

Component loss- and heat-spreading analysis: After the electrical design of the converter, component loss analyses are performed to determine the crucial components that exhibit the majority of the losses. Special care has to be taken of these components in the design of the subsequent circuit layout. The individual component losses are then compared with the heat spreading performance investigation of Section 6.3.1 to get an indication if the MID is feasible for component cooling and to determine how large the copper surfaces are required to be.

Layouting supported by FEM simulation: An initial layout design is used which’s size is mainly determined by component size and routing requirements. FEM simulation of the entire layout is performed next, to determine if the target specification on component temperatures are fulfilled. The initial design can directly be varied by using parametric simulations that change component distances and copper layer dimensions to obtain improved component temperatures.

Measurement on prototype converter: Finally, experimental verification is performed on a prototype system to prove simulation results.

6.4.2. Case study implementation

The analysis, the design as well as the realisation of 3D-MID-based thermal management will be evaluated in the following by means of a case study LED-driver. The LED-driver used

Conduction

Convection& Radiation

3D-MID

DeviceQ

Tambient

186 Chapter 6

here is a two-branch buck-boost converter with inductive power sharing comparable as introduced in Chapter 4.3.2. Figure 6-17 repeats the topology with the relevant components for a better understanding. The converter specification and component parameters are given in Appendix C.

Figure 6-17: two-branch buck-boost converter topology used as case-study

The system’s thermal design is supposed to work under the environmental conditions to follow:

A single and 10μm thin copper layer is available for routing and the thermal management.

Heat transfer to the ambient is performed by natural convection and radiation only.

The ambient temperature ranges from -40°C to +80°C.

Convection is used as heat transfer mechanism in modern head- or taillight systems, as they are open systems that allow air exchange for reasons of cooling, de-thawing and for pressure exchange. In addition, no influence of external housing on convection and radiation is considered, here. Due to simplicity, only the power converter switching cell components are focused for the thermal management design. Their maximum temperature rating is given in Table 6-4.

Table 6-4: Maximum component temperatures

MOSFET Q Diodes DBx, DFx Inductors Lx

Maximum temperature Tmax [°C] 175 150 210

Component loss analysis

In a first step, power converter loss analysis is performed for the main components involved in power processing. This contains the branch- and freewheeling-diodes, the MOSFET and the branch inductors. Table 6-5 summarizes the main converter losses of the topologies at minimum-, nominal- and maximum- input voltage. The loss analysis is generally described in

Vin

Q

L1

C1

L2

C2DB1 DB2

DF1 DF2


Appendix B and has been performed with input parameters and converter specification summarised in Appendix C, Table C-3.

Table 6-5: Breakdown of main converter losses Plossx over input voltage

Input voltageVin

[V]

Branch diodesDBx

[W]

Free-wheeling diodes DFx

[W]

MOSFET Q

[W]

Inductors Lx

[W]

Total losses[W]

8.5 0.67 0.27 0.25 0.27 1.46

14 0.4 0.27 0.24 0.2 1.11

17 0.33 0.27 0.27 0.19 1.06

It can be derived from the table, that the majority of the losses is concentrated in the semiconductor components. Especially, the branch diodes show the highest losses with 0.4 Watts at nominal input voltage. The total converter losses are in the range of about 1 to 1.5 Watts, depending on the input voltage.

Heat spreading analysis

The heat-spreading investigations of Section 6.3.1 have shown that a 3D-MID circuit carrier is able to keep the temperature rise of a single 1 Watt power source below ΔT=90K with convective and radiative heat transport only. Similar losses appear for the case study LED-driver, but the load is distributed to multiple components instead of a central heat source.Hence, the 3D-MID circuit carrier should be able to maintain even lower temperature rises, when an adapted component layout with efficient heat spreading areas is implemented.

The heat spreading model of Section 6.3.1 will be used in the following to get a first indication if the 3D-MID copper surfaces are feasible to maintain individual component cooling

If it is assumed, that each component is centrally attached to an individual copper area and no cross-coupling exists, a system configuration like exemplary shown in Figure 6-18 appears. On the basis of this strongly simplified model, a first estimation can be made if the 3D-MID copper surfaces are sufficient for component cooling. Furthermore, the order of magnitude of the resultant copper area sizes A=sx² can be determined.

188 Chapter 6

Figure 6-18: Example: Simplified model to determine copper area size for heat spreader cooling

In a first step, the component package resistances and their worst-case losses (Table 6-5) can be used to calculate the maximum allowed thermal resistance Rtot of each copper layer for a given temperature rise ΔT. Rtot is the sum of the copper’s spreading- Rsp and convection resistance Rconv to the ambient, as defined in Section 6.3.1.

Table 6-6 shows the resulting maximum thermal resistance Rtot allowed for the semiconductor devices. The values have been calculated for the given worst case losses Plossx and with the given components’ junction to case resistances Rth_j_c. Two cases have been considered:

Component temperature rises ΔT to their individual maximum ratings (Table 6-4)have been allowed at Tambient=80°C

A temperature rise of ΔT= 50K has been allowed at Tambient=80°C

Table 6-6: Maximum allowed thermal resistances Rtot component to ambient

Branch diodeDBx

(SMA package)

Free-wheeling diode DFx

(SMA package)

MOSFET Q

(SO-8 package)

Maximum losses per component Plossx [W] 0.335 0.135 0.25

Component thermal resistance Rth_j_c [K/W] 25

Maximum Rtot for T= Tmax [K/W] 184 484 355

Maximum Rtot for ΔT=50K [K/W] 124 345 175

The heat spreading model of Section 6.3.1 can now be used to calculate each copper area size required to maintain the specified thermal resistances Rtot. Table 6-7 shows the calculated edge length sx of each component’s heat spreading area and for the two different configurations of Rtot.

The convection coefficients hc, and therefore Rtot, have been calculated iteratively in dependency of the copper area size. Further, a vertical plate orientation has been assumed for the calculations. The correlations used to calculate the heat transfer from vertical plates are given in Appendix C.

s1

Ploss1 tCu

Tambient

Rconv1

=

Rsp1

s2

Ploss2 tCu

Tambient

Rconv2

=

Rsp2

s3

Ploss3 tCu

Tambient

Rconv3

=

Rsp3

s4

Ploss4 tCu

Tambient

Rconv4

=

Rsp4

sc1

sc3

sc2

sc4


Table 6-7: Estimation of heat spreading edge length sx for purely convective cooling of single copper surfaces

Branch diodeDBx

Free-wheeling diode DFx,

MOSFET Q

Edge length sx for T= Tmax [mm] 19 8.7 10.3

Edge length sx for ΔT=50K [mm] 31 12 20

It can be seen from Table 6-7 that an increase in the heat spreading areas can be used to obtain decreased component temperatures, as already discussed in Section 6.3.1. However, maintaining low temperatures rises of ΔT=50K already requires comparably large copper areas which conflicts with the requirement on compact power converter layout, discussed in Chapter 5. Moreover, it has been observed in the analysis, that the heat spreading performance of the 10μm thin copper layer reaches its limits for maintaining a ΔT of 50K among the branch diodes DBx for the given input configuration.

It has to be noted that the foregoing approach is considered as a first estimation regarding potential copper sizes, due to the assumptions made. In the following, circuit layouting combined with FEM will be performed on the basis of the derived copper areas. FEM simulations are used to model thermal couplings between the components and to account the problem of several heat sources that are connected to multiple copper areas on a common substrate, given in real circuit layouts.

Layout concepts

Three different layouts will be considered to analyse if the 3D-MID circuit carrier is able to provide sufficient heat transport to the environment for component temperatures below their maximum ratings. The layouts are created as follows:

Two layouts, with different component positions and circuit carrier‘s aspect ratio, are used to determine their influence on component temperatures on 3D-MIDs

The layout sizes will be used as compact as possible to maintain a low space consumption and short laser time in the manufacturing process

A third layout with increased surfaces will be used for reasons of comparison to the two compact layouts

The component temperatures will be evaluated by means of FEM simulation and the solution with the lowest component temperature will be selected for practical verification.

Layout 1 – Compact layout

Layout 1 is shown in Figure 6-19; it is realised as compact layout structure with symmetrical orientation of the two inductor branches and their related components. The circuit carrier is a flat plate for simple assembly and has a portrait orientation. The component position is determined by the power flow through the converter. No special heat spreading areas have been implemented for the cooling of the crucial semiconductor components that exhibit the

190 Chapter 6

majority of the losses. Only the surfaces that were available have been filled with copper for heat spreading.

Figure 6-19: Layout 1 – (a) 3D model and (b) top-view of layout with considered components

Layout 2 – Optimised compact layout

Layout 2 has been designed for improved heat spreading from the semiconductors when compared to Layout 1. Figure 6-20 shows the layout which has a slightly increased footprint area. Again, a flat plate has been used as circuit carrier, but the aspect ratio has been changed to landscape, that allows a change of component positions and heat spreading areas. The branch inductances L1 and L2 have been moved to the circuit carrier boundary and the diodes have been rearranged to surround the MOSFET. Furthermore, the copper areas have been adjusted in a manner that approximately the same heat flux density is maintained in each heat spreading area. Consequently, the distances between components have been slightly increased and it was taken care that the components are, whenever possible, centred on the copper surface for improved heat spreading.


Layout 3 – Non-compact layout

A third layout is used to show the influence of increased heat spreading areas on the component temperatures for reasons of completeness. Layout 3 is based on Layout 1 where each heat spreading area has been increased by a factor of two. Hence, the entire structure occupies twice the surface of Layout 1. The layout is visualised in Figure 6-21.

L1 L2

DF 1

DF 2

DB

1

DB

2

Q

(a) (b)

QDF2

DB2DB1

DF1

L1 L2

(b)(a)



Table 6-8 shows the parameters of the three layout variants with related copper areas used for component contacting and heat spreading. Furthermore, the calculated heat flux is given for each surface area.

Table 6-8: Comparison of heat spreading areas and calculated heat fluxes

Copper surfaces actively used for heat spreading Heat flux per area

Contacting areas:

L1-DB1-DF1

L2-DB2-DF2

[mm²]

Contacting area:

DF1-CoutDF2-Cout

[mm²]

Contacting area:

DB1- DB2-MOSFET

[mm²]Total[mm²]

Contacting areas:

L1-DB1-DF1

L2-DB2-DF2

[W/cm²]

Contacting areas:

DF1-CoutDF2-Cout[W/cm²]

Contacting area:DB1- DB2-MOSFET[W/cm²]

Layout 1 103 38 107 248 0.21 0.18 0.38

Layout 2 64 29 125 218 0.33 0.23 0.33

Layout 3 199 79 225 503 0.11 0.09 0.20

6.4.3. Case study results

Finite Element Model

The component heating has been simulated by means of FEM analysis for all layout versions and for different operating conditions. Simulations have been performed at nominal input and at minimum input voltage, for reasons of comparison. Finally, a worst case simulation has been performed at minimum input voltage Vin=8.5V and maximum ambient temperature Tambient=80°C. Table 6-9 summarizes the simulation results. The simulation input parameters and material properties are given in Appendix C, for a better understanding.

L1 L2

DF 1

DF 2

DB

1

DB

2

Q

(a) (b)

192 Chapter 6

Table 6-9: Simulated maximum component temperatures at nominal and minimum input voltage, as well as worst-case simulation for layouts 1-3

Normal operation: Vin=14V and Tambient =30°C

Substratesurface area

[cm²]

Coppersurface area

[mm²]

Component temperatures [°C]

L1 L2 DF1 DF2 DB1 DB2Q

Layout 1 8.5 248 64.3 65.5 81.9 83.3 90.2 89.6 85.5

Layout 2 9.7 218 65.2 64.9 80.4 80.2 84.2 83.8 77.4

Layout 3 16.6 503 55.5 54.9 66.3 65.0 75.8 74.1 68.2

Minimum voltage operation: Vin=8.5V and Tambient =30°C


[cm²]

Coppersurface area

[mm²]



Layout 1 8.5 248 75.2 76.2 91.9 94.7 110.2 109.4 96.5

Layout 2 9.7 218 72.3 71.9 89.6 90.6 102.5 101.6 88.7

Layout 3 16.6 503 65.8 66.7 76.2 77.5 96.1 95.3 79.8

Worst-case operation: Vin=8.5V and Tambient =80°C


[cm²]

Coppersurface area

[mm²]



Layout 1 8.5 248 119.8 120.1 135.9 137.2 155.8 155.1 142.4

Layout 2 9.7 218 124.8 123.9 139.8 140.4 151.7 151.3 137.6

Layout 3 16.6 503 109.6 110.0 120.2 121.5 142.3 141.2 127.6

It can be derived from the results that the highest component temperatures appear for the branch diodes DBx, as expected from the high individual losses and the comparably high thermal resistance of the SMT package.

A comparison of Layouts 1 and 2 does not exhibit significant temperature deviations, as both have been designed to keep within maximum temperature ratings of components at small layout footprints. However, it can be seen from the contrasting that Layout 2, which has been improved for heat spreading, achieves lower component temperatures of about ΔT=6K than Layout 1, when compared at nominal input voltage.

At worst-case conditions, both layouts slightly exceed the maximum temperature rating of the branch diodes (Tj_max=150°C), whereas Layout 2 still performs better with Tmax=151.7°Cinstead of Tmax=155.8°C.


Increasing the layout size could be used to further decrease component temperatures (ΔT=15-20K), as shown with the results of Layout 3 and with the heat spreading analysis in Section 6.4.2. This effect is limited by the low copper layer thickness and comes at greatly increased efforts in creating large copper areas on laser structured 3D-MIDs. Furthermore, component distances will get greatly increased, affecting switching performance and negatively influencing the total converter volume and its volume utilisation.

FEM and measured results

A prototype system according to Layout 2 has been built and tested to prove the numerical results of the FEM. Layout 2 has been used as it shows the best performance at a compact layout footprint. The prototype specification is given in Appendix C and the layout has been created on a single 10μm copper layer corresponding to the simulation parameters.

The converter has been vertically oriented and only free convection and radiation were available for the heat transfer to the ambient. The component maximum temperatures have been measured by means of IR measurement. Figure 6-22 shows the resultant component temperatures and the temperature distribution in the converter when operated at a nominal input voltage of Vin=14V. The ambient temperature has been constant Tambient=30°C.

Figure 6-22: IR images of case study LED-driver under normal operation Vin=14V, Tambient=30°C

Figure 6-23 shows the corresponding result from the FEM analysis with the same input parameters for reasons of comparison.

It can be seen from the results, that a quite uniform temperature distribution is achieved in the entire layout. Among the semiconductors temperature deviations of below 10K appear, asexpected from the equal heat fluxes densities (Table 6-8). A comparison to the results of the FEM simulation (Table 6-9 and Figure 6-23) shows a good accuracy for the FEM model with deviations of about 10K among the semiconductors.

Nr. Temp. [°C]

M1 51.3M2 52.5M3 70.1M4 68.0M5 79.5M6 83.3M7 65.1

80°C

70°C

60°C

50°C

40°C

MOSFETL1 L2

Cin

Diodes branch 1 Diodes branch 2 30°C

194 Chapter 6

Figure 6-23: Simulation results of case study LED-driver under normal operation Vin=14V, Tambient=30°C

The higher simulation temperatures found for the inductors Lx can be ascribed to the simplified thermal model which neglects the connection of the ferrite cores to the board. Further, the connection of the gate and source pad of the MOSFET has not been considered, which contributes to slightly increased simulation temperatures of the MOSFET and the free-wheeling diodes.

Summary

The case study shows that adjusted copper areas and improved component positioning can also be used with 3D-MIDs to improve heat spreading and hence component temperatures. However, increased surface areas are required. This stands in contrast to the investigated compact 3D-MID circuit layouts with low parasitic inductances of Chapter 5. A trade-off decision between electrical and thermal design is therefore necessary. This can be found by combining the thermal FEM with the parasitic extraction simulation, as has been presented by [Ch01], [Jo02] for power modules.

Besides, it can already be seen from the case study that the performance of the 3D-MID-based heat transport to the ambient is strongly limited, even when improved heat spreading areas are implemented. Higher loss densities, as the observed ones, require additional cooling solutions that have to be implemented.

6.5. Integrated Reflector Heat Sink

Sections 6.3.1 and 6.4 have shown that copper areas with high thickness and increased size are required for improved circuit carrier-based component cooling. In addition, high thermal resistances appear for the attachment of external cooling structures at the circuit carrier’s backside (Sections 6.3.1). Attaching a heat sink to the front-side, however, is challenged by the presence of an optical system and by the three-dimensional shape of 3D-MIDs (Section 6.3.5).

In this section, the implementation of a novel cooling approach for LEDs on 3D-MIDs, with the so-called Integrated Reflector Heat Sink (IRHS) [TP11] will be described. It allows enhancing the passive heat transport from the LED-section of 3D-MID-based LED-lighting

85 C

70 C

55 C


systems. The general idea of using the IRHS, however, can be modified and used in a variety of application scenarios besides LED-lighting.

6.5.1. Basic idea

Figure 6-24 (a) visualises a cross section of a conventional LED-segment with heat sink attached to the circuit carrier backside. If it is assumed that the only heat exchange with the environment is performed by the heat sink and that a uniform temperature distribution appears over the component cross-sections, the simplified thermal network shown in Figure 6-24 (a) can be used to determine the structure’s thermal resistance.

Figure 6-24: Cross-section of LED-segment with conventional heat sink (a) and reflector heat sink principle (b) and related simplified thermal resistance network

An example system, with the foregoing thermal-network and -resistances given in Table 6-10achieves a total thermal resistance of Rth=38.1K/W. It can be seen from Table 6-10, that the substrate layer dominates the total resistance, because no thermal vias are used, and hence significantly limits the effect of heat sinking.

Table 6-10: Example configuration for thermal resistance calculation

Copper layer

Interface layer

Substratelayer

LED-package Heat sink

A [cm²] 4 - -

t [mm] 0.01 0.3 2 - -

λ [W/mK] 394 0.6 0.28 - -

Rth [K/W] 6.4E-5 1.25 17.86 9 10

The basic idea of the IRHS is to avoid this high resistive thermal pathway from the LED package through the 3D-MID. The IRHS is furthermore directly attached to the front-side of the 3D-MID where the LEDs and the circuit artwork are located, as shown in Figure 6-24 (b).

It can be seen from the cross-sectional view that the heat, dissipated by the LED-chip, is transported to the package’s bottom and is then spread in the 3D-MID’s copper layer. The IRHS bottom surface can be designed to create maximum contact surfaces to the spreader and therefore to decrease the thermal resistance. A thin thermal interface connects the IRHS with the heat spreader. Due to the avoidance of the high resistive thermal pathway through the substrate, the thermal resistance of the LED-segment in Figure 6-24 (b) can be nearly halved,

Copper

IntegratedReflectorHeatsink(IRHS)

Substrate

InterfaceLED

Copper

Reflector

Substrate

Heat sink

LED

Interface

Thermal vias(optional)

= Tambient

Rth_LED

Rth_Cu

Rth_heat_sink

Rth_interface

Rth_substrate

PLED

= Tambient

Rth_LED

Rth_Cu_spread

Rth_IRHS

Rth_interface

PLED

(a) Conventional heat sink (b) Integrated Reflector Heat Sink (IRHS)

196 Chapter 6

Rth= 20.3K/W, in comparison to the conventional heat sink attachment (Figure 6-24 (a)), when the same input values are used for calculation.

Implementation challenges

The following requirements have to be fulfilled when the heat sink has to be attached to the front side of an LED-section:

The front side of the LED-section is usually occupied by a reflector or a similar optical system that is required to collect and reflect the light of the LEDs. A prospective multi-functional heat sink has to be able to integrate this function.

The heat sink should be able to be attached on complex three-dimensional shaped geometries.

The reflector shape is determined by design requirements that have to be fulfilled.

Standard aluminium extruded heat sinks cannot solve these challenges, because of:

Limited degrees of freedom, efforts and costs for three-dimensional shaping

Incapability of vapour deposition on aluminium

Proposed solution

An alternative approach is therefore suggested for the construction of the IRHS. Thermally conductive polymers are considered to be used instead of conventional metal heat sinks. The polymer heat sink can be created by injection moulding, which allows an adjustable design with contact surfaces that ideally match the 3D-MID leading to minimum contact resistances. The heat sink can be attached to the back side, but moreover directly to the front side of the 3D-MID where the heat is generated. This means for an LED-lighting system, that the already present reflector can be directly replaced with a reflector made of thermally conductive polymers and adapted surfaces for improved heat transport.

The system is therefore called Integrated Reflector Heat Sink, as it directly integrates the functions of the essential heat sink and the reflector in a single component that is shaped to ideally match the 3D-MID surface.

The IRHS used in the following is assembled as a discrete part due to reasons of availability. However, in the future a 2-component-injection moulding of 3D-MID LDS material and of thermally conductive polymers might get possible. This could be advantageously used to integrate the IRHS functionality directly into the 3D-MID.


6.5.2. IRHS construction

IRHS materials

A variety of thermally conductive plastics has been developed in the past to improve thermal conductivities which can be used for creating the IRHS. Increased thermal conductance is achieved by adding thermally conductive filler materials to the plastic matrix.

The filler materials can be divided into two groups, which are:

thermally-conductive and electrically insulating

thermally- and electrically-conductive

Figure 6-24 gives an overview of the achievable thermal conductivities of filled polymers, according to [Eg08].

Typical electrically insulating substrates, e.g. filled with ceramics like aluminium oxide (Al2O3), achieve isotropic thermal conductivities of λ=0.5-6W/mK, dependent on the filler concentration. Filler materials which are also electrically conductive, like copper or carbon nanotubes, are able to provide even higher isotropic thermal conductivities of up to λ=20W/mK.

However, their electrical conductance has to be considered in the design of the IRHS and a direct connection of the 3D-MID traces and the IRHS has to be avoided, e.g. by using insulating interface materials between both components or by finishing the 3D-MID surface with an insulating protective lacquer. As with any metallic heat sink connected to a power electronic system, possible electromagnetic interactions between circuit traces, carrying switched currents, and the heat sink, in terms of eddy currents that might be induced in the heat sink, have to be considered in the design.

Figure 6-25: Achievable thermal conductivities of filled polymers according to [Eg08]

0.1

1

10

100

The

rmal

con

duct

ivity

[W/m

K]

isotropic

anisotropic

isotropic

anisotropic

electricallyinsulating

electricallyconductive

198 Chapter 6

The IRHS material used in this work is therefore chosen as electrically insulating material. LUVOCOM 1-7904 [Le09] has been selected due to its good availability. The material has a thermal conductivity of λ=3.2W/mK.

IRHS attachment

A successful implementation of the IRHS further requires a good connection between the 3D-MID and the IRHS. The mechanical connection of both components can be solved with mounting elements, like screws or self-adhesive interface pads. In addition, mounting clips and countersinking holes can be directly integrated in the IRHS and in the 3D-MID for simplified assembly.

Nevertheless, an interface material is essential to compensate production based tolerances and surfaces roughness so that no air is enclosed between the circuit carrier and the heat sink. A variety of materials is available for interfacing, ranging from rather solid thermal pads to fluids, e.g. thermal grease. Their thermal conductivity is strongly dependent on the material thickness which should be as low as possible; but gets additionally challenged by requirements on electrical isolation and by the three-dimensional shape they are supposed to be used on.

A trade-off between required thermal conductivity and available mechanical connection is therefore required as is the case with any conventional heat sink attachment. The three-dimensional shape of IRHS and 3D-MID as well as the available mounting solutions in three-dimensions will predominantly define the choice of appropriate mounting and interfacing of the IRHS.

6.5.3. IRHS design

The minimum design requirement on the IRHS is to ensure that the LEDs do not exceed their maximum temperature ratings. Furthermore, lower junction temperatures are beneficial as they contribute to improved optical efficacy and LED lifetime (Chapter 2) and can be positively influenced by an appropriate IRHS design.

Thermal network model of LED-section with IRHS

The proper design of the IRHS requires knowledge of the thermal pathway from the LED package to the reflector and then to the ambient. Figure 6-26 shows the thermal network model of the entire LED-section. Two parallel heat conduction paths can be identified: heat conduction from the LEDs to the IRHS, introduced in the prior section, and the heat path from the LED to the circuit carrier’s backside.


Figure 6-26: Thermal Network model for LED-Section

The heat transfer to the ambient environment is split into radiation and natural convection. The analysis of how much power can be transferred by the IRHS will be described with a case study system in the following; FEM analyses and experimental verification are performed additionally to prove the IRHS concept.

Heat transfer from the IRHS to the ambient

When a uniform temperature distribution can be maintained in the surfaces of the IRHS, a simplified thermal analysis can be performed for the heat transfer to the ambient.

The total power Ptotal that can be transported from the IRHS to the ambient environment is the sum of the convective- Pconv and radiative- heat transfer Prad. Both are temperature dependent mechanisms:

Δ Δ Δ (6.5.1)

The heat dissipated from the IRHS’s outer surfaces by means of radiation is defined by the Boltzmann law. In the case of an IRHS, the inner reflector shells will not contribute to radiative heat transfer as their surface is vaporized to achieve a high reflectivity for maximum light output. Hence, only negligible small emission coefficients appear.

Copper

IntegratedReflectorHeatsink(IRHS)

Substrate

InterfaceLED

Tambient

Rth_j_c

Rth_Cu_spread

Rth_IRHS_ambient

Rth_interface

PLED

Rth_IRHS

=

Rth_Cu

Rth_sub

Rth_sub_ambient

IRHS LEDs

Copper-layer

Substrate

Section planex

y

z

y

z

x

IRHS-orientation

Cross-sectional view

200 Chapter 6

The heat that is dissipated by means of natural convection is treated as the power that can be transported convectively in total from the outer IRHS surfaces. However, the convective heat transport of a surface is not only temperature dependent, but also influenced by its geometry and the orientation in space. If a straight alignment of the IRHS, as shown in Figure 6-26(top), is considered, the IRHS’s side-walls can be treated as heated vertical plates. The power transfer from the horizontally oriented outer surfaces can be calculated by considering the IRHS’s top surface as horizontal hot plate facing upwards and the bottom side as horizontal hot plates facing downwards.

The correlations and equations used for calculating the radiative- and convective- heat transfer from the IRHS to the ambient will be given in Appendix C.

6.5.4. Implementation – a case study

The IRHS case study that is realised for LED-cooling is visualised in Figure 6-27. The figure shows the IRHS attached to a plain circuit carrier with eight high-power LEDs mounted. The front side of the LED-section is covered with a 10μm thick copper layer for heat spreading and low resistive connection to the IRHS; only small intersections are between the heat spreading areas required for electrical isolation between the LEDs.

Figure 6-27: Case study integrated reflector heat sink for LED-cooling on 3D-MIDs

A self-adhesive thermally conductive interface material ensures the IRHS connection to the circuit carrier. The thermal network of the complete structure is therefore identical to the network shown in Figure 6-26.

The following specification is given for the case study system:

A fixed circuit carrier size with evenly distributed LEDs is given, as defined in Figure 6-27.

The available footprint area is given by the circuit carrier size

The IRHS wall thickness of the outer surfaces is given by the substrate- and LED-size

HeighthIRHS

Dimensions

[mm²]

wIRHS lIRHS hIRHS

160 20 25

Atop

Abottom Aside

Aback

Afront


The IRHS should be able to fulfill the following requirements:

Total losses of Ploss=8W have to be dissipated to the ambient environment

The maximum allowed heat sink temperature rise is ΔT=50K

Determination of initial IRHS length

From a lighting point of view, the shape of the IRHS is mainly determined by the required light output angle and light distribution which influences the depth as well as the opening angle of the reflector shells.

Concerning the thermal management design, the length lIRHS of the reflector is of special interest. Because of the low thermal conductivity of thermally conductive polymers (here λIRHS=3.2W/mK), a uniform temperature distribution along the reflector is not naturally given even along low distances. A uniform temperature distribution, however, is required to perform the prior introduced simplified thermal management design (Section 6.5.3).

The temperature drop along the IRHS surface has therefore to be calculated first, to ensure that the assumption of uniform plate temperatures is still valid.

A single reflector segment of the IRHS is used to calculate its thermal resistance along the z-axis, as defined in Figure 6-28 (left). The total thermal resistance is then calculated as the parallel connection of all eight reflector segments. Figure 6-28 (right) presents the resulting thermal resistance of the IRHS, with given dimensions and with a thermal conductivity of λIRHS=3.2W/mK. In addition, the resistances of a fictive IRHS made of aluminium, are given for reasons of comparison.

Figure 6-28: Reflector segment (model with mean wall thicknesses) and thermal resistance of IRHS dependent on length lIRHS

It can be seen from the charts that the length of the IRHS has a significant influence on the temperature distribution along the IRHS, as expected. A comparatively short value of lIRHS=20mm has therefore been selected as the initial length for a first design. This leads to a total thermal resistance of about 2.3K/W between bottom and top of the IRHS.

Table 6-11 summarizes the resulting outer surface areas that appear in this initial design:

0.00

0.05

0.10

0.15

0.20

0

1

2

3

4

5

5 10 15 20 25 30 35

Alu

min

ium

: IR

HS

resi

stan

ce[K

/W]

Poly

mer

: IR

HS

resi

stan

ce[K

/W]

Length lIRHS of IRHS [mm]

Therm. conductive PolymerAluminum

V1V4

xy

z

25mm

5mm

Volumes V1=V4, V2=V3

Single reflector segment

λ=3.2W/mK

λ=235W/mK

202 Chapter 6

Table 6-11: Resulting surfaces of IRHS contributing to radiation and convection

Atop Abottom Asides Aback Afront

Area [cm²] 32 32 10 30 16

Determination of power that can be transferred to the ambient environment

With the assumption of a quite uniform temperature distribution in the IRHS valid, the power dissipation to the environment can now be calculated by using the equations described in Section 6.5.3 and Appendix C.

Figure 6-29 shows the results of the analysis with the IRHS dimensions specified in Figure 6-27 and Table 6-11. The correlations of [ID00] have been used for the convective heat transfer for the horizontal top- and bottom plates, respectively. The correlation of [LK83] has further been used for the vertical plate heat transfer and an emission coefficient of εr=0.88 has been used.

Figure 6-29: Calculated power dissipation of the IRHS by natural convection and radiation over temperature increase.

It can be seen from the charts that the LED losses of 8 Watts lead to a temperature increase of ΔT=47K of the IRHS, which is below the specified maximum allowed temperature rise of 50K. Hence, no further modifications of the IRHS structure, like integration of extra cooling fins with further heat sink optimisation, are necessary.

During the analysis of the IRHS’ heat transfer capabilities, it has been observed that its performance is mostly affected by the available IRHS length lIRHS, which corresponds to the fin length of a conventional heat sink. Using only lIRHS/2 would result in a temperature increase of ΔT=80K, when keeping the remaining input values constant. This in turn, can be beneficially used to extend the heat transport by increasing lIRHS, which requires heat sink

0

2

4

6

8

10

12

14

20 30 40 50 60 70

Pow

er [

W]

Temperature difference ΔT [K]

Prad(ΔT) Pconv(ΔT) Ptotal (ΔT)

ΔT=47K


materials with increased thermal conductivity and is therefore comparable to conventional heat sink designs.

Thermal network modelling and resulting LED temperature rise

By knowing the temperature rise of the IRHS at full LED-losses, their junction temperature can now be derived by solving the thermal network model introduced in Section 6.5.3.

The heat transfer coefficient from the circuit carrier’s backside to the environment is assumed to be identical to the values derived for the IRHS due to the good thermal coupling, and hence negligible temperature drop, between both components.

Table 6-12 summarizes the calculated conduction resistances in the thermal pathway based on the geometrical data also defined in the table. The values have been derived from the prototype IRHS system to be demonstrated at the end of this section.

Table 6-12: Calculated conduction resistances in LED-segment

NomenclatureContact area

[cm²]

Thickness/length[mm]

Thermal Conductivity

[W/mK]

Thermal resistance

[K/W]

LED Rth_j_c - - - 9

Copper layerRth_spread Assumed to be zero

Rth_perp 40 0.01 394 6.3E-6

Substrate Rth_substrate 40 1.55 0.25 1.55

Interface Rth_interface 30 0.3 0.6 0.167

IRHS Rth_IRHS 30.8 10 3.2 1.02

A mean value has been used to model the thermal resistance Rth_IRHS in the IRHS material by using half the reflector depths and the cross-sectional area of the reflector as input parameters.

The thermal resistances from the IRHS and the circuit carrier to the ambient by means of convection have been calculated. This assumes the same temperature rise of ΔT=47K, as has been calculated for the IRHS only (Figure 6-29). The calculated heat transfer coefficients and the resulting thermal resistances are summarized in Table 6-13.

Table 6-13: Calculated thermal resistances of IRHS and substrate backside for determined ΔT=47K

Nomenclature

Heat transfer coefficient vertical

surfaces[W/m²K]

Heat transfer coefficient horizontal

top surfaces[W/m²K]

Heat transfercoefficient horizontal

bottom surfaces[W/m²K]

Thermal resistance

[K/W]

IRHS Rth_IRHS_a 9.3 11.7 5.8 15.3

Substrate Rth_sub_a 9.3 - - 26.9

204 Chapter 6

By using the thermal resistance network (Figure 6-26) and considering the heat transfer by radiation (Figure 6-29), the LED junction temperature rise has been calculated with the input values of Table 6-12 and Table 6-13 to be ΔTLED=59.15K.

FEM modelling and experimental verification

The complete LED section has been simulated by means of FEM analysis for reasons of comparison. The simulation uses identical input parameters as the analytical model. The LED packages have been modelled as solid blocks with a thermal resistance that represents the package’s junction to case resistance. Results of the FEM simulation are shown in Figure 6-30.

Figure 6-30: FEM simulation results of LED-section with IRHS at an ambient temperature of Tambient=20°C

It can be seen from the figure that the simulation parameters fit the results derived by the analytical model very well, with ΔTLED=63.1K compared to the analysis with ΔTLED=59.15K.

The entire structure has been built and tested to prove prior analytical and numerical results. The reflector has been milled out from a solid block of a LUVOCOM 1-7904 [Le09] which has the identical thermal conductivity used in the prior analyses λIRHS=3.2W/mK. Furthermore, identical material parameters and boundary conditions as prior have been maintained.

Figure 6-31 shows IR images of a reflector section of the prototype IRHS at an ambient temperature of Tambient=26°C. It can be seen from the measurement that the practical results fit the simulated and calculated results obtained by the analyses very well, with a mean ΔTLED=59.1K.

Figure 6-31: IR-image of IRHS prototype operated with 8W LED losses at an ambient temperature of Tambient=26°C: left: ISO-view of entire IRHS, right: front view of an IRHS-section

IRHSLEDs

Copper-layer

Substrate 83°C

70°C

53°C

Nr. Temp. [°C]

M1 87.7M2 83.0M3 84.5M4 60.5M5 60.2

80°C

70°C

60°C

50°C

40°C

30°C

80°C70°C60°C50°C40°C30°C

90°C


Additional calculations and simulations with increased LED power levels have been performed with the identical IRHS to give an indication of the capabilities and limitations of the IRHS. Table 6-14 summarises the resulting LED junction temperatures increase.

Table 6-14: Comparison of LED temperatures rise at increased power level with identical IRHS

Single LED-power

[W]

Total LED-power

[W]

Temperature increase (Calculation)

[K]

Temperature increase(Simulation)

[K]

1.5 12 83.3 84.5

2 16 104.6 109.5

3 24 145.5 153.5

It can be seen from the values that the IRHS is still able to maintain a moderate LED temperature increase even, when a 50 percent higher load is applied to the LEDs. A further increase of the LED power, however, requires adapted IRHS design or extended thermal management solutions, e.g. with forced convection.

6.6. Summary

In this chapter, thermal management solutions that are able to maintain effective heat transport from 3D-MID-based LED-lighting systems with LED-driver have been investigated. The converter level thermal management has been identified as central domain that challenges the cooling of power electronic components and of the high-power LEDs, as the heat spreading and heat conduction performance directly influences the effectiveness of the available thermal management solutions (Section 6.2).

Investigations on the heat transport capabilities of 3D-MIDs have been performed in Section 6.3 to determine heat-conduction and -spreading limits caused by the circuit carrier technology. The analyses show that the 3D-MID can be used for the cooling of low power levels by using its copper layer not only for circuit routing, but also for thermal-management functions. However, high perpendicular thermal resistances as well as limited heat spreading performance, caused by the low copper layer thickness, highly restrict the processable power level.

The cooling performance and limits of 3D-MID-based thermal management are investigated in Section 6.4 by means of a case study LED-driver. The design approach suggested here contains converter loss calculation, FEM supported layouting and prototype verification. It is shown, that the 3D-MID-based thermal management is the limiting factor that influences power electronic implementation, as large component distances are required for passive cooling with the copper layer only. This negatively influences the power converter performance, as discussed in Chapter 5. Consequently, a trade-off is required between the electrical- and thermal-design of power electronic systems on 3D-MID, which could be covered by coupled thermo- electrical simulations, when necessary.

206 Chapter 6

The use of external cooling solutions, e.g. heat sinks, can extend the power range of 3D-MIDs, but these solutions are normally optimised towards cooling of two-dimensional structures. Thus, a successful implementation on 3D-MIDs is mainly limited by the desired 3D-shape (Section 6.3).

Therefore, a novel Integrated Reflector Heat Sink concept has been developed (Section 6.5).It integrates thermal management- and optical functions in a single component and allows the direct heat transport from the surface where the components are attached. It circumvents the limitation of 3D-MID’s restricted perpendicular heat transport and, therefore, provides significantly reduced thermal resistances to the ambient. The IRHS shape can be generated by injection moulding of thermally conductive polymers to ideally match the 3D-shape of the 3D-MID, contributing to decreased contact resistances and maintaining high spatial degrees of freedom. Its heat transfer is defined by available cross sectional areas which are mainly determined by the 3D-MID surface. Additional optimisation parameters available are material choice, integration of extra cooling fins and conventional heat sink optimisation as broadly presented in the literature.

The IRHS concept is able to greatly enhance the power dissipation of 3D-MIDs and has been experimentally verified on a prototype system. The measured and predicted component temperatures are in close correlation and verify the introduced IRHS design and analysis (Section 6.5).

Bibliography [AN12] ANSYS, Inc: ANSYS, 2012.

[Ch01] Chen, J. Z.; Wu, Y.; Gence, C.; Boroyevich, D. et al.: Integrated electrical and thermal analysis of integrated power electronics modules using iSIGHT: Proc. Sixteenth Annual IEEE Applied Power Electronics Conf. and Exposition APEC 2001, 2001; pp. 1002 1006.

[Co02] Coxe, W. K., III; Solbrekken, G. L.; Yazawa, K.; Bar-Cohen, A.: Experimental modeling of the passive cooling limit of notebook computers: Proc. Eighth Intersociety Conf. Thermal and Thermomechanical Phenomena in Electronic Systems ITHERM 2002, 2002; pp. 15 21.

[Eg08] Egelkraut S.; Zeltner S.; März M.; Eckardt B.: Wärmeleitfähige Kunststoffe für Entwärmungsaufgaben. In Thermisches Management in der Leistungselektronik, Peak-Seminar, 2008.

[Er00] Ericsson Microelectronics: Thermal aspects on DC/DC Power Modules, Design Note 004, 2000.

[Fa12] Fan, A.; Bonner, R.; Sharratt, S.; Ju, Y. S.: An innovative passive cooling method for high performance light-emitting diodes: Proc. 28th Annual IEEE Semiconductor Thermal Measurement and Management Symp. (SEMI-THERM), 2012; pp. 319 324.

[FL09] Forster, S.; Lindemann, A.: Combined optimisation of thermal behaviour and electrical parasitics in Power Semiconductor components: Proc. 13th European Conf. Power Electronics and Applications EPE ’09, 2009; pp. 1 10.



[Hi076] Hirschmann, D.; Tissen, D.; Schroder, S.; Doncker, R. de: Reliability Prediction for Inverters in Hybrid Electrical Vehicles. In IEEE Transactions on Power Electronics, 2007, 22; pp. 2511–2517.

[Ho11] Hoerber, J.; Mueller, M.; Franke, J.; Ranft, F. et al.: Assembly and interconnection technologies for MID based on thermally conductive plastics for heat dissipation. In 2011 34th International Spring Seminar on Electronics Technology (ISSE), 2011; pp. 103–108.

[HRC98] Hartnett, J. P.; Rohsenow, W. M.; Cho, Y. I.: Handbook of heat transfer. McGraw-Hill, New York, 1998.

[ID00] Incropera, F. P.; DeWitt, D. P.: Fundamentals of heat and mass transfer. Wiley, New York ;, 2000.

[Ja94] Jamieson, D. J.; Mansell, A. D.; Staniforth, J. A.; Tebb, D. W.: Application of finite difference techniques for the thermal modelling of power electronic switching devices: Proc. Fifth Int Power Electronics and Variable-Speed Drives Conf, 1994; pp. 313 318.

[Jo02] Jonah Zhou Chen; Ying Feng Pang; Boroyevich, D.; Scott, E. P. et al.: Electrical and thermal layout design considerations for integrated power electronics modules: Proc. 37th IAS Annual Meeting Industry Applications Conf. Conf. Record of the, 2002; pp. 242 246.


[Jo13] Josifovic, I.: Power Sandwich and x-dimension components, Delft, 2013.

[JPJ93] Jones, S.; Pye, D.; Jeal, P.: Modern materials technologies in PCB thermal management. In IEE Colloquium on (Digest No.027) CAD (Computer Aided Design) Tools for Thermal Management, 1993; pp. 8/1.

[Le09] Lehman & Voss: Datasheet: Thermally conductive LUVOCOM® compounds, 2009.

[Le1206] Leneke, T.: Thermisches Management mit 3D-MIDs. In Elektronik, 2012; pp. 38–41.

[LHS08] Leneke, T.; Hirsch, S.; Schmidt, B.: A multilayer process for fine-pitch assemblies on molded interconnect devices (MIDs), 2008; pp. 663 668.

[Li98] Li, R. S.: Optimization of thermal via design parameters based on an analytical thermal resistance model: Proc. Sixth Intersociety Conf. Thermal and Thermomechanical Phenomena in Electronic Systems ITHERM ’98, 1998; pp. 475 480.

[LK83] Lewandowski, W. M.; Kubski, P.: Methodical investigation of free convection from vertical and horizontal plates: Wärme - und Stoffübertragung. Springer, 1983; pp. 147–154.

[LSM95] Lee, S.; Song, A.; Moran, K.: Constriction/spreading resistance model for electronics packaging: Proc. 4th ASMEI/JSME, Thermal Eng. Joint Conf, 1995.

[ORA09] Oliver, G.; Roberts, K.; Amey, D.: Benchmark Study of Metal Core Thermal Lamintes. In IMAPS Device Packaging Conference, 2009.

[Pa05] Pang, Y.: Assessment of Thermal Behavior and Development of Thermal Design Guidelines for Integrated Power Electronics Modules, 2005.

[Pe04] Petroski, J.: Spacing of high-brightness LEDs on metal substrate PCB’s for proper thermal performance: Proc. Ninth Intersociety Conf. Thermal and Thermomechanical Phenomena in Electronic Systems ITHERM ’04, 2004; pp. 507 514.

[QLH09] Qin, Y. X.; Lin, D. Y.; Hui, S. Y. R.: A Simple Method for Comparative Study on the Thermal Performance of Light Emitting Diodes (LED) and Fluorescent Lamps: Proc. Twenty-Fourth Annual IEEE Applied Power Electronics Conf. and Exposition APEC 2009, 2009; pp. 152 158.


[SBM02] Sawle, A.; Blake, C.; Maric, D.: Novel power MOSFET packaging technology doubles power density in synchronous buck converters for next generation microprocessors. In 2002. APEC 2002. Seventeenth Annual IEEE Applied Power Electronics Conference and Exposition, 2002, 1; pp. 106 111.


[TP11] Thomas, W.; Pforr, J.: Design of power converters on 3D-MIDs for driving three-dimensional LED-lamps. In 2011 IEEE Energy Conversion Congress and Exposition (ECCE), 2011; pp. 325 332.

[ZJL97] Zhang, M. T.; Jovanovic, M. M.; Lee, F. C.: Design and analysis of thermal management for high-power-density converters in sealed enclosures: Proc. 1997. Twelfth Annual Applied Power Electronics Conf and Exposition APEC ’97, 1997; pp. 405 412.

7. Case study: 3D-MID-based high-power LED-lighting system

7.1. Introduction

In Chapters 4 to 6 solutions and techniques have been developed to make the electrical, spatial and thermal design of 3D-MID-based high-power LED-lighting systems possible. Individual limitations arising from circuit complexity and power limitations, defined by component losses and required ampacity levels, have been determined as well as solutions to extend the power range of 3D-MIDs have been presented.

In this chapter, a case study LED-lighting system is used as an example to demonstrate how to apply the developed techniques of Chapters 4 to 6 to the design of an entire high-power LED-lighting system with LED-driver on 3D-MIDs. The case study prototype uses a single circuit carrier as multifunctional component to provide electrical, thermal and spatial functions according to the thesis’ concept, as proposed in Chapter 3.

Section 7.2 defines the target specifications the case study system has to be designed for. Section 7.3 describes the system design which is based on the techniques and solutions developed in Chapters 4 to 6 to enable a 3D-MID-based LED-lighting system. The design leads to the physical construction of the prototype, which will be described step by step in Section 7.4.

The prototype LED-lighting system is experimentally evaluated in Sections 7.5 to 7.7 considering its spatial, electrical and thermal performance. Measured waveforms as well as thermal measurements are presented and compared to results obtained from the proposed design.

The chapter is summarized in Section 7.8.

7.2. System specification

An automotive day-time-running light containing twenty high-power LEDs with a total power consumption of PLED=15W is considered as target application to be designed as a 3D-MID-based high-power LED-lighting system. This power level has been identified in the foregoing three chapters to be manageable on 3D-MIDs using the developed solutions.

Required lighting functions

According to Chapter 1 and 3, the following lighting functions have to be fulfilled in the target application:

Creation of a uniform brightness distribution among twenty high-power LEDs

212 Chapter 7

Control of LED brightness with stable chromaticity values at high PWM dimming frequencies of f=1kHz to avoid flickering in the automotive application

Maintaining operational availability after single LED failures

Electrical boundary conditions

The system is required to operate directly from the 14V automotive electrical power net with an input voltage level of Vin=8V-17V.

Luxeon K2 [Kl] high-power LEDs are considered for the prototype as these are common types in this kind of application. These LEDs show a typical forward voltage of VLED=3V at an LED-current of ILED=250mA.

Voltages above 54V are unwanted in this kind of application (Chapter 2), which prohibits a simple series connection of all LEDs.

Thermal boundary conditions

Next to the electrical conditions, the following thermal boundary conditions are determined for the case study system:

The ambient temperature ranges from -40°C to +80°C

The LED-temperature rise must not to exceed ΔT=50°C

LED-driver components have to be operated within their maximum temperature ratings

Heat transfer to the ambient is only available by natural convection and radiation

Spatial boundary conditions

The following spatial boundary conditions appear for 3D-MID realisations (Chapter 2 and 5), in general:

A low component count is required for simplified assemblies

Reduced wiring complexity has to be ensured for successful routing

In the case study, no stringent restrictions exist on constructed space, unless the dimensions of typical automotive daytime-running-light systems are not exceeded.

7.3. System design

The design of the LED-lighting system will be described step by step in the following section. The design contains three stages as visualised in Figure 7-1.

Case study: 3D-MID-based high-power LED-lighting system 213

Figure 7-1: Design stages of prototype

In the first step the LED-driver topology and required components to fulfil the target specification are determined. As second step the electrical and spatial design of the prototype is performed. This leads to a first layout which serves as input parameter for the thermal management design.

The system’s electrical, spatial and thermal design will be addressed by choosing appropriate techniques and solutions developed in Chapters 4 to 6 that are suited best for the given system target specification.

7.3.1. LED-driver topology selection

The low complexity LED-driver topologies developed in Chapter 4 serve as basis for the selection of an appropriate LED-driver topology. Considering the specification of Section 7.2,the boost converter with coupled inductor (Section 4.4) can be identified as solution that is capable to directly fulfil the functional as well as electrical requirements of the target application:

The LED-driver is able to provide a good current balancing performance over the entire automotive input voltage range whilst maintaining a low circuit complexity. Output voltages above 54V can be avoided by arranging the LEDs in two branches with 10 LEDs each. Short-circuit LED failures can be directly compensated by the topology and the introduced passive diode network Dx can be used to limit the influence of single open-circuit LED failures on the entire system’s availability.

Brightness control with stable colour values is addressed with the introduced technique of modulated dimming.

Prototype configuration and specification

Figure 7-2 shows the resultant prototype’s schematic. It can be seen that the topology is based on the two-branch boost converter with coupled inductor of Section 4.4. The prototype’s configuration will be described in the following.

The entire prototype uses SMT components to allow a simple realisation on 3D-MIDs, as described in Chapter 5. A discrete input inductance Lin is used to avoid issues in integrating a sufficiently large leakage inductance directly in the coupled inductance Lc.

Furthermore, several countermeasures are made to allow a simple routing on the single layer circuit carrier. Only a single MOSFET Q is used as active switch to maintain a low number of traces. Thus, additional diodes D1 and D2 are necessary for branch current separation. The

Electrical- and spatial design

Based on Chapter 5

Thermal management design

Based on Chapter 6

LED-driver topology selection

Based on Chapter 4

214 Chapter 7

failure compensation network Dx is based on a series connection of seven low profile diodes in each branch. This ensures a sufficiently high forward voltage difference between the LED-branches during normal operation (Vx ≈ 3.1V). The use of discrete diodes provides a sufficiently large heat spreading area to avoid overheating of the diodes.

Figure 7-2: Prototype topology based on principle of Section 4.4

The LED branches are based on the configuration of Prototype 2 (Section 4.4.4), with two parallel LED-strings containing a series connection of ten Luxeon K2 [Ph07a] high-power LEDs in each branch. Filter capacitors C1 and C2 are connected in parallel to the LEDs to maintain approximately dc LED-currents.

The prototype is configured to be driven by a microcontroller. The converter’s input voltage Vin as well as the individual branch voltages VLED1 and VLED2 serve as input parameters for the duty cycle calculation. The simple voltage measurement requires only three additional sensor traces and a few resistors to be implemented in the layout. Whenever more precise output current control is required, branch current sensing could be used to adjust the converter’s duty cycle, but comes at the cost of increased component count as well as wiring complexity. It is therefore not implemented in this prototype.

The system is furthermore designed to detect short circuit LED failures by measuring the individual branch voltages and comparing them to pre-saved values. An alternative can be seen in splitting each LED branch into different sections and performing differential mode voltage measurements, but requires increased wiring efforts. Open circuit LED failures can be detected similar to the short circuit detection by measuring the voltage across the individual LED-branches.

Table 7-1 summarises the resultant prototype specifications.

VinQD1 D2

D3

D4Lc

Lin

LED

-bra

nch

2

LED

-bra

nch

1

C1 C2

Cin

Dx

VinVLED1VLED2

μCVcc

Dr


Table 7-1: Prototype electrical specification

Vin

[V]ILED

[mA]VLED1

[V]VLED2

[V]Switching frequency

fs [kHz]

8-17 250 ≈30 ≈30 300

The exact LED branch voltages VLED1 and VLED2 are dependent on the individual LED forward voltages and are given in the experimental verification in Section 7.6.

Component values

With the given LED-power level and the 14V automotive electrical power net as boundary conditions, the power converter design of Prototype 2 (Section 4.4) can be used for the case study.

Table 7-2 summarizes the resulting main components used in the prototype’s power section. Table 7-2: Prototype components



Cin 20μF/ 25V 0805 Q FDS5680 [Vi08] SO-8

C1, C2 4.7μF/ 50V 1206 Driver Dr MCP1407 [Mi12] SO-8

Lin 10μH IHLP 2525EZ [Vi12] D1-D4 STPS2L60 [ST11] SMA

LcM: 25μHLs: 0.2μH

EPCOS EP-7Windings: 19

Dx PMEG6010 SOD323-R

It can be seen from the table that all components have been realised with standard SMT components. The inductor Lin has been selected as power inductance from Vishay (IHLP-2525CZ-01), whereas the coupled inductor has been realised with EPCOS EP-7 cores mounted on a SMT winding carrier. Schottky diodes have been used as free-wheeling and branch separation diodes. The diode network Dx contains low profile diodes PMEG6010 in each branch.

The electrical performance of the prototype will be evaluated in Section 7.6.

7.3.2. Spatial design and routing

In the next step, the spatial configuration as well as an initial circuit layout will be determined for the practical realisation of the prototype.

Spatial configuration

Chapter 3 has shown that the simplest assembly of 3D-MID-based LED-lighting systems is obtained with all components attached to the same surface, if sufficient construction space is available – single sided configuration (Chapter 3). This is the case for the target application.

216 Chapter 7

Figure 7-3 shows a principle view of the prototype’s resulting spatial configuration. It uses an axisymmetric design with the LED-driver located at the centre of the circuit carrier and the two LED-branches are arranged to its left- and right-hand side.

Figure 7-3: Spatial configuration of prototype

Due to the simple spatial configuration, only a single copper layer is considered for heat spreading and circuit routing.

Circuit track routing

The initial circuit layout can be determined by calculating the RMS-currents on the basis of the LED-driver topology and the given component values. Inserting these values in the current carrying capacity model of Section 5.3 leads to the initial trace widths and related parasitics.

Table 7-3 summarises the calculated RMS currents flowing through the components of the LED-driver’s power section when operated under full load conditions and minimum input voltage. The resulting circuit trace widths have been calculated by assuming a copper layer thickness of 12μm. Further, a temperature rise of T=40K has been allowed.

Table 7-3: RMS-currents flowing through components and initial trace width in prototype layout at Vin=8V

Lin D1, D2 Q D3,D4

RMS current [A] 2.27 1.61 1.97 0.99

Trace width [mm] 2 1 2 0.5

It can be seen from the table that the resulting circuit track widths are still bridgeable with standard SMT jumper components as described in Section 5.4.2. By knowing the minimum circuit track dimensions, a first compact circuit layout can be established. The focus of this layout is to achieve low loop inductances for optimised switching performance – comparable to the electrical designs presented in Section 5.4.

The concept of using the 3D-MID as a multifunctional component includes that the MID’s copper layer performs thermal management functions to keep LED-driver components below maximum values. This requires increased heat spreading areas around the lossy components and will consequently influence compact circuit routing, as investigated in Section 6.4. In addition, the considerably high LED-power of PLED=15W requires external thermal management solutions for the cooling of the LEDs (Chapter 6).

LED-driverLED-branch 1 LED-branch 2


Both design aspects will be addressed in the following section. The influence of increased heat spreading requirements on the resulting spatial design of the prototype LED-lighting system will be evaluated in Section 7.5.

7.3.3. Thermal management design

As a final step, the prototype’s thermal management and the interrelation between the thermal management and circuit routing, involving the LED-driver topology, have to be considered.

Thermal management concept

The case study’s thermal management follows the developed thermal management concept and design introduced in Chapter 6:

The 3D-MID is considered for cooling the LED-driver components. Its thermal management design will be oriented on the design introduced in Section 6.4.

Two Integrated Reflector Heat Sinks are used for cooling the LED-branches and will be realised according to the design introduced in Section 6.5.

Thermal management design of the LED-driver

Converter loss prediction is used as initial step to determine the losses in the LED-driver and builds the foundation of an adapted circuit layout that contains sufficiently large heat spreading areas for component cooling, as shown in Section 6.4.

Table 7-4 summarises the calculated prototype losses at minimum, nominal and maximum input voltage and gives values for the LED-driver’s predicted efficiency. The loss analysis isintroduced in Appendix B and focuses on the main loss contributors in the driver. The calculation uses the LED-driver topology and the component values of Section 7.3.1 as input parameters.

Table 7-4: Breakdown of calculated losses at different input voltages and efficiency prediction

Input voltageVin

[V]

Branch diodesD1, D2

[W]

Free-wheeling diodes D3, D4

[W]

MOSFET Q

[W]

Inductors Lin, Lc

[W]

Efficiencyη

[%]

8 0.66 0.22 0.28 1.48 83.0

14 0.27 0.23 0.17 0.83 91.1

17 0.19 0.23 0.14 0.68 92.2

It can be seen from the loss breakdown that an approximately equal loss distribution appears among passive- and semiconductor-components, when operated at nominal input voltage. The converter’s efficiency is expected to be 91 percent under these conditions. However, it is expected from the analysis that especially branch diode and inductor losses will increase at worst-case conditions, i.e. at minimum input voltage, and have therefore to be considered in the LED-driver layout.

218 Chapter 7

The component losses are used in the next stage to determine a circuit layout, which is feasible to keep component temperatures below their maximum ratings, when operated at worst-case conditions. The maximum component ratings are shown in Table 7-5.

Table 7-5: Maximum component temperatures

MOSFET Diodes Inductors

Maximum temperature Tmax [°C] 175 150 210

Combined heat spreading analysis and FEM supported layout are used in the next step to obtain a circuit layout with sufficiently large heat spreading areas (Section 6.4). Figure 7-4shows the resulting layout obtained from the analyses.

Figure 7-4: Final layout of prototype’s LED-driver – (a) 3D model and (b) top-view of layout with components

The component position is mainly determined by the power flow through the converter and a compact positioning between the components in the LED-driver’s power loop has been considered (Chapter 5). However, enlarged copper areas have been required for the heat dissipation from the branch diodes D1, D2 and the inductors Lin, Lc as these components exhibit the majority of the losses under worst case conditions (Table 7-4). As a consequence, the distances between the lossy components have been increased and care has been taken that the components were, whenever possible, centred on the copper surface for improved heat spreading.

Table 7-6 summarises the resultant component temperatures obtained from FEM simulations using convective- and radiative- cooling and working under different operation conditions.The simulations have been performed at nominal input voltage and at an ambient temperature of Tambient=30°C. In addition, worst-case simulations have been performed at minimum input voltage Vin=8V and maximum ambient temperature of Tambient=80°C to determine the layout pattern. The simulations’ input parameters are identical to the analysis presented in Section 6.4.

(b)(a)

QD

3

Lc

Lin

D4

D1

D2


Table 7-6: Simulated maximum component temperatures of the prototype’s LED-driver section at different operation conditions


D1 D2 D3 D4 Q Lin Lc

Normal operation: Vin=14V, Tambient =30°C 78.7 76.2 70.0 71.8 70.5 90.0 73.2

Worst-case operation: Vin=8V, Tambient =80°C 152.0 151.3 123.2 130.1 137.8 152.0 133.6

It can be derived from the results that a quite uniform temperature distribution is obtained among the semiconductor components at normal operation conditions. The highest component temperatures appear for the branch diodes and for the input inductance, as expected from their spatial distance and their comparably high losses. Under worst-case conditions, component maximum temperature ratings are slightly exceeded at the branch diodes. This could be further enhanced with an extra re-design of electrical layout and thermal management layout.Here, the copper surfaces connecting diodes D1, D2 and MOSFET Q would have to be increased, according to the results of Chapter 6.

It has to be noted, that the simplicity of the proposed LED-driver’s circuit layout still allows a compact routing of the power converter’s switching loop. The resulting prototype’s electrical performance will be evaluated in Section 7.6.

Thermal management design of the LED-sections

The design of the prototype’s IRHS follows the procedure presented in detail in Section 6.5.Hence, only a compact description will be given, in the following.

In contrast to Section 6.5, the prototype’s IRHS have to be adapted for the cooling of 10 high-power LEDs. Power losses of Ploss=6W have to be dissipated by each IRHS (defined by an LED-efficiency of 20 percent).

Figure 7-5 shows the resulting adapted IRHS with ten reflector cells, but with identical outer dimensions as the IRHS used in Section 6.5. The surfaces that contribute to radiative and convective heat transfer are further given in the figure. The IRHS’ heat transfer capabilities can be directly calculated by inserting the reflector surface dimensions into the equations of Section 6.5.3. The calculated power that can be dissipated by the IRHS to the ambient is also shown in Figure 7-5.

220 Chapter 7

Figure 7-5: IRHS for cooling of 10 high-power LEDs and calculated heat transfer to the ambient

It can be seen that the LED power dissipation increases the IRHS temperature by ΔT=37K.By knowing the temperature rise of the IRHS at full losses, the LED-junction temperature can now be derived by solving the thermal network model introduced in Section 6.5.3. Table 7-7summarises the calculated conduction resistances in the thermal pathway, based on the geometrical data of the IRHS and the circuit carrier used in the prototype implementation –also defined in the table.

Table 7-7: Calculated conduction resistances in LED-segment

NomenclatureContact area

[cm²]Thickness/length

[mm]Thermal Conductivity

[W/mK]Thermal resistance

[K/W]

LED Rth_j_c - - - 9

Copper layerRth_spread Assumed to be zero

Rth_perp 40 0.012 394 7.6E-6

Substrate Rth_substrate 40 1.55 0.25 1.55

Interface Rth_interface 28.4 0.3 0.6 0.176

IRHS Rth_IRHS 28.4 10 3.2 1.1

Finally, the thermal resistances from the IRHS and the circuit carrier to the ambient can be calculated for the expected temperature increase of ΔT=37K, leading to the thermal resistances, given in Table 7-8.

Height hIRHS

Dimensions

[mm²]

wIRHS lIRHS wIRHS

160 20 25

Atop Abottom Asides Aback Afront

Area [cm²] 32 32 10 28 12

02468

101214

20 30 40 50 60 70

Hea

tdis

ispa

tion

[W]

Temperature difference ΔT [K]

Prad(ΔT)Pconv(ΔT)Ptotal (ΔT)

ΔT=37K


Table 7-8: Calculated thermal resistances of IRHS and substrate backside for determined ΔT=37K

Nomenclature

Heat transfer coefficient vertical

surfaces[W/m²K]

Heat transfer coefficient horizontal

top surfaces[W/m²K]

Heat transfercoefficient horizontal

bottom surfaces[W/m²K]

Thermalresistance

[K/W]

IRHS Rth_IRHS_a 8.76 10.94 5.47 16.32

Substrate Rth_sub_a 8.76 - - 26.9

The LED junction temperature rise has been calculated with the input values of Table 7-7 and Table 7-8 to be ΔTLED=47.84K, which is slightly lower than the allowed temperature rise of ΔTmax=50K given in the target specification. The calculated input parameters can now be used to determine the temperature distribution among the LED section by means of FEM analysis. Figure 7-6 shows the resulting temperature distribution among one LED-segment, to be expected in the prototype. Only one section has been simulated due to the symmetry of the LED-lighting system.

Figure 7-6: FEM simulation results of one LED-branch with IRHS at an ambient temperature of Tambient=20°C

It can be seen from the figure that the simulation parameters fit the results derived by the analytical model very well, with ΔTLED=49.53K compared to the analysis with ΔTLED=47.84K.

The thermal management evaluation and performance of the prototype including LED-driver and LED-branches with IRHS will be performed in Section 7.7.

7.4. Realisation of the case study prototype

A prototype has been realised on the basis of the foregoing results to prove theoretical predictions. Its physical realisation will be described in the following.

Figure 7-7 (a) shows the LED-lighting system’s main assembly parts without electronic components attached. The system contains a single circuit carrier and two IRHS for extended heat transport of the high-power LEDs, as described in the prior section. The circuit carrier has been realised on a flat structure for reasons of simplicity in the assembly of the prototype system.

IRHS LEDs

Copper-layer

Substrate 72°C

55°C

35°C

222 Chapter 7

Figure 7-7: Components of the LED-lighting systems: circuit carrier and two IRHS

A single and 12μm thin copper layer is used for the electrical interconnection of components and for heat spreading tasks. In contrast to Prototype 2, which has been created on a 3D-MID substrate, FR-4 has been used as substrate material due to reasons of availability and has been used due to its similar material parameters (Section 5.2.1).

The two IRHS have been milled out of two solid blocks of thermally conductive polymer LUVOCOM 1-7904 [Le09]. The size of the IRHS has been mainly determined by the dimensions of the available polymer blocks, which have been created by injection moulding. These showed maximum dimensions of LxHxB=160x25x70mm³. Consequently, also the entire circuit configuration has been determined by these dimensions. Figure 7-7 (b) shows the placement of the IRHS on the circuit carrier, as planned in the final assembly.

The first assembly step of the lighting system contains the positioning and soldering of the LEDs and driver components to the circuit carrier, as shown in Figure 7-8. The LED-driver is located at the centre of the circuit carrier and the LEDs are arranged in two branches on the upper and lower part of the circuit carrier. Due to the low heat spreading performance of the 3D-MID copper layer, no meaningful cooling of the power-converter’s loss components can be expected with the available IRHS configuration.

A distance of about 2cm has been ensured between the high-power LEDs and the LED-driver components to avoid meaningful thermal cross-couplings, which has been identified in the thermal simulation of the LED-section (Section 7.3.3) and will be verified in Section 7.7.

The LED-branches are realised in the following manner: Ten high-power LEDs are connected in series in each LED-branch Each LED is located in the centre of an individual heat spreading area (Figure 7-8 (b))

The heat spreading areas are electrically insulated from each other, whereas their size has been defined by the dimensions of the IRHS and the number of LEDs in each branch.

IRHS 2

IRHS 1

Circuit carrier

(a) (b)


Figure 7-8: (a) LED-lighting system with main functional parts, (b) definition of components and LED-driver segments

The LED-driver comprises: The power-section with input and output filter components as well as the semiconductors: MOSFET Q, Schottky diodes D1-D4 and driver DrThe diode network Dx for open-circuit compensation Peripheral components, including linear regulator and microcontroller

Figure 7-9, shows the final LED-lighting prototype. The two IRHS have been attached with a self adhesive thermal interface pad to the circuit carrier’s heat spreading surfaces, leading to an LED-lighting system with a reduced number of components, as proposed in the concept idea in Chapter 3.

Figure 7-9: Final LED-lighting system assembly with circuit carrier, LED-driver and two IRHS

Using a 3D-MID as circuit carrier allows an integrated mechanical connection of the IRHS by directly realising snap joints and mounting elements in the plastic circuit carrier, as introduced in Chapters 3 and 5.

The prototype’s performance will be evaluated in the subsequent sections.

LEDs Heat spreader

Diode network Dx

Power section

Peri

pher

al co

mpo

nent

s

(a) (b)

IRHS 2

IRHS 1

Circuit carrier

Thermalinterface

224 Chapter 7

7.5. Spatial evaluation

The spatial layout and routing of the prototype has been mainly determined by thermal management needs, which has led to the introduction of extra heat spreading areas and the application of two IRHS that directly influence the spatial configuration of the system. The focus of the spatial evaluation is therefore on the prototype’s volumetric composition. Figure 7-10 shows a breakdown of the volume occupied in the prototype. This contains three different views: the LED-driver, the LED-segment and the entire LED-lighting system.

Figure 7-10: Breakdown of prototype’s volume composition: LED-driver, LED-segment and total system

The left breakdown shows the volume composition in the LED-driver. It can be seen that the requirement on increased heat spreading areas and single layer routing has lead to a relatively poor volume utilisation of 18.3 percent. It is assumed that the highest component defines the entire LED-driver volume. This is mainly caused by the chosen single sided configuration and the use of a purely two-dimensional substrate. 3D-shaping of the 3D-MID substrate could be used to overcome these limitations with spatially optimised designs, when tall components are horizontally aligned to decrease the total LED-driver height, as shown in Section 5.5.

In contrast to the LED-driver, the LED-segments show a significantly higher volume utilisation of 41.2 percent. This is caused by the IRHS which is used as multifunctional component to perform thermal management and optical functions. As a consequence, the total volume utilisation of the LED-lighting system (Figure 7-10 (right)) is positively influenced and reaches a value of 39.3 percent.

Furthermore, the routing of the entire system has been possible by using only five SMT jumper components to solve signal crossings. This can be accounted to the low complexity of the developed LED-driver topology. Whenever possible, already existing resistors, e.g. those for branch voltage measurement, have been used to avoid the use of extra jumpers.

The influence of the increased routing distances on the LED-driver’s electrical performance will be evaluated next.

Semi-conductors

1.7%

Passives3.9% Peripheral

Components0.2%

Substrate 12.6%

Air81.7%

LED-driver

.2%

Substrate 12.6%

Substrate6.5%

LEDs1.4%

IRHS33.3%Air

58.8%

Single LED-segment

Substrate7.0%

LEDs0.7%

Semi-conductors

0.1%

Passives0.3%

Peripheral Components

0.0%

IRHS31.2%

Air60.7%

LED-lighting system


7.6. Electrical evaluation

The LED-lighting system’s electrical performance has been measured at different input voltage levels as well as for different scenarios: current balancing, LED failure compensation as well as modulated dimming. The measurements have been performed without the peripheral components active.

7.6.1. Current-balancing

The LED-driver’s current balancing performance has been measured by inserting measuring lines in series to the LED-branch traces for the current measurement. Figure 7-11 shows the LED-driver waveforms at nominal input voltage Vin=14V and at full LED output power PLED=15W, leading to branch currents of ILEDx=250mA. It can be seen from the LED currents that only a small high frequency current ripple appears, leading to a high optical efficiency of the LEDs, as discussed in Chapter 4 [Sa06]. In addition, the LED-currents are nearly identical which contributes to a precise and homogenous brightness distribution.

A compact power loop layout has been possible with the given design and enables high switching speeds (e.g. toff=10ns) contributing to reduced switching losses. Furthermore, overvoltages of ΔVds≤10V have been measured under normal operation conditions.

Figure 7-11: LED-driver waveforms at Vin=14V and full load – Ch1: switch voltage 20V/div, Ch.3 and Ch.4: LED-branch currents I1 and I2 200mA/div, time-scale: 200μs/div

In a further step, the current balancing performance has been measured over the entire automotive input voltage range and hence, over the converter’s duty cycle whilst maintaining full LED-output power. It has been observed during the measurements that the prototype’s LED branch voltages are pretty similar, with VLED1=30.4V and VLED2=30.7V when operated at ILED=250mA. This, however, can still lead highly different branch currents if no current balancing technique is applied, as shown in Sections 4.2 and 4.3. Due to the low forward voltage deviations, two different cases have been utilised to evaluate the prototype’s current balancing performance:

Branch 1

Branch 2

226 Chapter 7

Case 1: The LED-branches have been kept identical to the prior measurements. Case 2: VLED2 has been decreased by shorting a single LED to achieve even higher forward voltage deviations of ΔVLED=-2.7V.

Figure 7-12 shows the measured values (given as discrete points) and values that have been obtained from the analysis, introduced in Section 4.4, by using the prototype’s component values (Table 7-2).

Figure 7-12: Current-balancing performance versus input voltage

The results from the measurements account the prototype a good current balancing performance, even at increased forward voltage deviations, as expected from the results in Section 4.4 (Prototype 2). The case study prototype maintains current deviations of below 5 percent over the entire input voltage range among the tested LED-branch voltages.

7.6.2. LED failures

The LED-driver’s behaviour at single LED failure has been measured in analogy to Section 4.4 to verify the system’s performance in abnormal operation conditions. The LED-currents have been measured directly with current probes in the measuring lines used for the foregoing current balancing measurements. Figure 7-13 shows the LED current waveforms of branch 1 and branch 2 at (a) LED failure with short circuit and (b) at open circuit in branch 2. In both cases, no duty cycle adjustment has been performed to compensate the output currents.

0

1.5

3

4.5

6

7.5

9

8 10 12 14 16

Rel

ativ

e cu

rren

t dev

iatio

n be

twee

n br

anch

1 a

nd 2

[%]


ΔVLED=0.3V calculated

ΔVLED=2.7V calc

ΔVLED= -0.3V: measured calculated

ΔVLED= -2.7V: measured calculated


Figure 7-13: LED currents at failures (a) short circuit (b) open circuit – 100mA/div, time scale 500ms/div

It can be seen from (a) that the short circuit of a single LED only leads to a minor change of the total output currents (<10 percent), as expected from the analysis in Section 4.4 and from the results with Prototype 2. At single open circuit failure, the diode network Dx ensures that one LED-branch is still working, as shown Figure 7-13 (b).

7.6.3. Modulated dimming

The LED-driver’s operation at modulated dimming has been measured at a dimming frequency of f=1kHz. Figure 7-14 shows the modulation signal and the resulting pulse width modulated LED currents ILED1 and ILED2, when the prototype is operated at a dimming ratio of about 50 percent.

It can be seen from the waveforms that the LED-lighting system achieves a comparably high di/dt at modulation signal turn on and turn off with Δton=Δtoff=50μs at an LED current ripple of ±20mA. Comparing these values with the investigations performed in Section 4.5 accounts the prototype good colour stability at the desired dimming frequency.

Figure 7-14: Waveforms at modulated dimming: CH1: modulation signal, CH3: LED current branch 1(200mA/div), CH4: LED current branch 1 (200mA/div), Time-scale: 500μs/div

Branch 1

Branch 2Short circuit in 2

(b)Branch 1

Branch 2

Open loop in 2

(a)

Branch 1

Branch 2

228 Chapter 7

When necessary, increased dynamics could be easily obtained by decreasing the output filter capacitance which in turn increases the high frequency LED-current ripple. An alternative is the replacement of the simple C-output filter by C-L filters, as analysed in Section 4.5.

7.6.4. LED-driver efficiency

The efficiency of the LED-driver has been measured in a final step and has been compared to the results obtained from the analytical calculations (Section 7.3.3). The ambient temperature has been kept constant at Tambient=25°C and system cooling has been performed by natural convection and radiation, only. The LED-lighting system has been operated at full output power over the entire automotive input voltage range. The input power has been directly measured at the LED-drivers input terminals. The LED-branch voltages and the output power have been directly measured across the LED-branches. Conductive losses in the circuit tracks connecting the LED-segments are therefore also accounted as LED-driver-losses.

Figure 7-15 shows the results from the measurements, with the efficiency plotted versus the input voltage. The experimentally determined values are shown as discrete points and the result obtained from the loss estimation, given in Section 7.3.3, is shown with a solid line.

The measurements and the loss prediction account the LED-driver an efficiency of about 90 percent at nominal input voltage and full load conditions. The maximum efficiency is obtained at maximum input voltage Vin=17V, with 91 percent.

Figure 7-15: Converter efficiency versus input voltage

A comparison of the loss prediction and the measurement shows a good agreement. Increased differences at low input voltages might be caused by simplifications made in the loss prediction, e.g. conduction losses in the circuit tracks have been neglected. This gets more expressed at low input voltage as higher currents are required to obtain the same output power.

0.70

0.75

0.80

0.85

0.90

0.95

5 10 15 20

Eff

icie

ncy

[%]


MeasurementPrediction


7.7. Thermal evaluation

The system’s thermal performance has been evaluated with the full prototype system, shown in Figure 7-9. Only free convection and radiation have been available for the heat transfer to the ambient and have been ensured by a sufficiently large enclosure. For the measurements, the LED-lighting system has been suspended with a thermally isolating cord that has been fixed to a tripod. Figure 7-16 shows an IR-image of the entire IRHS and its orientation in space, used for the subsequent measurements. The system has been operated at nominal input voltage of Vin=14V at full LED power PLED=15W.

Figure 7-16: IR image of case study LED-lighting system under normal operation Vin=14V, Tambient=25°C

It can be seen that a quite homogenous temperature distribution appears among the IRHS and in the LED-driver. Further, no significant thermal interactions appear between the LED-driver and the LED-branches, as expected from the design (Section 7.3).

In the following, thermal measurements focusing on the LED-driver and the LED-branches will be presented. The experimental results will be compared to results obtained from the thermal management design in Section 7.3.

7.7.1. LED-driver

Figure 7-17 shows the resultant component temperatures and the temperature distribution in the LED-driver when operated at nominal input voltage (Vin=14V) and full LED power PLED=15W. The electrical evaluation has shown that the converter is operated at an efficiency of 90 percent under these conditions (Section 7.6.4). The ambient temperature has been constant Tambient=25°C.

65°C

55°C

45°C

35°C

25°C

IRHS 1

IRHS 2

LED-driver

230 Chapter 7

Figure 7-17: IR image of prototype’s LED-driver section at nominal input voltage Vin=14V at full load,Tambient=25°C

It can be seen from the measurements, that a quite uniform temperature distribution is achieved in the entire layout, as expected from the thermal design. Figure 7-18 shows the corresponding result from the FEM analysis using the same input parameters for reasons of comparison (Section 7.3.3).

Figure 7-18: Thermal FEM simulation of LED-driver section at Vin=14V and full load, Tambient=30°C

A comparison of the component temperatures obtained from the FEM simulations to the experimentally measured values is given in Table 7-9. The simulation values have been corrected to the same ambient temperature as with the practical measurements: Tambient=25°C.

Table 7-9: Comparison of component temperatures from measurement and simulation at Vin=14V and full load, normalised to Tambient=25°C


D1 D2 D3 D4 Q Lin Lc

Measurement 79.2 75.4 71.8 75.4 75.0 86.7 76.4

FEM simulation 73.7 71.2 65.0 66.8 65.5 85.0 68.2

The comparison shows a good accuracy of the FEM model to the practical results with maximum deviations of below 15 percent and verifies the predictions made in the thermal deign.

Considering the worst-case simulations, given in Section 7.3.3, the implemented thermal management layout can be seen as absolute minimum configuration to keep component

Nr. Temp. [°C]

M1 76.4M2 86.7M3 75.0M4 71.8M5 75.4M6 75.4M7 79.2

80°C

70°C

60°C

50°C

40°C

Q

Lin

Lc

Diodes branch 1

D3,D4

30°C

90°C

D1,D2

90°C

65°C

40°C


temperatures under their maximum ratings. If additional routing space is available, enlarged heat spreading areas would be beneficial to further decrease maximum component temperatures.

7.7.2. LED-section

The thermal evaluation of the LED-sections has been performed in the same manner as for the LED-driver. Figure 7-19 shows thermal images of the upper IRHS and gives a detailed view of four reflector cells, measured at an ambient temperature of Tambient=25°C and full LED-power.

It can be seen from the figure, that the measured values fit the calculated values from the analysis and the results of the FEM simulation very well (Section 7.3.3).

Figure 7-19: Thermal images of top IRHS operated with 6W LED losses at an ambient temperature of Tambient=26°C – left: entire IRHS, right: front view of an IRHS-section (4 reflector segments)

A mean LED-temperature rise of ΔTLED=49.53K has been identified among the LEDs in the prototype which is in close correlation to the calculated value of ΔTLED=47.84K, and hence meets the target specifications.

7.8. Summary

The design, realisation and experimental evaluation of a case-study automotive daytime-running light have been presented in this chapter. The design and evaluation focus on the electrical- and thermal- performance of the system. Experimental results are compared to analytical and simulated values and show a good agreement.

The prototype is supposed to contain twenty high-power LEDs with integrated LED-driver and a total LED-power of 15 Watt. Section 7.2 introduces the prototype’s full target specification with required lighting functions, as well as with thermal-, electrical- and spatial-boundary conditions.

The prototype’s design is based on the introduced concept of using the 3D-MID as multifunctional component (Chapter 3) and utilises technologies and solutions developed in Chapters 4 to 6 to enable 3D-MID-based high-power LED-lighting systems. A compact overview of the prototype’s design is given in Section 7.3. The analyses and designs have

70°C

60°C

50°C

40°C

30°C

70°C

60°C

50°C

40°C

30°C

Nr. Temp. [°C]

M1 71.3M2 72.2M3 71.3M4 51.7M5 49.8

232 Chapter 7

been discussed in detail in the individual chapters. Hence, only the design approach and corresponding results are given in this chapter.

After the design phase, the physical realisation of the LED-lighting system is illustrated in Section 7.4. The system contains the LED-driver and the LEDs assembled to a single-layer circuit carrier that serves as multifunctional component which provides electrical, spatial and thermal functions. Furthermore, the concept of using Integrated Reflector Heat Sinks is applied to the LED-lighting system to extend the heat transfer capability of 3D-MIDs.

Section 7.5 discusses the spatial performance of the LED-lighting system, which shows enlarged space requirements for the LED-driver section, as expected due to the simplified concept of using a flat circuit carrier for component cooling. Using the 3D-shaping possibility, available with 3D-MIDs, could be used in future designs to improve the overall spatial performance.

The electrical evaluation of the LED-lighting system is performed in Section 7.6, and shows that the system is able to provide stable LED-brightness levels over the entire automotive input voltage range, with an efficiency of 90 percent at nominal input voltage and full load conditions. The proposed current balancing principle achieves LED-current deviations below 5 percent over the entire input voltage range – even at high LED-tolerances. The system achieves integrated LED PWM dimming at high dimming frequencies of f=1kHz with minor colour shift. In addition, single LED failures are directly compensated with the proposed LED-driver topology. Due to the low complexity of the LED-driver, only minor routing challenges appear which reflects in low switching loop parasitics that enable fast switching speeds of t=10ns and low overvoltages of ΔVds≤10V.

The prototype’s thermal evaluation (Section 7.7) shows that the LED-driver section can be sufficiently cooled by the circuit layout, avoiding external thermal management components. In addition, the concept of using an Integrated Reflector Heat Sink is successfully applied to the two LED-sections and maintains maximum LED-temperature rises below the specified value of ΔT=50K ensuring high-luminous fluxes of the twenty high-power LEDs.

Bibliography [Kl] Klein, J.: Synchronous buck mosfet loss calculation with EXEL model. Application note

AN-6005.

[Le09] Lehman & Voss: Datasheet: Thermally conductive LUVOCOM® compounds, 2009.



[Sa06] Sauerlander, G.; Hente, D.; Radermacher, H.; Waffenschmidt, E. et al.: Driver Electronics for LEDs: 41st IAS Annual Meeting Industry Applications Conference Conference Record of the 2006 IEEE, 2006; pp. 2621 2626.




8. Conclusions and recommendations

8.1. Summary

This thesis deals with decreasing the complexity and improving the degrees of freedom in the design of three-dimensional high-power LED-lighting systems with LED-driver by enhancing the level of function integration.

Chapter 1 identifies the necessity of the three-dimensional (3D) shaping of LED-lighting systems for improved functionality as well as for enhanced design, which is especially required in automotive applications for means of diversification. Target functions that have to be fulfilled for enhancing prospective applications are likewise addressed.

In Chapter 2 the present practice of LED-lighting assembly and the evolution towards first three-dimensional LED-lighting systems is analysed. The circuit carrier is identified as central element which defines the number of components required and that determines the degrees of freedom a LED-lighting system can reach. The potential of 3D-Moulded Interconnect Devices (3D-MID) to integrate mechanical- and electrical-functions into a single three-dimensional component is identified as possible means for enhancing the design and construction of future 3D LED-lighting systems, if it is possible to handle increased power levels.

Chapter 3 introduces an approach to enable future high-power LED-lighting systems with increased design versatility by using a 3D-MID as multifunctional component that is supposed to integrate the inevitable LED-driver as well as spatial-, electrical- and thermal-functions. These domains have to be investigated in order to make 3D-MID-based high-power LED-lighting systems possible. The individual design domains are treated in Chapters 4 to 6, in detail.

Chapter 4 focuses on the development of novel LED-drivers that fulfil essential lighting functions at a high operational availability whilst demanding a low component count and reduced circuit complexity which is required for a realisation of (power) electronics on 3D-MIDs. The developed techniques are able to cover a wide range of electrical configurations as well as various LED-power levels. Analytical results are verified with practical measurements on different prototypes.

Chapter 5 systematically determines how the use of 3D-MID-technology influences the spatial realisation of power converters compared to conventional PCB technology, and shows how the system’s electrical performance gets affected by resulting circuit track parasitics. Further, merits and limitations that arise when (power) electronic systems are aimed to be realised on 3D-MIDs are determined.

The implementation of an effective thermal management for 3D-MID-based high-power LED-lighting systems is considered in Chapter 6. This contains the determination of heat dissipation limits of the 3D-MID as well as an approach to extend the manageable power level by using an integrated reflector heat sink. The integrated reflector heat sink unifies thermal

236 Chapter 8

management- and optical-functions in a single component and enhances component cooling without limiting the desired three-dimensional shape of the LED-lighting system.

Chapter 7 combines the techniques and solutions developed in Chapters 4 to 6 in the design and experimental evaluation of an automotive LED daytime-running light supposed for a 3D-MID use. The application can be considered as case study due to its demanding power level and the general requirement to enhance future automotive LED-lighting systems with sophisticated three-dimensional designs.

8.2. Conclusions

The conclusions that can be drawn from the thesis are arranged in five categories corresponding to the thesis objectives presented in Chapter 1:

Identification of the main reasons that limit enhanced designs of contemporary high-power LED-lighting systems by analysing the present practice of construction and the evolution towards 3D LED-lighting systems Determination of an approach to use the 3D-MID technology for enhancing the 3D-design whilst decreasing the construction complexity of high-power LED-lighting systems with LED-driver by increasing the level of function integration Development of optimised LED-drivers with integrated lighting functions for asimplified 3D-MID realisation Determination of merits and limitations to mount and contact the LED-driver and the LEDs on the 3D-MID as well as to analyse influences of the 3D-MID technology on the spatial- and electrical- realisation of power-electronics Examination of the potential to integrate thermal management functions into the 3D-MID for low complexity systems and to derive a solution to enhance the power level of 3D-MID-based LED-lighting systems whilst maintaining high degrees of freedom

8.2.1. Present practice and evolution of (3D) LED-lighting system construction

The present practice of realising LED-lighting systems with increased LED-power is dominated by the use of a multitude of components that fulfil electrical-, spatial- and thermal-functions. In the vast majority of applications these components are individually designed and often only address single functions. This, however, leads to complex assemblies with a plurality of components (Chapter 2). A similar situation appears in the inevitable power electronic LED-drivers for high-power LEDs, as these contain different and separated networks required to provide essential lighting functions (Chapter 2 and 4).

Conclusions and recommendations 237

The resulting construction complexity prohibits designs that are able to benefit from the LED technology’s advantage of individually placing light sources in three-dimensions – essential for improved designs and enhanced functionality. This gets further amplified, as a three-dimensional circuit carrier technology is missing that integrates advanced 3D-shaping and 3D-interconnection for (high-power) LED-lighting systems.

To enable more sophisticated 3D LED-lighting systems, the technologies of creating electrical-, spatial- and thermal- functions have to meet. Two central themes have been identified to enhance future systems:

Maintaining a high 3D-shaping flexibility is necessary to enhance future designs and has been identified to be strongly defined by the used circuit carrier technology

Decreasing the number of components is essential to reduce the assembly complexity and can be achieved by enhancing the level of function integration of the components used in the LED-lighting system

8.2.2. 3D-MID technology application to enhance the 3D-design of high-power LED-lighting systems with LED-driver

Enhanced three-dimensional design and the reduction of the number of components have been identified as central themes to enhance future 3D LED-lighting systems. The 3D-MID technology has been determined as technology that is able to address prior domains for low-power systems already. It provides enhanced 3D-shaping possibilities and integrates electrical- and spatial-interconnections in a single as well as robust component.

When the 3D-MID is considered as multi-functional component to enhance LED-lighting systems with advanced power level, new challenges arise (Chapter 3). These are mainly determined by the increased power class, demanding (more) complex LED-drivers that have to be routed on the 3D-MID and causing enlarged power losses that have to be managed. The approach of using the 3D-MID as multifunctional component in LED-lighting systems with LED-driver has therefore to consider the following domains:

LED-driver topology: The power electronic LED-driver strongly defines the circuit complexity and the component count that have to be connected on the 3D-MID, which offers only limited routing options compared to PCBs. The LED-driver complexity must, therefore, be minimised to enable a simplified spatial-, electrical- and thermal- design of the entire system. Spatial- and electrical design: The restricted routing options of 3D-MIDs determine the spatial- and electrical-design of the entire system. Hence, it is required to analyse the influence of the 3D-MID technology on the spatial realisation, but moreover, on the electrical performance of power electronic LED-drivers. Thermal management: The thermal management solutions available with 3D-MIDs define the manageable power-level as well as the achievable three-dimensional shape of the 3D-MID-based LED-lighting system. It is, therefore, required to determine the

238 Chapter 8

available heat transfer capabilities of 3D-MIDs and to derive solutions to extend their power level without undermining the versatile 3D-shaping possibilities.

Conclusions obtained from the preceding design domains will be summarised in the subsequent sections.

8.2.3. Development of adapted LED-driver topologies for 3D-MID realisation

The successful implementation of LED-lighting systems on 3D-MIDs requires LED-drivers with low component count, minimised circuit complexity as well as with a homogenous loss distribution. For this reason, adapted LED-driver topologies must be developed which are realisable on 3D-MIDs whilst providing essential lighting functions, like precise brightness control and -distribution among a multitude of LEDs as well as LED-failure compensation. The following conclusions can be drawn from the development of LED-drivers suitable for 3D-MID-based high-power LED-lighting systems (Chapter 4 and 7):

The separation and independent design of the dc-dc power converter and of current balancing- as well as dimming-networks in state of the art LED-drivers has been identified as hurdle for 3D-MID applications, as this approach increases system complexity and component count. The distribution of lighting functions to different networks is used as starting point in this thesis to develop adapted LED-drivers with low complexity by integrating lighting functions directly into standard power converter cells, beneficial for a realisation on 3D-MIDs.

The developed novel principle of inductive brightness distribution can be directly applied to a variety of different isolated and non-isolated power converter topologies allowing simplified 3D-MID realisation due to low wiring complexity and low numbers of components required. The principle is able to compensate large LED-forward voltage deviations and single LED-failures without active components, which has been verified on several prototypes throughout the thesis (Chapter 4 and 7).

Integrating the commonly used external PWM-dimming networks in the power converter has been identified as further means to decrease the component count as well as the wiring complexity whilst fulfilling demands on dimming with high colour stability – even at high-dimming frequencies required in applications like automotive lighting. This makes the developed technology especially suitable for 3D-MID applications. The technique has been successfully applied to different power converter topologies and its performance has been verified on prototype systems, in this thesis.

8.2.4. Influence of 3D-MID usage on electrical and spatial realisation of power electronics

The 3D-MID technology offers significantly different spatial- and electrical interconnection options when compared to state of the art printed circuit boards. This is mainly caused by the


process of creating the circuit artwork, which influences the contacting of single components as well as the routing of entire (power-) electronic systems. The following main conclusions can be drawn for the spatial- and electrical-realisation of power electronics on Laser-Direct-Structured (LDS) 3D-MIDs, as identified in Chapters 5 and 7:

The construction technology of (LDS) 3D-MIDs limits the available circuit routing variances as well as the Current Carrying Capacity (CCC), which is mainly determined by the selective additive generation of the copper traces and the limited layer availability. Increasing the trace width is identified as the most convenient solution to increase ampacity levels, but raises the circuit footprint, decreases the volume utilisation and may affect the electrical performance of power converters.

CCC modelling can be used as helpful means to determine the influences of 3D-MID’s circuit trace dimensions on the spatial realisation of power converters, with a given topology and known ampacity levels. In addition, circuit trace parasitic extraction combined with analytical circuit modelling or -simulation is an essential method to determine the electrical performance, and therefore, the feasibility of prospective power converters on 3D-MIDs. It is further shown in the thesis, that the successful realisation of power electronic systems on 3D-MIDs requires optimised circuit layouts with low complexity, as already low-power applications are prone to considerably high overvoltages across switching devices. The main reasons are that 3D-MIDs are more susceptible to increased parasitic layout inductances caused by low current carrying capacities and due to limited routing options compared to PCBs. 3D-MID substrate shaping in all dimensions can be used to overcome limitations of 2D-routing on single layer substrates. However, this is mainly solved at expenses of modifying injection moulding tools in dependency of the circuit layout. Thus, the layout flexibility of the LDS 3D-MIDs gets undermined and a trade-off between the effort of conventional (2D) routing and 3D-substrate modification is required.

8.2.5. Thermal management of 3D-MID-based LED-lighting systems

The converter level thermal management is identified in this thesis as the central domain that challenges the cooling of power electronic components and of the high-power LEDs, as the 3D-MID’s limited heat spreading and heat conduction performance directly influences the effectiveness of the available thermal management solutions. The thermal management concept identified in this thesis is therefore dependent on the component power level. It contains thermal management functions directly integrate-able in the 3D-MID and solutions to increase the manageable power-level without limiting the enhanced 3D-shaping possibilities 3D-MIDs offer. The following main conclusions can be drawn for the thermal management design, as derived in Chapter 6 and 7:

The 3D-MID can be used for the cooling of low power levels by using its copper layer not only for routing- but also for thermal-management functions. As routing flexibility is greatly reduced with 3D-MIDs, low circuit complexity layouts are essential.

240 Chapter 8

Otherwise routing demands will contradict with the implementation of thermal pathways. Combined loss- and heat-spreading analysis are suitable methods to determine the power level that is still processable by the 3D-MID and FEM-supported layouting can be used for the design of 3D-MID-based cooling. This approach has been evaluated experimentally on different prototype LED-drivers in Chapter 6 and 7. The developed concept of using a novel Integrated Reflector Heat Sink (IRHS) can be used to extend the power level of 3D-MID-based LED-lighting systems, which is especially required for the cooling of the high-power LEDs. The IRHS allows the direct heat transport from the surface where the components are attached, which circumvents the limitation of 3D-MID’s limited perpendicular heat transport and therefore provides significantly reduced thermal resistances to the ambient.

The IRHS integrates thermal management- and optical functions in a single component, according to the thesis’ approach of using multifunctional components to enhance future 3D LED-lighting system. It can be assembled by injection moulding of thermally conductive polymers, which offers maximum spatial degrees of freedom and provides the possibility to decrease contact resistances to ideally match the 3D-shape of the 3D-MID. The IRHS concept has been verified with two different prototype realisations (Chapter 6 and 7).

8.2.6. Thesis contributions

The main scientific contributions of this thesis can be summarised as:

LED-driver architectures for driving a multitude of high-power LEDs with low circuit complexity

The design of novel LED-driver topologies with integrated passive-brightness distribution network and integrated PWM dimming possibility for high-power LEDs that can be applied to a variety of basic power converter topologies is considered as contribution. In the literature, different approaches for passive current balancing of low-power LEDs have been presented, but these are not capable of driving high-power LEDs with high optical efficacy and low component count.

The integrated PWM LED-dimming with its optimisation for low-wiring complexity and stable LED-colour values for high frequency dimming operation is a novel approach and considered as further contribution.

Concept for the electrical, thermal and spatial integrated design of LED drivers on 3D-MIDs

The systematic analysis of the 3D-MID technology to obtain design constraints for the electrical, thermal and spatial realisation of power electronic LED-drivers is considered as new contribution and has not been found in the literature. So far, only low-power systems containing sensor applications and low-power LED-lighting systems that show a significantly


lower power-level and circuit complexity as the proposed high-power LED-lighting systems have been presented.

Integrated Reflector Heat Sink (IRHS) concept for 3D-MID-based LED-lighting systems

The use of thermally conductive polymers to replace conventional extruded heat sinks is generally used in industry and is also described in the literature to decrease component weight as well as to integrate external functions directly into the thermal management component, e.g. with power module housing directly made of thermally conductive polymers. Also the design of reflectors that contribute to increased heat transport from light sources is already used in industry.

The new contribution of this thesis is the design of an integrated reflector heat sink that can be ideally shaped to fit complex three-dimensional shapes of 3D-MIDs for maximum contact surfaces whilst maintaining high-degrees of freedom in the design and integrating optical- and thermal management- functions.

Multifunctional 3D-MIDs for 3D high-power LED-lighting system with LED-driver

The (integral) electrical-, thermal- and spatial- designs of power electronic converters have been presented in the literature and are used in industry to gain increased power densities. This is often obtained by introducing multifunctional components. Also, the 3D-MID technology itself is used in different low-power applications as multifunctional device that integrates spatial- and electrical- functions.

However, using a 3D-MID as multifunctional component that integrates electrical-, thermal- and spatial-functions to reduce the construction complexity and to enhance the design versatility of 3D LED-lighting systems with high-power level and integrated LED-driver is a unique approach and is, therefore, considered as contribution.

8.3. Recommendations for further research

The following recommendations for further research can be made:

Consistent three-dimensional electrical- and spatial-design environment

The design of a 3D-MID-based electronic system is dependent on the availability of existing software tools that address the electrical- as well as the spatial-design of the 3D-MID. Currently, the world of electrical-CAD and mechanical-CAD are – to a large extent – treated as two individual domains, as the prior is focused on two-dimensional design of PCBs and the latter does not consider electrical interconnections. First software tools emerged that allow the 3D-routing of components. It has been identified throughout the design and realisation of 3D-MID-based power converters though that these solutions lack the convenience of state of the art PCB layouting software, e.g. in terms of automatic routing or interfaces to power electronic simulation software. This made the 3D-design of prototypes with increased layout

242 Chapter 8

complexity, requiring routing iterations, e.g. for improved heat spreading, barely manageable. As a consequence, mainly 2D-layouts have been focused on.

Developing a consistent 3D-routing and -spatial design software environment would be a great first step to decrease today’s indisputable hurdles for power electronic design on 3D-MIDs.

Integral and automated design

The LED-driver design in this thesis is based on the spatial orientation of components within the limits of calculated circuit trace widths, with the focus on maintaining a compact layout in the crucial domains of the power electronic LED-driver, e.g. in the switching loop. This is then adapted to meet the requirements on the converter level thermal management, e.g. heat spreading areas around lossy components. This approach is done by hand and is based on experiences made throughout this thesis in the loss analyses, heat spreading analyses and in the determination of 3D-MID circuit trace parasitics.

The development of a design tool that achieves automated component positioning as well as circuit routing in three-dimension for an optimum design, in terms of component temperatures or layout parasitics, could extend the scope of the 3D-MID technology towards moderate-loss power electronic applications with requirements on high 3D-shaping flexibility.

Electromagnetic compatibility (EMC) design

The circuit layouts realised in this thesis have been routed on a single copper layer only, which offers the possibility to accomplish them with an EMI shielding layer. However, the EMC-design of the 3D-MID-based LED-lighting system has not been in the scope of this work. Nevertheless, EMC-design is an essential cornerstone for the realisation of power-electronic systems, which gains importance when no compact routing is possible or even unwanted and when (switching-) transients are carried on three-dimensionally arranged circuit traces.

A systematic determination of an appropriate EMC-design and its interdependencies to the spatial- and thermal-design for three-dimensionally arranged power electronic systems would, therefore, be a substantial means for enhanced designs.

Increased function integration in the 3D-MID

In this thesis, three basic functions have been incorporated by a multifunctional 3D-MID –namely electrical- mechanical- and (basic) thermal-functions – to enable 3D LED-lighting systems with LED-driver and high-power LEDs. This can be seen as a substantial step to lay the basis for further power electronic systems on 3D-MIDs.

However, as material technology improves new possibilities for even extending the use of the 3D-MID as multifunctional component might become possible. The integration of passive components, e.g. with injection moulded soft-magnetic material for integrated inductors, has yet to be determined to be compatible in a 2-shot-injection moulding process with the LDS-substrate material. Besides, enabling enhanced thermal conductivity in the LDS-substrate


could lead to new power levels of 3D-MIDs as external cooling solutions might get obsolete. Materials with increased thermal conductivity and decreased coefficients of thermal expansion could further contribute to multilayered 3D-MIDs. Progresses in substrate material technologies can, therefore, contribute substantially to the use of 3D-MIDs in power-electronic applications and should be considered for further research.

A. Appendix: Influence of inductor tolerances

A.1. Introduction

In this appendix, the influence of the inductor tolerances on the proposed principle of inductive power sharing and current balancing of Chapter 4 is calculated (Section A.2., A.3)

The influence of magnetic core material tolerances on resulting inductance values is calculated in Section A.4, leading to a design example with low inductor tolerances suitable for the proposed current balancing topologies that operate without coupled inductors.

A.2. Influence of inductor tolerances on power sharing performance

The permeability of the inductor core ferrite material is subject to production tolerances. As deviations among the inductors determine the power sharing quality of the proposed inductive power sharing principle, an analysis has been performed to calculate the influence of the non-ideal permeability of the core material on the power sharing quality of the proposed buck-boost and flyback converters of Section 4.3.

The energy stored in the buck-boost converter’s branch inductances has been determined in Equation (4.3.11) and will be repeated here for convenience:

Equation (A.1) shows that the energy stored in each inductor Ex is dependent on the inductance Lx as well as on the peak inductor current ΔI at the end of switching mode 1. For a system with two inductances with values L1 = L and L2 = L+ΔL the energy deviation between the two branches can be defined as:

E1 is the energy stored in inductor 1 with inductance L and E2 is the energy stored in inductor 2 having the inductance L+ΔL.

By inserting (A.1) into (A.2) and considering the inductance difference ΔL, the following general expression is obtained for the energy deviation:

We obtain a nearly linear relationship between the inductance deviation ΔL and the deviation of the stored energy in the inductors ΔE when inductance deviations of up to 25 percent are considered. Figure A-1 visualises the result of the analysis. It can be concluded, that a good power sharing performance requires small tolerances between the individual branch inductances.

246 Appendix A

Figure A-1: Energy deviation ΔE for two-branch system plotted over inductance deviation ΔL/L

Similar calculations have been performed for the flyback converter topology of Section 4.3.3. A linear relationship is obtained between the inductance deviation ΔL and the deviation ΔE of the energy stored in the flyback’s transformers:

Again, small tolerances are required among the inductances to achieve a good power sharing performance. An inductor realisation with low tolerances will be addressed in Section A.4.

A.3. Influence of inductor tolerances on current balancing performance

The influence of the inductor tolerances on the resulting branch current deviations can be derived in a similar manner as for the power deviations. The analysis will be exemplified for the parallel power converter topologies, in the following.

The current deviation between the branches of a two-branch system with inductances L1 = Land L2 = L+ΔL can be written as:

Inserting the branch inductances’ values in the buck converter’s branch currents calculation, as shown in Section 4.3.1 (Equations (4.3.1)-(4.3.10)), can be used to obtain the influence of inductor tolerances on current balancing. The same analysis has been performed for the boost- and buck-boost topologies.

The three topologies share the fact that the resulting influence of the inductor tolerances on the current deviation ΔIrel is:

0 0.1 0.2 0.30.2

0.15

0.1

0.05

0

0.092E L( )

0.1

L

LLL

Influence of inductor tolerances 247

Again, a nearly linear relationship between the inductance deviation ΔL and the deviation of branch currents ΔIrel appears, as visualised in Figure A-2. It has to be noted, though, that this simplified relationship is only valid for the plotted range of inductance deviations (ΔL≤ 0.25·L).

Figure A-2: Energy deviation ΔE for two-branch system plotted over inductance deviation ΔL/L

Therefore, current balancing requires precise inductance values, when the parallel current balancing topologies without coupled inductors are considered.

A.4. Influence of core material tolerances on inductance values

Planar cores are suggested for the realisation of the branch inductances to obtain low tolerances and have been used in Prototype 1 and 3. The inductor windings can be realised with external winding carriers or with directly integrated windings, as discussed in Appendix B.

Because of the concentrated air gap of planar cores, the length of the air gap can be manufactured with small tolerances, leading to a well defined magnetic resistance of the air-gap. However, typical soft-ferrite materials show tolerances of up to ±25 percent in their permeability [EP06]. The influence of these deviations on the inductances will be considered in the presented analysis.

Smallest planar cores (ELP 14/3.5/5) have been selected for the realisation of the inductancesto keep the ferrite costs low and the size of the prototypes small. The calculation of the expected tolerances is based on a simple magnetic resistance model consisting of the ampere-turns Ni (magnetomotive force), the magnetic resistance of the core Rm_ferrite and the magnetic resistance of the air-gap Rm_air-gap [Er01]. The cross-section of the air-gap is assumed equal to the cross-section of the ferrite core. The inductance is dependent on the overall magnetic resistance L=N2/Rm where Rm=Rm_air-gap+ Rm_ferrite. Hence, the number of the inductance

0 0.1 0.2 0.30

0.05

0.1

0.15

0.2

0.092I rel L( )

0.1

L

LLL

248 Appendix A

windings N has to be increased when the air gap is enlarged to achieve a constant value of the inductance.

Soft-ferrite material N87 from EPCOS is proposed for application. The datasheet of this material shows a typical magnetic permeability of μr=2200, with ±25 percent tolerances [EP06]. The magnetic resistance of the core has been determined under assumption of

r=2200, r=1.25 2200 and r=0.75 2200 and the resulting inductance has been calculated dependent on the length of the air-gap as well as including the magnetic resistances of the core at minimum and maximum permeability. Figure A-3 shows the results of this analysis.

Figure A-3: Calculated inductance deviations for ±25% deviations of μr and required winding number for given inductance L

The figure shows the calculated positive and negative deviations and hence the tolerance band of the inductance values depending on the length of the air-gap. The number of the inductor windings N has been increased in analogy to the increase of the air gap to keep the inductance values constant. In this calculation, a branch inductance of L=6.1μH has been used, as needed in Prototype 1 (Section 4.3.4). The number of the required windings is plotted against the second y-axis of the figure.

The charts show that an air gap of 100μm is required to reduce inductance deviations to under ±4 percent, when assuming the worst case scenario with the maximum tolerances appearing in the magnetic permeability μr, as defined in the datasheet values (±25 percent). As a consequence, power or current deviations are also limited to this magnitude, supporting an improved brightness distribution among LEDs. In practical applications where the magnetic cores are likely to be delivered from the same production lot, tolerances are probably even smaller. Consequently, the same applies to the power- and current-deviations.

The calculations for the flyback converter’s transformers (Section 4.3.3) lead to a similar result and have been published in [TP10a].

0123456789

-10-8-6-4-202468

10

0 50 100 150 200

Req

uire

d w

indi

ng n

umbe

r

Indu

ctan

ance

dev

iatio

ns

Air gap (μm)

positive deviationnegative deviationWindings N

Bibliography [EP06] EPCOS AG: Ferrites and Accessories, 2006.

[Er01] Erickson, R. W.: Fundamentals of Power Electronics. Springer Science+Business Media, Inc, 2001.

[TP10a] Thomas, W.; Pforr, J.: Isolated converter topology with integrated power-sharing for driving a large number of HB-LEDs. In 2010 14th International Power Electronics and Motion Control Conference (EPE/PEMC), 2010; pp. T6-45.

B. Appendix: Loss analysis and -comparison

B.1. Introduction

In this part, additional information is given to the analyses used in Chapter 5, in order to determine the spatial and electrical design of power electronics on 3D-MIDs.

Section B.2 focuses on the loss analysis of single switch dc-dc power converters, which serves as the basis for the loss predictions used throughout this thesis. Section B.3 extends the discussion of integrated inductances on 3D-MIDs from Section 5.3.2 and focuses on the perspectives of planar core integration. Inductor loss calculations of 3D-MID-based, PCB-based and SMT inductances are performed, as an example, to evaluate the feasibility of 3D-MID-based planar core integration.

B.2. Loss analysis

In this section, converter loss analysis is introduced which is the basis to predict the converter losses of the individual case study prototypes used in this thesis. The loss analysis is focused on single switch power converters, and is subsequently used in Chapters 5 to 7.

B.2.1. Resistive losses

The resistive losses in the power converters, e.g. in circuit traces or inductor windings, are calculated as follows:

(B.1)

with R = Resistance [Ω] IRMS = Root mean square current [A]

B.2.2. MOSFET losses

The MOSFET losses are separated into switching losses Psw, conduction losses Pc and gate-charge losses Pgate in this analysis. The conduction losses can be directly calculated by solving (B.1) and inserting the MOSFETs’ Rdson, which is given as datasheet value.

Switching losses

The converters used in this work are single switch-topologies operated in DCM operation. This leads to a zero-current-switching condition at MOSFET turn-on. Hence, the analysis is focused only on the turn-off transition of the MOSFETs.

The simplified switching waveforms of the turn-off transition are given in Figure B-1, and have been derived according to [Er01]. The MOSFET’s time-dependent drain current and

252 Appendix B

drain-source voltage are described with ids and vds, respectively. The gate-source voltage is defined with vgs.

Figure B-1: Simplified visualisation of MOSFET turn-off transition

According to the model illustration in Figure B-1, the resultant switching losses Psw can be written, as:

(B.2)

with ΔI = Drain current peak value [A] Vs = Voltage across the power switch [V]tvr, tif = Voltage-rise- and current-fall-time [s] fs = Switching frequency [Hz]

The voltage-rise- and current-fall-time tvr, tir have to be determined separately to obtain the switching losses. This can be achieved by circuit simulation, practical measurement or by using analytical models. A simplified calculation model, which uses the MOSFET’s gate charge to determine the resulting switching speed is given by [Kl].

The voltage rise time is calculated as:

(B.3)

with Qgd = MOSFET gate-charge, as defined in the datasheet [C] Idr = Gate driver current [A] Vplt = Plateau voltage of the MOSFET gate-voltage, from datasheet [V] Rgate = Gate resistance used in circuit [Ω] Rgate_dr = Internal driver gate resistance [Ω]

0

10

20

30

40

1.8E-04 1.8E-04 1.8E-04 1.8E-04 1.8E-04

ids

vds

0

10

20

30

40

1.8E-04 1.8E-04 1.8E-04 1.8E-04 1.8E-04

vgs

tvr tif

ΔI

Vgate

Vs

Vplt Vth

Loss analysis and -comparison 253

The current-fall time tif is calculated, according to the model in [Kl], by determining the time to discharge the gate-source capacitor from the plateau voltage Vplt to the gate-threshold voltage Vth. The time tif is calculated as:

(B.4)

with Ciss = MOSFET input source capacitance [F] Vth = Threshold voltage of the MOSFET, as defined in datasheet [V] Vgate = Gate driver voltage [V]

An advanced model that further takes the parasitic layout inductance into account has been developed by [Xi04]. It can be used to determine the switching speed in dependency of circuit layout parasitics when available, as used in Chapter 5. The switching-loss model has also been extensively described by [Me08] and has been further applied to loss calculations of high frequency dc-dc converters. The equations will therefore not be repeated here.

The model will later be used in Section B.2.5 to determine the switching losses in the four switching cell layouts of Section 5.4.3. This can be done as layout parasitics are known from the PEEC modelling. The input parameters and results are given in Section B.2.5.

Gate-charge losses

The MOSFET’s gate charge losses Pgate can be calculated by using the gate charge information given in the datasheet. Further input parameters are the gate-voltage and the switching frequency, leading to:

(B.5)with

Qgate = MOSFET gate-charge [C] Vgate = MOSFET gate-voltage [V] fs = Switching frequency

B.2.3. Diode losses

Diode losses appear in the free-wheeling- and in the branch-diodes of the presented power converter topologies. As Schottky diodes are used exclusively, reverse recovery is assumed to be negligibly small and only conduction losses are considered. The latter can be calculated as Pdiode:

(B.6)with

Iavg = Average current flowing through the diode [A] VD = Diode forward-voltage [V]

254 Appendix B

B.2.4. Inductor losses

The inductor loss calculation is divided into the calculation of the losses in the core material due to the change of the magnetic flux density and the calculation of the resistive losses in the inductor windings.

SMT inductors

The SMT inductances used in this work are selected from one manufacturer’s product line which is well documented with detailed winding and core loss calculation models. The models and inductor specific parameters are provided in [Vi12].

The core losses per volume Pv are calculated by using the Modified Steinmetz Equations (MSE), which has been introduced for non-sinusoidal waveforms [JAS01]:

(B.7)

with K0 = Core volume [m³] Kf = Frequency constant – empirical parameters as defined in the datasheet Kb = Flux density constant – empirical parameters as defined in the datasheet Bpk = Peak magnetic flux density [T] fe = Effective frequency, equivalent excitation frequency [Hz] fo = Repetition frequency, switching frequency [Hz]

The dc-winding losses can be directly obtained with the datasheet values for the winding resistances, whereas the ac-winding resistances can be determined by the manufacturer’sdesign guideline equations [Vi12]. The ac-winding losses can be determined with:

(B.8)

with K1 = AC loss constant, as defined in the datasheetΔIac = AC current component in the inductor [A] fo = Repetition frequency, switching frequency [Hz] Roper = Temperature corrected resistance of the inductor

where,

(B.9)

with Rmax = Maximum winding resistance as defined in the datasheet [Ω] Tambient = Ambient temperate [K] ΔT = Temperature rise [K]


Planar core inductors

The determination of the losses in the planar core inductances can be performed in a similar manner, and is described in Section B.3

B.2.5. Loss analysis results for case study switching cells

Results obtained for the loss analysis of the four case study boost-converter switching cells (Section 5.4.3) will be summarised in the following. The results have been calculated on the basis of the foregoing loss-analysis.

The converter schematic is repeated in Figure B-2 for reasons of convenience.

Figure B-2: Boost converter schematic of case study switching-cells

The converters are supposed to work under the environmental conditions defined in Table B-1and the converter’s main components, with related datasheets that are summarised in Table B-2.

Table B-1: Case-study converter operating conditions


Switchingfrequency

fs [kHz]

GatevoltageVgate [V]

Gate resistance

Rg [Ω]

Duty cycle

D

Peak drain current

Î [A]

LEDvoltage

VLED [V]

14 300 15 1 0.43 2 28

L

DQDr

Rgate

Cin Cout

Cb

256 Appendix B

Table B-2: Components used in case-study prototypes



Cin10μF/ 25V 0805 Q FDS5680 [Vi08] SO-8

Cout4.7μF/ 50V 1206 Dr MCP1407 [Mi12] SO-8

Cb4.7μF/ 25V 0805 D STPS2L60 [ST11] SMA

L 10μH IHLP 2020 [Vi12]

Rgate 1Ω 0805 & 2010

Determination of MOSFET turn-off time toff: switching model

Pspice simulations and analytical modelling of the converter switching transients have been used to determine the turn-off time of the MOSFET required for the switching-loss calculations (Section B.2.2). The model will be described shortly in the following.

Figure B-3 shows the complete Pspice model used for the simulation of the boost converters. The electrical circuit is based on the switching loss model of [Xi04] and contains not only the converter components (Table 1), but also considers the parasitic layout and component inductances (Ld1-Ld4, Ls, LA and LK).

Figure B-3: Pspice simulation model of case-study layouts


The layout parasitics have been determined in Section 5.4.3. The complete inductance matrices of the four case study layouts, containing the self and mutual inductances, are presented in Table B-3 for reasons of completeness.

Table B-3: Simulated inductance matrices of layout parasitics of the case study layouts – values in nH

35μmCu_min Ld1 Ld3 Ld4 35μmCu_max Ld1 Ld3 Ld4

Ld1 2.43 0.04 0.01 Ld1 1.62 0.03 0.10

Ld3 0.04 2.32 -0.29 Ld3 0.03 1.46 -0.20

Ld4 0.01 -0.29 2.43 Ld4 0.10 -0.20 1.04

10μmCu Ld1 Ld3 Ld4 5μmCu Ld1 Ld3 Ld4

Ld1 1.62 0.03 0.11 Ld1 2.67 -0.11 0.03

Ld3 0.03 1.46 -0.20 Ld3 -0.11 1.88 -0.41

Ld4 0.11 -0.20 0.84 Ld4 0.03 -0.41 1.20

In addition, the MOSFET’s parasitic input and output capacitances Ciss, Crss are modelled to obtain the switching characteristics. The non-linear behaviour of the capacitances has been modelled by using curve approximation based on the data given by the manufacturer’s datasheet [Vi08], as has been proposed in [UHP10].

The voltage dependency of the capacitors has been approximated with the following equation:

BThe parameters a1 and a2 for Ciss and Crss are given in Table B-4.

Table B-4: Parameters used to model case study’s MOSFET [Vi08] non-linear input and output capacitances in circuit simulation

a1 a2

Ciss -116 2117

Crss -91 370

The analytical model of [Xi04] has been used with the same input values as for the Pspice model. Therefore, fixed values have been used for the MOSFET’s non-linear parasitic capacitances for reasons of simplicity. These have been determined by integrating and averaging (B.10) over the applied voltage.

Using the input values of Table B-1 to Table B-4, a MOSFET turn-off time of about toff=9.5ns has been determined for all four layouts, as previously described and experimentally determined in Section 5.4.3. The similarity of the turn-off times among the layouts is mainly accounted to the nearly constant source inductance.

258 Appendix B

Results

Besides the parasitic inductances, the trace resistances are required to determine the resulting loss distribution in the case study converters. These values have already been presented in Figure 5-35 and are repeated in Table B-5.

Table B-5: Layout parasitic resistances from PEEC model – values in mΩ

Layout R1 R2 R3 R4 R5 R6

35μmCu_min 1.80 6.40 3.27 2.87 2.80 3.0735μmCu_max 0.36 1.40 0.70 0.90 1.20 0.70

10μmCu 3.06 8.85 2.90 4.80 5.30 5.855μmCu 5.68 16.70 5.30 6.50 12.20 9.52

The currents flowing through the components are given in Table B-6 and have been calculated according to the converters’ waveforms and component values.

Table B-6: Calculated currents and flux-density in case study

Calculated currents and flux density

MOSFETQ

DiodeD

Inductorwindings

Magneticcore

Average current [A] 0.42 0.57 0.99 -

RMS-current [A] 0.75 0.87 1.15 -

Peak flux density [T] - - - 0.17

The converter losses have been calculated by using equations (B.1) to (B.10) with input parameters defined in Table B-1 to Table B-6 as introduced throughout this section.

Table B-7: Predicted losses and efficiency in case study layouts

Loss prediction

MOSFETQ

DiodeD

Inductorwindings

Magneticcore

Layout – circuit traces

35μmCu_min 35μmCu_max 10μmCu 5μmCu

Losses [W]

0.21 0.285 0.2 0.29 0.17 0.004 0.026 0.048

Predicted efficiency [%] 92.5 92.7 92.5 92.3

It can be seen from Table B-7, that all converters achieve an efficiency of about 93 percent at nominal input voltage. It is also noticeable that the circuit trace losses are negligibly small when compared to the component losses. The losses are quite uniformly distributed among


the semiconductor components and the input filter inductance. The comparably high inductor losses are accounted to the selection of a small footprint SMT component and could further be decreased by an alternative inductor choice.

B.3. Inductor realisation possibilities and inductor loss-comparison

Integration of planar core inductances

The utilisation of the PCB as circuit carrier for inductor windings or inductive and capacitive layers contributed to an increased functional integration and reduction of discrete components on printed circuit boards [Po05], [WF02]. Up to now, state of the art 3D-MIDs do not allow multilayer structures required for these additional capacitive or inductive layers, as already discussed in Chapter 5. However, different solutions exist to use the 3D-MID substrate as winding carrier for planar ferrite cores, which will be summarised in the following. The different inductor realisation options have been considered by utilising solutions already used in PCB-based power converters [JFB06]. As in PCBs, discrete SMT inductances (Figure B-4) (a)) can be used on 3D-MID, but require additional contacting and placing in three-dimensions.

Figure B-4: Possibilities for inductor realisation on 3D-MID (cross sections)

Planar cores with integrated windings can also be used on the 3D-MID which allow a reduction of the component height and reduce the contacting effort, shown in Figure B-4 (b)-(d). However, the direct integration of the inductor windings on 3D-MIDs is in general adifficult option, as a very low fill factor is achieved due to the reduced track thickness and the lack of multiple winding layers.

Hence, additional winding carriers are required in order to effectively use planar cores on 3D-MIDs, e.g. with SMT coil formers or with additional rigid or flexible PCB-windings. These structures achieve significantly higher fill factors and hence lower conduction losses. Planar transformers can be implemented in a similar way by using two SMT coil formers, where the high voltage side is attached to one side of the 3D-MID and the low voltage side is attached to the opposite (Figure B-4 (d)).

a.) SMT-inductance b.) direct integrated windings on 3D-MID

c.) SMT coil former on 3D-MID

planar core

3D-MIDwindings

coil former d.) planar transformer with SMT coil former

260 Appendix B

Example of power losses of inductor realisations on 3D-MIDs

A comparison of inductor losses of planar integrated inductances on 3D-MID to PCBs, corresponding to Figure B-4 (b) is performed next. The calculation gets accomplished by the calculation of the expected inductor losses of a standard SMT inductance with winding carrier, as shown in Figure B-4 (c).

The calculation input parameters are summarized in Table B-8.

Table B-8: Inductor parameters used for calculation [EP06]

Core parameters Winding parameters

Planar core

SMTinductance

Winding type PCB integrated

3D-MID integrated Wire wound

Type EPCOS EILP14

EPCOS EP7

Specific winding resistance [Ωm] 1.78E-8 2.66E-8 1.78E-8

Core volume Ve

[mm³]242 162 Number of turns N Dependent on air gap size

Core cross section Ae

[mm²]14.3 10.3 Number of winding

layers used NL4 2 -

Core window [mm]

2x4 -Mean winding length

[mm]26 26 15

Core material, permeability

μr

N87, 2200 Copper thickness tCu [μm] 70 15 -

Air gapll[μm]

Variable (running parameter to

obtain desired L)

Circuit track distance dtrace

[μm]150 200 -

Smallest ELP cores (EILP 14/3.5/5) have been selected for the planar integrated inductances.A SMT inductance of comparable size (EP7 and individually configurable winding carrier has been further used for reasons of comparison. The inductances aim to achieve an inductance value of L=6.1μH, as used in Prototype 1. The inductance calculation is performed in the same way as in Appendix B, by using a simple magnetic resistance model consisting of the ampere-turns Ni (magnetomotive force), the magnetic resistance of the core Rm_ferrite and the magnetic resistance of the air-gap Rm_air-gap [Er01].

The length of the air gap and the number of windings N influence the losses in the core and the resistive losses in the windings. Thus, calculations have been performed to quantify the overall losses in the inductors depending on the length of the air gap.

For the calculation of the magnetic flux density an input current excitation of ΔI=2A and a switching frequency of f=300kHz has been used. The calculation of the magnetic losses has


been performed according to Legg’s equation [Le3615]. Since for these ferrite materials at frequencies below 1MHz the eddy current losses are only a small fraction of the total core losses, this equation has been approximated as:

(B.11)

with Ve = Core volume [m³] k1,k2,k3 = Material parameters derived from the datasheet charts Bpk = Peak magnetic flux density [T] fo = Repetition frequency, switching frequency [Hz]

The material parameters k1, k2 and k3 and the core volume Ve have been derived from the datasheet for the material N87. The following values were obtained: k1 = 0.081, k2 = 2.907and k3 = 4.0 10-5.

For the calculation of the RMS currents a boundary of DCM with D=0.5 has been assumed. The calculation of the winding resistances of the EP7 inductances assumes a constant fill factor of 0.3 which is maintained in the calculation by adjusting the winding diameter according to the required winding number N.

The winding dimensions of the planar core inductors have been calculated by using the required distances between circuit traces and the magnetic core dtrace, as well as the available number of circuit layers NL. These parameters are also defined in Table B-8. The resulting trace width wtrace can then be calculated with:

(B.12)

with wwindow = Width of magnetic core’s winding window [m]dtrace = Distance among circuit traces and to magnetic core [m] N = Number of required windings

Figure B-5 shows the resulting inductor losses versus the air gap length. At small air-gaps, the core losses dominate and at large air-gaps the winding losses dominate. To obtain the desired inductance values, the required winding numbers N_x are plotted as dotted line on the second y-axis for the planar core integrations, as well as for the SMT inductance.

It can be seen that both the planar core integration on PCBs as well as the SMT inductance show significantly lower inductor losses then the 3D-MID planar core integration. This is accounted by the low copper layer thickness available on 3D-MIDs as well as the low fill factor achieved with 3D-MIDs. The PCB integration with 4 layers shows losses comparable to the SMT inductance example with minimum losses at an air gap of 40μm, requiring 6 windings for the given inductance value.

262 Appendix B

Figure B-5: Comparison of inductor losses versus air gap length with corresponding winding number N

As a consequence, the prototypes used throughout this thesis are realised with SMT inductances, whenever a 3D-MID-based design is used. This is the case for prototypes 2-3 and the final LED-lighting system of Chapter 7.

0

5

10

15

20

25

30

35

0

0.1

0.2

0.3

0.4

0.5

0 50 100 150 200 250

Win

ding

num

ber

N

Indu

ctor

loss

es [

W]

Air gap [μm]SMD PCB (4-layers) MID (2-layers)N_SMD N_PCB/ N_MID

Bibliography [EP06] EPCOS AG: Ferrites and Accessories, 2006.

[Er01] Erickson, R. W.: Fundamentals of Power Electronics. Springer Science+Business Media, Inc, 2001.

[JAS01] Jieli, L.; Abdallah, T.; Sullivan, C.: Improved calculation of core loss with nonsinusoidal waveforms. In 2001. Thirty Sixth IAS Annual Meeting. Conference Record of the 2001 IEEE Industry Applications Conference, 2001, 4; pp. 2203–2210.

[JFB06] Jong, E. de; Ferreira, J.; Bauer, P.: Integrated Flex Winding Realisation for 3D PCB Converters: Proc. 37th IEEE Power Electronics Specialists Conference PESC ’06, 2006.

[Kl] Klein, J.: Synchronous buck mosfet loss calculation with EXEL model. Application note AN-6005.

[Le3615] Legg, V.: Magnetic Measurements at Low Flux Densities Using the Alternating Current Bridge. In Bell system technical journal, 1936; pp. 39–62.

[Me08] Meade, T.; O'Sullivan, D.; Foley, R.; Achimescu, C. et al.: Parasitic inductance effect on switching losses for a high frequency Dc-Dc converter. In 2008. APEC 2008. Twenty Third Annual IEEE Applied Power Electronics Conference and Exposition, 2008; pp. 3–9.




[UHP10] Utz, S.; Hackner, T.; Pforr, J.: A novel tri-state driver to improve the switching performance in automotive converter. In 2010 14th International Power Electronics and Motion Control Conference (EPE/PEMC), 2010; pp. T2-110.



[WF02] Waffenschmidt, E.; Ferreira, J.: Embedded passives integrated circuits for power converters: Proc. 33rd Annual Power Electronics Specialists Conference PESC, 2002; pp. 12–17.

[Xi04] Xiao, Y.; Shah, H.; Chow, T.; Gutmann, R.: Analytical modeling and experimental evaluation of interconnect parasitic inductance on MOSFET switching characteristics. In 2004. APEC '04. Nineteenth Annual IEEE Applied Power Electronics Conference and Exposition, 2004, 1; pp. 516–521.

C. Appendix: Thermal-modelling and -simulation

C.1. Introduction

In this part, further information on the thermal management analysis and simulations performed in Chapter 6 is given.

Section C.2 gives an overview of the used correlations for calculating the radiative- and convective- heat transfer, used in the circuit-carrier-based thermal management design (performed in Section 6.4), as well as for the design and analysis of the integrated reflector heat sink (performed in Section 6.5).

In Section C.3, additional parameters on the calculation and thermal FEM simulation of the case study buck-boost converter of Section 6.4.2 are given for reasons of clarity.

C.2. Equations for convective and radiative heat transport

The thermal analysis and simulations used in Chapter 6 are based on natural convection cooling and cooling by radiation.

The heat dissipated by radiation is defined by the Boltzmann law:

Δ (C.1)

with σ = Stefan–Boltzmann constant: 5.67·10-8 J/(s·m²·K4) ε = Surface emission coefficient

Aactive = Surface area that contributes to radiation [m²] ΔT = Temperature rise [K]

The correlations used to calculate the convective heat transfer from vertical and horizontal plates are commented in the following.

The heat that is dissipated by means of natural convection is treated as the power that can be transported convectively in total from a component’s surface.

Δ (C.2)

with Pconvi = Power convectively transported from single surface [W] n = Number of contributing surfaces

The convective heat transport of a surface is not only temperature dependent, but also influenced by its geometry and the orientation in space. The power dissipated from a vertical plate with uniform temperature distribution Pconv_vertical can be written as:

266 Appendix C

Δ Δ Δ (C.3)

with Aplate = The plate surface area [m²] hvert(ΔT) = Heat transfer coefficient [W/m²K]

The power transfer from the horizontally surfaces Pconv_horizontal, can be calculated in a similar way:

Δ Δ Δ (C.4)

with Aplate = The plate surface area [m²] hhor(ΔT) = Heat transfer coefficient [W/m²K]

The heat transfer coefficients hvert and hhor are determined by correlations between the dimensionless Grashof (Gr), Prandtl (Pr), Rayleigh (Ra) and Nusselt (Nu) numbers. These are defined in equations (C.5)-(C.10), according [Re01].

(C.5)

with L = Characteristic length [m] ρ = Fluid density [kg/m³] g = Gravity [m/s²] ΔT = Temperature difference between plate and ambient [W/m²K] β = Expansion coefficient of the fluid [1/K] μ = Absolute viscosity of the fluid [N·s/m²]

The characteristic length L is geometry-dependent and is defined as: L= plate height for vertical plate orientations and L= plate surface/plate perimeter for horizontally-oriented plates.

The Prandtl number is defined as:

(C.6)

with Cp = Heat capacity of the fluid [J/K] λ = Thermal conductivity of the fluid [W/mK] μ = Absolute viscosity of the fluid [N·s/m²]

The Rayleigh number is the product of the Prandtl and Grashof numbers. The Nusselt number is generally defined as:

(C.7)

Thermal-modelling and -simulation 267

with L = Characteristic length [m] λ = Thermal conductivity of the fluid [W/mK] h = Heat transfer coefficient [W/m²K]

Different correlations exist for the Nusselt number and have been presented in the literature. Most of them are dependent on the dimension of the Raleigh number and have to be selected appropriately. An extensive overview of correlations for vertical and horizontal plates is given in [LK83]. The heat transfer coefficients used in this work are also given in [Re01], [HRC98] and are summarised in the following:

Vertical heated plate with laminar flow:

(C.8)

Horizontal heated plate facing upwards:

for 104 ≤ Ra ≤107 (C.9)Horizontal heated plate facing downwards:

for 105 ≤ Ra ≤1010 (C.10)

C.3. Case study buck-boost converter thermal modelling and simulation

In this section, additional information on the implementation of the thermal management simulation of the buck-boost converter prototype of Section 6.5.2 is provided for a better understanding of the simulation configuration. This contains the converter specification, component values and expected current values which serve as input data for the converter loss analysis performed in analogy to Appendix B. These values are used as input parameters for the thermal FEM.

In addition, further details concerning the thermal FEM simulations of Section 6.5.2 are given for reasons of clarity.

C.3.1. Converter specification

The two-branch buck-boost converter with inductive power sharing, investigated in Section 6.5 and [TP11], is supposed to drive an automotive daytime-running-light, with twelve LEDs arranged in two parallel branches to avoid undesired high output voltages. The system is directly operated from the 14V electrical automotive power net.

268 Appendix C

The converter has the target specifications as defined in Table C-1.

Table C-1: Case-study converter operating conditions


Switchingfrequencyfs [kHz]

Total number of LEDs

ParallelLED

branches

LED power (total)[W]

LEDcurrent

ILED [mA]

LEDvoltage

VLED [V]

8.5-17V 120-310 12 2 12 300 20

The converter is operated with frequency adjustment between 120-310kHz to compensate input voltage changes. The main component values and related datasheets are shown in Table C-2.

Table C-2: Components used in case-study prototypes



Cin2x10μF/

25V 0805 Q SUD23N06 [Vi08] D-PAK

Cout9.4μF/ 50V 1206 DBx, DFx STPS2L60 [ST11] SMA

L 22μH EPCOS EP7

The average and root-mean-square currents that appear in the converter have been calculated for minimum-, nominal- and maximum input voltage and are given in Table C-3.

Table C-3: Breakdown of main currents over input voltage: Iavg/ IRMS

Input voltage

Vin

[V]

Branch diodes

DBx

Iavg / IRMS [A]

Free-wheeling diodes DFx

Iavg / IRMS [A]

MOSFETQ

Iavg / IRMS [A]

Inductors Lx

Iavg / IRMS [A]

8.5 0.75/1.02 0.3/0.65 0.6/1.49 -/1.21

14 0.44/0.66 0.3/0.55 0.89/1.32 -/0.86

17 0.36/0.57 0.3/0.515 0.73/1.13 -/0.76

The converter parameters specified in Table C-1 to Table C-3 are used to calculate the converter losses by means of the loss calculation given in Appendix B. The results of the calculations are summarised in Section 6.4.2 and are used as input parameters in the thermal modelling.

Thermal-modelling and -simulation 269

C.3.2. Thermal modelling

The buck-boost converter’s finite element modelling and the progress of data generation from the circuit layout to the final 3D FEM model are briefly described in the following.

Model generation

The footprint of the copper traces and related dimensions have been exported from a 2D circuit routing software and have been imported in 3D-CAD software to construct a 3D-model of the converter. This contains the circuit carrier with substrate and the respective copper layers. In a next step, the essential power converter components have been modelled. It was taken care that identical dimensions have been obtained as defined by the real component values (related datasheets are given in Table C-2). The resulting 3D-CAD model of Layout 2 with circuit carrier and main components is repeated in Figure C-1.

Figure C-1: Layout 2 – (a) 3D model and (b) top-view of layout with considered components

Component models

The component packages have been modelled as solid blocks with a thermal resistance that represents the package’s (junction to case) resistance. The resulting circuit carrier and component parameters are provided for Layout 2 in Table C-4. The detailed copper area dimensions surrounding each component have been introduced in Table 6-8. It is noted in Table C-4, whether the package’s thermal resistance or the material’s thermal conductivity has been provided by the datasheet. The congruent values have been calculated, as also indicated in the table.

QDF2

DB2DB1

DF1

L1 L2

(b)(a)

270 Appendix C

Table C-4: Thermal resistances and material values used in FEM simulation of buck-boost converter Layout 2

Copper layer Substrate

layerMOSFET package

Diode package

Inductor core

material

Footprint area A [cm²]

See Table 6-8 9.76 0.417 0.136 0.69

Component height h [mm]

0.01 1.5 2.39 2 6.5

Model thermal conductivityλ [W/mK]

394 0.28(datasheet)

18(calculated)

5.98(calculated)

4(datasheet)

Package thermal resistanceRth [K/W]

-5.49

(calculated)3.2

(datasheet)24.59

(datasheet)23.5

(calculated)

Heat transfer models

The power losses, calculated in Table 6-5 have been directly applied to the components. Anemission coefficient of εr=0.88 has been used to model the radiative heat transfer and has been set as constant value in the simulation for reasons of simplicity.

Temperature-dependent heat transfer coefficients have been further used for the simulation of the convective heat transfer. These values have been calculated according to equations (C.5)-(C.10). The calculations of the heat-transfer coefficient have been performed individually for the tested ambient temperatures: Tambient=30°C and Tambient=80°C.

Bibliography [HRC98] Hartnett, J. P.; Rohsenow, W. M.; Cho, Y. I.: Handbook of heat transfer. McGraw-Hill,

New York, 1998.

[LK83] Lewandowski, W. M.; Kubski, P.: Methodical investigation of free convection from vertical and horizontal plates: Wärme - und Stoffübertragung. Springer, 1983; pp. 147–154.



[TP11] Thomas, W.; Pforr, J.: Design of power converters on 3D-MIDs for driving three-dimensional LED-lamps. In 2011 IEEE Energy Conversion Congress and Exposition (ECCE), 2011; pp. 325 332.


SUMMARY Integrated Automotive High-Power LED-Lighting Systems in

3D-MID Technology

PhD Thesis

by Werner Thomas

The growing energy consumption of lighting – 19 percent of the global energy production in 2006 – as well as rising luminous efficacies and -fluxes of high-power Light Emitting Diodes (LEDs) have contributed to the widespread use of LEDs in modern lighting systems. One of the most prominent users of the LED-technology is automotive (exterior) lighting. It benefits from LEDs’ high efficiencies and long lifetimes, but furthermore uses their small size as key feature to obtain new degrees of freedom in placing light elements. This can be skilfully used to obtain unique designs that serve as recognition feature to stand out from the competitors and to provide a diversification in between the model-range of a car manufacturer. In addition, innovative lighting functions get possible by combining a multitude of spatially distributed LEDs. Hence, systems can be created that highly exceed the features of those with conventional central light sources. Although automotive LED-lighting is at the leading edge regarding 3D LED-lighting systems, their current construction is not optimised towards complex design requirements.

This thesis deals with decreasing the complexity and improving the degrees of freedom in the design of three-dimensional high-power LED-lighting systems with LED-driver by enhancing the level of function integration.

Analysis of present practice and evolution of (3D) LED-lighting system construction

Todays approach of realising 3D LED-lighting systems with increased LED-power is dominated by the use of a multitude of components that fulfil electrical, spatial and thermal functions. In the vast majority of applications these components only address single functions, which lead to complex assemblies with a plurality of components.

To enable more sophisticated systems, an approach has to be found that unites the technologies of creating electrical, spatial and thermal functions. It is identified in this thesis, that obtaining a high flexibility in 3D-design as well as decreasing the number of components are essential parameters that should be focused on to enhance the degrees of freedom of future LED-lighting systems. Both aspects are directly linked to the available circuit carrier technology and its 3D-shaping possibilities. A concept that uses the circuit carrier technology of 3D-Moulded Interconnect Devices (3D-MID) as 3D-“Multi-functional” Interconnect Device that performs spatial, electrical and thermal functions is suggested in this thesis to make future LED-lighting systems with enhanced three-dimensional shaping possible.

Up to the present, 3D-MIDs are only available for low-power systems with low complexity. When considering the MID as a multi-functional component to enhance LED-lighting systems

274 Summary

with higher power levels new challenges arise. These are mainly determined by increased(LED) power levels, leading to increased power losses and demanding complex LED-drivers that have to be implemented on the 3D-MID. Three main challenges are identified for the proposed concept and are investigated throughout the thesis. These are the integration of:

LED-driver functions Spatial - and electrical-functions

Thermal management functions

Development of adapted LED-driver topologies for 3D-MID realisation

The separation and independent design of the dc-dc power converter and of brightness balancing- as well as dimming-networks in state of the art LED-drivers leads to increased circuit layout complexity and component count, which has been identified as severe hurdle for a 3D-MID integration. For this reason, adapted LED-drivers are developed in this thesis to enable a simplified realisation on 3D-MIDs. This is mainly obtained by two integration steps.

The integration of the current balancing network is achieved with the development of a novel principle of inductive brightness distribution that uses single branch inductances and discontinuous inductor currents to compensate LED forward voltage deviations. It works without active components and allows a simplified 3D-MID realisation due to low wiring complexity and low numbers of components required. The technique can be directly applied to a variety of different isolated and non-isolated power converter topologies.

The integration of the external PWM-dimming network is obtained by modulating the drive signal of the power converter’s active switch with a low frequency signal to generate the desired PWM LED-current. This allows the replacement of commonly used external PWM-dimming networks and serves as further means to decrease the component count as well as the wiring complexity in the LED-driver.

Influence of 3D-MID usage on electrical and spatial realisation of power electronics

The 3D-MID technology offers significantly different spatial- and electrical interconnection options when compared to state of the art printed circuit boards. It is determined in this thesis that the process of creating the circuit artwork limits the available circuit routing variances as well as the Current Carrying Capacity (CCC). The most convenient solution to overcome this limitation is identified as the increase of the circuit trace width rather than the copper thickness. However, this decreases the circuit density manifesting in rising contacting challenges of components, increased component distances and enlarged parasitic layout inductances.

The influence of 3D-MIDs on the spatial and electrical performance of power converters is analysed in detail, in this thesis. Circuit trace parasitic extraction combined with analytical modelling and simulation of the expected electrical behaviour are used as means to determine the feasibility of prospective power converters on 3D-MIDs. In addition, solutions to overcome routing issues by using 3D-shaping of the substrate are presented.

Summary 275

Thermal management of 3D-MID-based LED-lighting systems

The converter level thermal management is identified as the central domain that challenges the cooling of power electronic components and of the high-power LEDs on 3D-MIDs. Different techniques to obtain 3D-MID cooling are taken into consideration. Two thermal management concepts are identified in this thesis to obtain component cooling whilst maintaining the versatile 3D-shaping possibilities of 3D-MIDs.

3D-MID-based thermal management is available for the cooling of low power levels by using its copper layer not only for routing- but also for thermal-management functions. It is determined that high perpendicular thermal resistances as well as the limited heat spreading performance, due to 3D-MIDs’ low copper layer thicknesses, highly restrict the processable power level. As low complexity circuit layouts are required on 3D-MIDs, the integration of thermal management functions gets further challenged. The techniques to achieve 3D-MID based cooling of the developed low-complexity LED-drivers are determined in this thesis.

The Integrated Reflector Heat Sink (IRHS) concept is developed as technique to extend the power level of 3D-MID-based LED-lighting systems. The IRHS integrates thermal management- and optical functions in a single component. It allows the direct heat transport from the surface where the components are attached, which circumvents the limitation of 3D-MID’s in heat transport and therefore provides significantly reduced thermal resistances to the ambient. The IRHS can be assembled by injection moulding of thermally conductive polymers to ideally match the 3D-shape of the 3D-MID to further decrease thermal resistances.

SAMENVATTING Integrated Automotive High-Power LED-Lighting Systems in

3D-MID Technology

Proefschrift

door Werner Thomas

Het toenemende energieverbruik door verlichting – 19% van de wereldwijde energieproductie in 2006 – en de stijgende lichtopbrengst en specifieke lichtstroom van hoogvermogen Light Emitting Diodes (LEDs) hebben bijgedragen aan het grootschalige gebruik van LEDs in moderne verlichtingssystemen. Eén van de grootste gebruikers van LED-technologie is de auto-industrie, voor zowel binnen- als buitenverlichting. Het hoge rendement en de lange levensduur van LEDs zijn welkome eigenschappen, maar het grootste voordeel is hun kleine omvang, die nieuwe vrijheden in het ontwerp van verlichtingselementen mogelijk maakt. Hiermee kunnen unieke ontwerpen gemaakt worden om op te vallen tussen concurrenten en onderscheid te creëren tussen de modellen van een autofabrikant. Een grote hoeveelheid LEDs uitspreiden over een groter oppervlak biedt nog meer mogelijkheden voor opvallende verlichtingssystemen. LEDs maken dus significant betere systemen mogelijk dan conventionele lichtbronnen. Hoewel LED-verlichting voor voertuigen vooroploopt in LED-verlichting, zijn de huidige ontwerpen niet optimaal ten aanzien van de complexe ontwerpeisen.

Dit proefschrift richt zich op het verlagen van de complexheid en het verhogen van de ontwerpvrijheden van driedimensionale hoogvermogens-LED-verlichtingssystemen inclusief de aansturing, door het integratieniveau te verhogen.

Analyse van de evolutie en huidige stand van (3D) LED-verlichtingssysteemconstructie

Het huidige ontwerp van 3D LED-verlichtingssystemen met hoger LED-vermogen wordt gedicteerd door een veelvoud aan componenten die elektrische, ruimtelijke en thermische functies vervullen. In veruit de meeste toepassingen wordt elke functie door een apart onderdeel vervuld, wat leidt tot complexe constructies met een groot aantal componenten.

Om complexere systemen mogelijk te maken is een aanpak nodig die de technologieën voor de elektrische, ruimtelijke en thermische rollen samenvoegt. Dit proefschrift stelt vast dat het verkrijgen van een grote flexibiliteit in 3D-ontwerpen en het verlagen van het aantal componenten essentieel zijn en veel aandacht moeten krijgen om de ontwerpvrijheden in toekomstige LED-verlichtingssystemen te vergroten. Deze aspecten houden beide direct verband met de beschikbare circuitdragertechniek en de 3D-mogelijkheden daarvan. Een concept waarin de circuitdragertechniek 3D-Moulded Interconnect Devices (3D-MID) gebruikt wordt als 3D-‘multi-functionele’ verbindingstechniek die ruimtelijke, elektrische en thermische functies vervult wordt voorgesteld in dit proefschrift om toekomstige LED-systemen met verbeterde driedimensionale vormgeving mogelijk te maken.

278 Samenvatting

Tot op heden is 3D-MID alleen beschikbaar voor laagvermogenssystemen met weinig complexiteit. Bij de toepassing van MID als multifunctioneel onderdeel ter verbetering van LED-systemen dienen zich nieuwe uitdagingen aan. Deze komen met name voort uit het hogere LED-vermogen, wat tot hogere verliezen leidt en waarvoor complexere aansturingen nodig zijn die geïntegreerd moeten worden op de 3D-MID. Drie hoofduitdagingen voor het voorgestelde concept worden vastgesteld en worden steeds behandeld in dit proefschrift. Dit zijn:

LED-aansturingsfuncties

Ruimtelijke en elektrische functies

Koelingsfuncties

Ontwikkeling van LED-aansturingstopologieën aangepast voor 3D-MID implementatie

De scheiding en afzonderlijke implementatie van de DC-DC-omzetter, stroombalanceercircuits en dimcircuits in state-of-the-art LED-aansturingen leidt tot een complexere circuit-layout en een meer componenten, wat gezien wordt als groot obstakel voor 3D-MID integratie. Daarom worden in dit proefschrift aangepaste LED-aansturingen ontwikkeld die een eenvoudige 3D-MID-realisatie toe laten. Deze ontwikkeling bestaat uit twee integratiestappen.

De integratie van het stroombalanceringsnetwerk wordt bereikt door ontwikkeling van een nieuw soort inductieve stroomverdeling, gebaseerd op losse spoelen en discontinue spoelstromen om verschillen in LED-doorlaatspanningen op te vangen. De voorgestelde techniek heeft geen extra actieve onderdelen nodig en maakt een eenvoudige 3D-MID-implementatie mogelijk doordat er slechts weinig verbindingen en onderdelen nodig zijn. Deze techniek kan direct toegepast worden op een verscheidenheid aan geïsoleerde en ongeïsoleerde vermogensomzetters.

De integratie van het externe PWM-dimcircuit wordt mogelijk gemaakt door het aanstuursignaal van de actieve schakelaar in de omzetter te moduleren met een laagfrequent signaal om de gewenste LED-stroom te verkrijgen. Hierdoor kunnen de gebruikelijke externe PWM-dimcircuits vervangen worden en worden het aantal componenten en de bedradingscomplexiteit van de LED-aansturing nog verder teruggebracht.

Invloed van 3D-MID-gebruik op de elektrische en ruimtelijke realisatie van vermogenselektronica

De 3D-MID-techniek biedt substantieel andere fysieke- en elektrische verbindingsmogelijkheden dan state-of-the-art printplaten. In dit proefschrift wordt vastgesteld dat het proces waarmee de sporen worden gemaakt zowel de maximale stromen als de variatie in layout-mogelijkheden beperkt. Het wordt verder vastgesteld dat de gunstigste oplossing voor dit probleem het verbreden van de sporen is, in plaats van het gebruik van een dikkere koperlaag. Dit verlaagt echter de dichtheid van de schakeling, wat leidt tot verbindingsproblemen van de onderdelen, grotere onderlinge afstanden en verhoogde parasitaire inductanties.

Samenvatting 279

In dit proefschrift wordt de invloed van 3D-MID op de ruimtelijke en elektrische prestaties van vermogensomzetters in detail geanalyseerd. Met parasitic extraction van printsporen, gecombineerd met analytische modellen en simulaties van het verwachtte elektrische gedrag, wordt de geschiktheid van kandidaat-vermogensomzetters op basis van 3D-MID bepaald. Daarnaast worden oplossingen voor routingsproblemen op basis van 3D-vorming van het substraat voorgesteld.

Thermisch management van 3D-MID-gebaseerde LED-verlichtingssystemen

Het thermisch management op omzetter-niveau wordt gezien als het centrale onderwerp dat de koeling van de vermogenselektronica en de hoogvermogens-LEDs op 3D-MIDs bemoeilijkt. Verschillende techieken voor koeling van de 3D-MID worden overwogen. Twee thermische management-concepten voor de koeling van de componenten waarbij de 3D vormgevingsmogelijkheden van 3D-MID behouden blijven, worden in dit proefschrift geïdentificeerd.

3D-MID-based thermal management kan gebruikt worden bij lage vermogens door de koperlaag niet alleen voor elektrische maar ook thermische geleiding te gebruiken. Het wordt vastgesteld dat hoge loodrechte thermische weerstanden en de beperkte hitte-spreidende capaciteit, veroorzaakt door de dunne koperlaag bij 3D-MID, het te verwerken vermogen sterk beperken. Het integreren van de thermische functies wordt verder bemoeilijkt door de beperkte haalbare complexiteit van 3D-MID-schakelingen. De technieken om 3D-MID-gebaseerde koeling mogelijk te maken voor de eenvoudigere LED-drivers worden vastgesteld in dit proefschrift.

Het Integrated Reflector Heat Sink (IRHS) (koelblok met geintegreerde reflector) concept is ontwikkeld om het vermogen van 3D-MID-gebaseerde LED-verlichtingssystemen te verhogen. De IRHS combineert thermische management en optische functies in één onderdeel. Bij een IRHS kan de warmte direct vanaf het oppervlak waar de componenten zich bevinden weggevoerd worden, wat de beperkingen van 3D-MIDs qua warmtegeleiding wegneemt, en dus aanzienlijk lagere thermische weerstanden naar de omgeving oplevert. De IRHS kan gemaakt worden door spuitgieten van warmtegeleidende polymeren om zo optimaal aan te sluiten op de 3D-vorm van de 3D-MID en de thermische weerstand nog verder te verlagen.

ZUSAMMENFASSUNG Integrierte automobile Hochleistungs-LED-Beleuchtungssysteme

in 3D-MID Technologie

Dissertation

von Werner Thomas

Der steigende Energiebedarf im Beleuchtungsbereich – 19 Prozent der globalen Energieerzeugung im Jahr 2006 – sowie steigende Lichtausbeuten und erhöhte Lichtströme von Hochleistungs- Licht-Emittierenden-Dioden (LEDs) haben zum weitverbreiteten Einsatz von LEDs in modernen Lichtsystemen beigetragen. Eine der prominentesten Anwendungen der LED-Technologie ist die automobile (Außen-) Beleuchtung. Diese profitiert von den hohen Wirkungsgraden sowie langen Lebensdauern von LEDs und nutzt darüber hinaus deren kompakte Abmessungen als Schlüsseleigenschaft, um neue Freiheitsgrade in der Platzierung von Lichtquellen zu erreichen. Dies kann geschickt dazu genutzt werden einzigartige Lichtdesigns zu kreieren, als Alleinstellungsmerkmal gegenüber dem Wettbewerb und zur Diversifikation innerhalb der Modellpalette eines Herstellers. Darüber hinaus werden innovative Lichtfunktionen durch die Kombination einer Vielzahl räumlich verteilter LEDs möglich. Infolgedessen können Systeme entwickelt werden, deren Eigenschaften die Möglichkeiten konventioneller (zentraler) Lichtquellen bei Weitem übersteigen. Wenngleich die automobile LED-Beleuchtung eine führende Rolle im Bereich dreidimensionaler LED-Lichtsysteme innehat, so ist deren aktuelle Konstruktion nicht für komplexe Designanforderungen optimiert.

Diese Dissertation befasst sich mit der Erhöhung der Funktionsintegration in LED-Lichtsystemen hoher Leistung um deren Komplexität zu reduzieren sowie die Freiheitsgrade im Design zu erhöhen.

Analyse der aktuellen Praxis und der Evolution in der Konstruktion von (3D) LED-Lichtsystemen

Der gegenwärtige Ansatz zur Realisierung von LED-Lichtsystemen mit erhöhter LED-Leistung wird durch den Einsatz einer Vielzahl an Komponenten, die elektrische-, räumliche- und thermische Funktionen erfüllen, dominiert. Diese Komponenten erfüllen in der breiten Mehrheit der Anwendungen lediglich eine einzige Funktion und führen daher zu komplexen Systemen mit einer Vielzahl an Einzelkomponenten.

Um weiterentwickelte Systeme zu ermöglichen ist es daher notwendig, einen Ansatz zu entwickeln, der die einzelnen Technologien zur Erzeugung elektrischer-, räumlicher und thermischer Funktionen vereint. Im Zuge dieser Arbeit wird identifiziert, dass sowohl die Ermöglichung einer hohen Designflexibilität in 3D als auch die Reduktion von Komponenten essentielle Bausteine sind um die Freiheitsgrade zukünftiger LED-Lichtsysteme zu erhöhen. Beide Aspekte sind direkt mit der zur Verfügung stehenden Schaltungsträger-Technologie und deren Möglichkeiten in dreidimensionaler Formgebung verknüpft. In dieser Dissertation

282 Zusammenfassung

wird ein Konzept vorgeschlagen, das die Schaltungsträgertechnologie der 3D-MouldedInterconnect Devices (3D-MID) als 3D-“Multi-funktionales” Interconnect Device nutzt, welches elektrische-, räumliche- und thermische Funktionen erfüllt, um zukünftige LED-Lichtsysteme mit erhöhten Freiheitsgraden im Design zu ermöglichen.

Zum gegenwärtigen Zeitpunkt werden 3D-MIDs in Systemen niedriger Leistung und geringer Komplexität eingesetzt. Durch den Ansatz 3D-MIDs als multi-funktionale Komponente zu nutzen, um 3D LED-Lichtsystemen hoher Leistung zu ermöglichen, entstehen neuartige Herausforderungen. Diese sind primär durch die erhöhte (LED-) Leistung begründet, da erhöhte Verlustleistungen abgeführt und komplexere LED-Treiber auf dem 3D-MID realisiert werden müssen. Drei zentrale Aufgabenstellungen stellen sich für das hier vorgeschlagene Konzept, die im Rahmen dieser Arbeit untersucht werden. Diese sind die Integration von:

LED-Treiber Funktionen Räumlichen- und elektrischen Funktionen

Funktionen des Thermischen Managements

Entwicklung angepasster LED-Treiber für eine Realisierung auf 3D-MIDs

Die Trennung sowie die separate Auslegung von DC/DC-Wandlern und Stromsysmmetrierungs- sowie Dimmungsnetzwerken aktueller LED-Treiber führen zu erhöhter Komplexität im Schaltungslayout und zu einer Vielzahl an Bauteilen. Dies stellt ein beträchtliches Hindernis für eine Realisierung von LED-Treibern auf 3D-MIDs dar. In dieser Dissertation werden daher angepasste LED-Treiberelektroniken entwickelt, die eine vereinfachte Realisierung auf 3D-MIDs ermöglichen. Dies wird primär durch zwei Integrationsschritte ermöglicht:

Die Integration des externen Netzwerks zur Stromsymmetrierung in den DC/DC-Wandler wird durch die Entwicklung eines neuartigen Verfahrens zur induktiviven Helligkeitsverteilung ermöglicht. Das Verfahren nutzt hierbei indviduelle Zweiginduktivitäten, die mit diskontinuierlichem Spulenstrom betrieben werden, um Toleranzen in den LED-Vorwärtsspannungen zu kompensieren. Das Prinzip benötigt keine zusätzlichen aktiven Komponenten und erlaubt durch das vereinfachte Schaltungslayout und die niedrige Bauteileanzahl eine einfache Realisierung auf 3D-MIDs.

Die Integration des externen Netzwerks zur PWM-Dimmung wird durch die modulierte Ansteuerung des aktiven Schalters im Leistungswandler erreicht. Hierbei wird ein niederfrequentes Signal dem regulären Ansteuersignal überlagert, um den benötigten pulsweiten-modulierten LED-Ausgangsstrom zu erzeugen. Dies erlaubt die Einsparung der konventionellen externen PWM-Beschaltungen und dient als weitere Maßnahme dazu, die Anzahl der notwendigen Ansteuerkomponenten sowie die Layoutkomplexität im LED-Treiber zu reduzieren.

Zusammenfassung 283

Einfluss des 3D-MID Technologieeinsatzes auf die elektrische und räumliche Realisierung von Leistungselektronik

Die 3D-MID Technologie bietet im Vergleich zur konventionellen Leiterplatten- (PCB) Technologie grundlegend verschiedene Möglichkeiten zur elektrischen und räumlichen Kontaktierung von Bauteilen. Im Rahmen dieser Arbeit wird gezeigt, dass das Verfahren zur Erzeugung des Schaltungslayouts laserstrukturierter 3D-MIDs die Möglichkeiten im Leiterbahn-Routing sowie die erzielbare Stromtragfähigkeit stark limitiert. Dabei zeigt sich, dass letztere Limitierung durch die Erhöhung der Leiterbahnbreite deutlich einfacher überwunden werden kann, als durch die Vergrößerung der Leiterbahndicke. Dies führt jedoch zu einer reduzierten Leiterbahndichte, die sich in steigenden Herausforderungen in der Kontaktierung, vergrößerten Bauteilabständen und erhöhten parasitären Layout-Induktivitäten manifestiert.

Im Zuge dieser Dissertation wird der Einfluss der 3D-MID Technologie auf das räumliche und elektrische Verhalten von Leistungswandlern detailliert untersucht. Eine Methode zur Extraktion parasitärer Komponenten des Schaltungslayouts wird dabei mit analytischen Schaltungsmodellen sowie -simulationen kombiniert, um die Realisierbarkeit zukünftiger Leistungswandler auf 3D-MIDs zu untersuchen. Darüber hinaus werden Techniken erarbeitet wie mit Hilfe der räumlichen (3D) Umformung des Schaltungsträgers die Hürden im konventionellen (2D) Routing auf 3D-MIDs überwunden werden können.

Thermisches Management von LED-Lichtsystemen in 3D-MID Technologie

Das Thermische Management auf der Ebene des Leistungswandlers ist das zentrale Feld, welches die Kühlung der leistungselektronischen Komponenten und der Hochleistungs-LEDsauf 3D-MIDs vor Herausforderungen stellt. Eine Vielzahl an Kühlungsmethoden für die 3D-MID Komponente werden in dieser Arbeit untersucht. Hierbei wurden zwei Konzepte zum Thermischen Management identifiziert, die gleichzeitig eine Kühlung der Komponenten ermöglichen und die flexible Formgebung, die durch die 3D-MID Technologie möglich ist, aufrecht erhalten.

3D-MID basiertes Thermisches Management kann für Systeme niedriger Leistung eingesetzt werden, indem die vorhandene Kupferlage nicht nur für das Schaltungslayouts, sondern auch für den Wärmetransport genutzt wird. Hierbei zeigt sich, dass die hohen thermischen Widerstände durch das Substrat hindurch sowie die limitierte Wärmespreizung – aufgrund der niedrigen Kupferschichtdicke – das Leistungsniveau deutlich begrenzen. Da darüber hinaus Schaltungslayouts mit niedriger Komplexität nötig sind, gestaltet sich der generelle Einsatz 3D-MID basierten Thermischen Managements als herausfordernd. Innerhalb der Dissertation werden Techniken und Lösungen ermittelt die entwickelten LED-Treiber niedriger Komplexität mittels 3D-MID basiertem Thermischen Management zu kühlen.

Das Konzept einer Integrated Reflector Heat Sink (IRHS) dient als Technik die Leistungsklasse 3D-MID basierter LED-Lichtsysteme zu erhöhen. Die IRHS integriert dabei Funktionen des Thermischen Managements sowie optische Funktionen in einer einzigen Komponente. Dabei ermöglicht es einen direkten Wärmetransport von der Oberfläche auf der

284 Zusammenfassung

die Bauteile kontaktiert sind, und umgeht so die Einschränkungen im konduktiven Wärmetransport in 3D-MIDs. Daher können deutlich reduzierte thermische Widerstände zur Umgebung erreicht werden. Die IRHS kann durch den Spritzguss thermisch leitfähiger Kunststoffe realisiert werden, um eine optimale Anpassung auf die 3D-Geometrie des 3D-MIDs zu ermöglichen und erlaubt eine weitere Reduktion der thermischen Widerstände.

CURRICULUM VITAE

Werner Thomas received the Dipl.-Ing. (FH) degree from the Faculty of Electrical Engineering and Information Technology of the University of Applied Sciences Ingolstadt, Germany, in 2007.

From 2007 to 2012 he has been a research assistant at the Institute of Applied Research at the University of Applied Sciences Ingolstadt, Germany. His research has been performed in a collaboration project with the Audi AG, Ingolstadt. He worked towards a Ph.D. degree in cooperation with the Electrical Power Processing group at the Delft University of Technology.

His research interests are the integration of power electronics for automotive dc-dc converters and Solid-State-Lighting systems for automotive applications.

Since October 2012, he is working in the department “development lighting functions / innovations” at the Audi AG in Ingolstadt, Germany.

Documents

Integrated Automotive High-Power LED-Lighting Systems in 3D-MID Technology