Instrumentation for Gate Current Noise Measurements on sub-100 nm MOS Transistors

L. Gaionia,c, M. Manghisonib,c, L. Rattia,c, V. Reb,c, V. Spezialia,c, G. Traversib,c

a Università di Pavia, I-27100 Pavia, Italyb Università di Bergamo, I-24044 Dalmine (BG), Italy

c INFN, Sezione di Pavia, I-27100 Pavia, Italyluigi.gaioniunipv.itAbstract

This work describes a measuring system that was developed tocharacterize the gate current noise performances of CMOS de-vices with minimum feature size in the 100 nm span. Thesedevices play an essential role in the design of present day mixed-signal integrated circuits, because of the advantages associatedwith the scaling process. The reduction in the gate oxide thick-ness brought about by CMOS technology downscaling leads to anon-negligible gate current due to direct tunneling phenomena;this current represents a noise source which requires an accu-rate characterization for optimum analog design. In this paper,two instruments able to perform measurements in two differentranges of gate current values will be discussed. Some of theresults of gate current noise characterization will also be pre-sented.

I. INTRODUCTION

In the last decade, the requirements of high granularity inthe design of the readout electronics for HEP experiments haveled to an extensive use of deep-submicron CMOS processes.While approaching the 100 nm span, the CMOS technology hasentered the sub-3 nm gate oxide thickness regime. In such aregime, MOSFET devices exhibit a non-negligible gate-leakagecurrent, due to the finite probability of electrons directly tunnel-ing through the insulatingSiO2 layer [1].

10-10

10-8

10-6

10-4

10-2

100

102

104

0 0.2 0.4 0.6 0.8 1

130 nm technologyGate C

urrent

Densi

ty (A/c

m2 )

Gate-to-Source Voltage (V)

NMOS @ VDS=VBS=0

90 nm technology tox = 16 A

tox = 20 A

Figure 1: gate current density of NMOS devices with various gate di-mensions and belonging to two CMOS technology nodes, with differ-ent oxide thicknessestOX .

As an example, Fig. 1 shows the gate current density for NMOSdevices belonging to two CMOS processes with 90 nm and130 nm feature size; in the 90 nm process the leakage currentis about 2-3 orders of magnitude higher than in the 130 nmprocess. This leakage current, which originates from discretecharges randomly crossing a potential barrier, is affected bynoise fluctuations which may degrade circuit performance inanalog applications.In particular, in solid state detector readout circuits integrated insub-100 nm CMOS technologies, the resolution, which is lim-ited by the noise from the input transistor of the charge sensitiveamplifier, may be degraded by the parallel noise source in thedevice gate current. In order to evaluate the effects of this noisecontribution on the resolution of readout circuits, and to supplysuitable design criteria for IC designers, accurate characteriza-tion and modeling of gate current noise are mandatory.In this work, the noise characterization is carried out by meansof purposely developed instrumentation with the required accu-racy in a frequency range large enough to include both whiteand1/f or Lorentzian-like components, considering the depen-dence of the gate current from device geometry and bias con-ditions. This measuring instrument consists mainly of a tran-simpedance stage amplifying the noise in the DUT (device un-der test) gate-leakage current, which is converted into a voltageand than detected by a commercial spectrum analyzer. The con-straint for the minimum detectable noise is chiefly dictated bythe noise of the amplifier and its feedback resistor: the value ofsuch a component has been chosen as a compromise betweenaccuracy and bandwidth of the measuring system. As a result,the system allows for measurements from 0.1 Hz up to 100 kHz.Such a bandwidth allows us to fully characterize the gate currentnoise, which exhibits white, 1/f and Lorentzian-like behavior inthis frequency range.In order to measure the noise arising from an extended range ofgate current values, two different interface circuits whose res-olution has been optimized for two different intervals of thesevalues have been developed .After presenting the details of the interface circuit design and ofthe setup and procedures for gate noise measurements, resultsrelevant to transistors belonging to a 90 nm and 130 nm CMOStechnologies will be also presented and discussed.

II. GATE-LEAKAGE CURRENT NOISE

In MOS devices with ultrathin gate oxide thickness, di-rect tunneling appears to be the dominant mechanism of gate-leakage current. This current can be divided into three majorcontributions [2]: the gate-to-inverted channel current (Igc), the

436

gate-to-source (Igs) and the gate-to-drain (Igd) components dueto the path through the source and drain overlap regions. Thegate-leakage current noise performances of a CMOS device canbe characterized in terms of the gate noise current spectrum,which can be modeled by means of the equation [3]:

S2

P= S2

W+

Afg

fαfg. (1)

The firs term in (1) describes the white noise component of thespectrum while the second one is given by fliker noise, whereAfg is a power coefficient of the1/f noise whileαfg deter-mines the slope of this low frequency noise contribution. ThetermS2

Win (1) can be expressed by means of the well known

shot noise law [4]:S2

W= 2qIG (2)

whereIG is the sum of the absolute values of each gate currentcontribution for a given bias condition.

III. I NSTRUMENTATION FORNOISE

MEASUREMENTS

In this section two interface circuits used to perform noisemeasurements will be presented. These circuits have been de-signed with different resolution on the basis of the expectednoise level for a given gate current of the DUT.

SpectrumAnalyzer

RFDT

RF

S

DUT

Gate and DrainBias

−

Test Signal

Figure 2: system for the noise measurements.

The driving criterion in the design of the amplification systemswas the minimization of their input-referred noise with respectto the current noise of the DUT,SI,DUT . Noise measurementsare performed by means of the system described in Fig. 2. Thenoise in the gate current of the DUT is converted into a voltageby means of a low noise transimpedance amplifier, and then de-tected by a commercial network/spectrum analyzer. The testsignal source of the analyzer is applied, through the resistorRFDT and the switchS, to the input of the interface circuit, inorder to evaluate the transfer function of the measuring system.The transfer function is obtained by applying a voltage signal,converted into a current signal by means of the resistorRFDT

shunted to the amplifier input virtual ground. The equivalentinput noise current spectrum is calculated by dividing the out-put noise spectral density by the measured transfer function andtaking into account the value of the resistorRFDT . By means

of gate and drain bias circuits it is possible to obtain differentbias conditions and gate current contributions and make one ofthese components dominant with respect to the others.

A. Interface circuit for high DUT gate currents

Noise measurements at high gate current values (from hun-dreds of nanoamps to few microamps) can be performed bymeans of the interface circuit shown in Fig. 3.

RF

CF

RG

CI

CD

V D V G

−

+

DUT

Vout

Figure 3: high-gate-current interface circuit.

The voltagesVD andVG are applied respectively to the drainof the DUT and to the resistorRG, used to regulate the voltageat the gate of the device. By adjustingVD andVG it is possi-ble to obtain the desired device bias conditions. The value offeedback resistorRF and bias resitorRG has been chosen tak-ing into account the value of the static gate current of the DUTand the expected noise level for that current. Actually,RF andRG provide the main noise contribution to the overall systemperformances. The value of the gate current can be obtained bymeasuring the voltage drop across theRG resistor.CI is a de-coupling capacitor, whileCF has been introduced to avoid res-onance peaks in the circuit response andCD includes the inputcapacitance of the amplifier and parasitics from the PCB. Highgain all over the frequency range is also needed to overcome thenoise of the spectrum analyzer. The frequency response of thesystem can be expressed by means of the following equation:

G(jω) =RF

1 + jωRF CF

. (3)

The frequency responseof the interface circuit is shown inFig. 4, for a feedback resistor of2 MΩ.

437

110115120125130135140

100 101 102 103 104 105

Transi

mpeda

nce Ga

in (dB

)

Frequency (Hz)

RF = 2 MΩ

Figure 4: transimpedance gain of the instrument in the high-gate-current topology.

A noise analysis of the measuring system can be carriedout considering the main noise sources, shown in Fig. 5, whereSI,RF andSI,RG are current noise sources relevant to the ther-mal noise of theRF andRG resistors, whileSI,OP andSV,OP

are the equivalent input noise sources of the amplifier.

CF

RF

S I,RF

S V,OP

S I,OPCDS I,RGRG

Vout−

Figure 5: transimpedance stage with the main noise sources.

The noise of the measuring system can then be modeled bymeans of an equivalent input current noise source, whose powerspectral density is given by the following equation:

S2

SY S(ω) = 4kT

(

1

RF //RG

)

+ S2

I,OP(ω) +

+ S2

V,OP(ω)

(

1

RF //RG

)2

·

·

(

1 +

[

ω

(

RF RG

RF + RG

)

(CD + CF )

]2)

,

(4)

wherek is the Boltzmann’s constant andT the absolute tem-perature. Expression (4) can be minimized choosing high valueresistors; the choice for the operational amplifier used in thetransimpedance stage has been dictated by its performances interms of parallel input-noiseSI,OP .

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10-2

10-1

100

101

100 101 102 103 104 105

Noise

Curre

nt Spec

trum (

pA / H

z1/2)

Frequency (Hz)

SI,RF, SI,RG

SI,OP

theoreticalmeasured

SV,OP contribution

Figure 6: input-referred noise contribution of the amplifier, and calcu-lated contributions.

Fig. 6 shows the measured input-referred noise of the inter-face circuit, and the theoretical noise contributions calculated bymeans of (4), for an estimatedCD of 25 pF . Considering thatSI,OP = 1.5 fA/

√Hz, and neglecting the series noise contri-

bution from the operational amplifier, which has an impact onthe resolution only at frequencies higher than 100 kHz, the totalinput noise of the interface system is mainly due to resistorsRF

andRG. Assuming that minimum gate-leakage current noisefor the DUT can be expressed by means of (2), it is possible todetermine the valueIG,min for the gate current which leads to asignal to noise ratio (S2

I,DUT/S2

SY S) equal to unity:

IG,min ≈

4kT(

1

RF+ 1

RG

)

2q. (5)

With the values used forRF and RG, IG,min = 52 nA.

B. Interface circuit for low DUT gate currents

Measurements of noise spectral density arising from smallercurrents, can be carried out by decreasing the noise contribu-tions in the interface circuit. A solution which suitably improvesthe noise performance of the amplifying system is described inFig. 7. The main difference with respect to the schematic ofFig. 3 lies in the absence of the gate-biasing resistorRG, whichleads to a significant noise reduction in the interface amplifier.In particular, the dominant noise source in this configurationis represented only by the feedback resistorRF . Adopting a100 MΩ resistor, it is possible to measure the noise arising froma minimum gate-leakage current in the order of few nanoamps,as highlighted in Fig. 8, where the signal-to-noise ratio is repre-sented as a function of the gate-leakage current. DUT biasing isdone by means of the voltageVG applied to the non-inverting in-put of the transimpedance amplifier and the voltageVD appliedto the drain of the DUT.

438

RF

CF

CD

RA

CA

RB

DUT

+

−

−

Vo’ Vout+

V D

V G

RO

CO

Figure 7: low-gate-current interface circuit.

-20-10

0102030405060

10-1 100 101 102

Signal

-to-No

ise Ra

tio (dB

)

Gate Current (nA)

S/N=0 dB @ IG≈0.6 nA

Figure 8: signal-to-noise ratio for the low gate current interface circuit.

At low gate current, the noise at the output of the tran-simpedance amplifier requires an additional gain stage in orderto overcome the noise of the spectrum analyzer; in particular, a40 dB gain stage has been included in the circuit. ResistorR0

and capacitorC0 perform the high-pass filtering action neededto decouple the two stages of the circuit. Adequate values forthese components were chosen in order to obtain an extremelylow cut-off frequency. Stray capacitorCA in parallel with re-sistorRA introduces an high-frequency pole in the frequencyresponse of the system. The value of the feedback resistorRF

of the transimpedance amplifier has to be chosen as a compro-mise between the noise performance of the measuring systemand the range of the gate current values in the DUT, which islimited by the output dynamic range of the amplifier. Fig. 9shows the good agreement between measured and theoreticalfrequency response, which can be calculated as follows:

G(jω) =RF

1 + jωRF CF

(

1 +RA

RB

)

1 + jω( RARB

RA+RB)CA

1 + jωRACA

.

(6)

160

170

180

190

200

210

101 102 103 104 105

measured FdTtheoretical FdT

Transi

mpeda

nce Ga

in (dB

)

Frequency (Hz)

Figure 9: transimpedance gain of the instrument in the low-gate-currenttopology.

IV. NOISE MEASUREMENTS

The instruments described in Section II were used to mea-sure gate-leakage current noise of devices belonging to a 130 nmand a 90 nm CMOS process by STMicroelectronics. Noise wasmeasured by means of a HP3562A Dynamic Signal Analyzer,also performing network transfer function characterization.

0.1

1

10

100

100 101 102 103 104 105

IG = 0.7 µAIG = 1.7 µAIG = 4.9 µA

Noise

Curre

nt Spec

trum (

pA / H

z1/2)

Frequency (Hz)

NMOS W/L = 600/0.40 @ VDS = VBS = 0 V

Figure 10: gate noise current spectra for an NMOS withW/L=600/0.40, belonging to a 90 nm CMOS technology, biased at dif-ferent gate current values, forVDS = 0 V .

Fig. 10 and Fig. 11 show noise current spectra of NMOS withdifferent dimensions biased in different conditions in terms ofgate-to-source and drain-to-source voltages, for gate current val-ues ranging from 0.8 nA to4.9 µA. Source and bulk of the DUTswas always connected to ground.Noise measurement results have shown that the gate currentnoise spectrum exhibit both white and1/f behavior, thereforethey can be modeled by means of equation (1). The results showa dependence of the1/f term on the gate current: decreasing thegate-leakage current of the DUT results in a lower1/f noisecontribution.

439

1

10

100

1000

100

101

102

103

104

theoretical value

No

ise

Cu

rre

nt

Sp

ectr

um

(fA

/ H

z1

/2)

Frequency (Hz)

NMOS W/L = 1000/1.00 @ IG = 10 nA, V

DS=V

BS=0 V

1

10

100

1000

10-1

100

101

102

103

104

No

ise

Cu

rre

nt

Sp

ectr

um

(fA

/ H

z1

/2)

Frequency (Hz)

NMOS W/L=200/0.7 @ IG=0.8 nA, V

DS=V

BS=0 V

b)

c) d)

130 nm technology

130 nm technology 90 nm technology

90 nm technology

0.01

0.1

1

10

100

101

102

103

104

105

IG = 49 nA

IG = 95 nA

No

ise

Cu

rre

nt

Sp

ectr

um

(p

A /

Hz

1/2)

Frequency (Hz)

NMOS W/L = 600/0.28 @ VGS

= VBS

= 0 V

0.1

1

10

101

102

103

104

105

No

ise

Cu

rre

nt

Sp

ectr

um

(p

A /

Hz

1/2)

Frequency (Hz)

NMOS W/L=1000/0.35 @ IG=3.9 µA, V

DS=V

BS=0 V

a)

Figure 11: gate noise current spectra for devices belonging to 90 nm and 130 nm CMOS technologies, biased at different gate current values.

This low-frequency noise exhibits a quadratic dependence onthe gate current [5]. For devices belonging to the 130 nm pro-cess the1/f noise component of the spectrum is not clearlyvisible at 1 Hz as shown in Fig. 11b), while the white noisecontribution confirm the good accuracy of the model for the the-oretical behavior expressed by (2). In order to detect1/f con-tribution it has been necessary to perform measurements fromlower frequencies, as shown in Fig. 11c), relevant to a gatecurrent smaller than 1 nA. As it can be seen in the presentedspectra, white and1/f noise increase by increasing the gatecurrent; moreover, at a fixed current, white noise seems to bealmost independent of the gate geometry. Some devices exhib-ited Lorentzian-like noise behavior, as shown in Fig. 11d).

V. CONCLUSION

This paper described a laboratory instrument for gate-leakage current noise measurements that is an effective tool forthe characterization of CMOS devices with oxide thickness inthe 2-nm span. In the frequency range used for the presentedresults, it was possible to fully characterize the noise behaviorof the DUTs. Measuring the1/f noise component in extremelylow gate currents (a few nanoamps or less) requires measuringthe DUT noise spectrum from very low frequencies as the flickerterm rapidly decreases with the gate-leakage current. With thisinstrumentation it is possible to carry out a complete charac-

terization of the technologies used in the design of low-noisecharge sensitive amplifiers, where the gate-leakage current canrepresent a limit in the achievable resolution.

REFERENCES

[1] Y. Taur, A.D. Buchanan, W. Chen, D.J. Frank, K.E. Ismail, S. Loet al.,“CMOS scaling into the nanometer regime”,Proceedingsof the IEEE, vol. 85, no. 4, pp. 486-504, Apr. 1997.

[2] N. Yang, W.K. Henson, J.J. Wortman, “A comparative study ofgate direct tunneling and drain leakage currents in n-MOSFET’swith sub-2 nm gate oxides”,IEEE Trans. Electron Devices,vol. 47, no. 8, pp. 1636-1644, Aug. 2000.

[3] J. Lee, G. Bosman, K.R. Green, D. Ladwing, “Noise model ofgate-leakage current in ultrathin oxide MOSFETs”,IEEE Trans.Electron Devices, vol. 50, no. 12, pp. 2499-2506, Dec. 2003.

[4] A.J. Scholten, L.F. Tiemeijer, R. van Langevelde, R.J. Havens,A.T.A. Zegers-van Duijnhoven, V.C. Venezia, “Noise modelingfor RF CMOS circuit simulation”,IEEE Trans. Electron Devices,vol. 50, no. 3, pp. 618-632, 2003.

[5] M. Manghisoni, L. Gaioni, L. Ratti, V. Re, V. Speziali, G.Traversi, “Impact of gate-leakage current noise in sub-100 nmCMOS front-end electronics”,2007 IEEE Nuclear Science Sym-posium Conference Record. feature size range”,2007 IEEE Nu-clear Science Symposium Conference Record.

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