Inside the all-ADI 3 GHz Signal Analyzer - Analog Devices Keysight ADS software for 2.5D simulation Highlighted layout weakness, reduced board iterations 1st Prototype: Suffered Coupling

BOB CLARKE

PROJECT MANAGER

Inside the all-ADI 3 GHz

Signal Analyzer:

1

Some Low to Mid Performance Commercial Spectrum Analyzers

Model Maximum

Frequency

Noise Floor,

preamp off

IIP3 @ 1GHz Price

Keysight N9913A 4 GHz -139 dBm/Hz 15 dBm? $10,795

Keysight N9340B 3 GHz -139 dBm/Hz 10 dBm $8,599

Keysight E4402B 3 GHz -150 dBm/Hz 16 dBm $24,948

R&S FSH3 3 GHz -144 dBm/Hz 13 dBm ??

Anritsu MS2711E 3 GHz -141 dBm/Hz 20 dBm $6,950

Advantest U3741 3 GHz -145 dBm/Hz 10 dBm ? $7,980

HP8591A 1.8 GHz -145 dBm/Hz +5 dBm $2,497 used

ADI 4 GHz Measured!

-155 dBm/Hz

-5 dBm

2nd mixer limitedMuch Less!

(Thanks to Benjamin Sam for compiling commercial data!)

Design and Presentation Partitioning: Three Board Designs

Typical Partitioning in Industry

Separate Boards “Easy” to Design and Debug

Allows Different Synthesizers and ADCs

Takes Advantage of AD6676 Software

3 ©2016 Analog Devices, Inc. All rights reserved.

Receiver Board

Synthesizer Board

(1st LO)

Synthesizer Board

(2nd LO )

AD6676 Evaluation Board

Receiver Board

©2016 Analog Devices, Inc. All rights reserved. 5

Receiver Functional Block Diagram


AD6676

Receiver Prototype Board – Top and Bottom

Two layer FR4 board to verify layout and

functionality

Not worried about frequency response on this pass

Each section individually laid out to simply

debugging

“Only” one set of issues at a time to debug

50 ohm SMAs at Input and Out

Buried 50 ohm transmission lines in final version

Note multiple vias surrounding each stage

Red test points are +5V inputs for each stage

Allowed current limiting and verifying supply current

using bench supply

Differential Signal Path for 1040 and 240 MHz

IFs

Life is simpler when you don’t have to worry where

ground is…

Less Interference and Coupling

Board worked without shielding

RF Probes come In very handy here!


Some of the Details


Microstrip

Hairpin

Filter

Microstrip

Hairpin

Filters set

100 MHz

Passband.

RF Gain

Blocks with

each.

Passive,

Wideband

1st Mixer

Wideband

Mixer Driver

Differential

Output Active

Mixer

Differential Signal Path Minimizes Need For

Shielding. Two Differential BPFs.

Programmabl

e

Gain Block

2nd LO input

and 3rd LO

DIvider

Low Noise Synthesizer:

Phase Combining Four ADF4355s

PLL/VCOs


ADL6005 30 GHz TruPower RMS Responding Detector

ADF4355 ADF4355 ADF4355 ADF4355

ADCLK948

REFIN

1 - 250 MHz

RFOUT

10 - 6000 MHz

PBR006 PBR006

PBR006

Synthesizer Functional Block Diagram

ADCLK948 clock buffer used to provide

reference to 4 x ADF4355 parts.

Phase adjust feature used to align output

waveforms for phase coherency.

High isolation combiners used to give 6 dB

lower phase noise.

Optional resistive attenuation pads at RF

output to improve isolation if necessary.


Combining Four PLLs in Phase Yields 6 dB Phase Noise Improvement

Drive each PLL/VCO with same reference

signal.

Adjust each individual PLL/VCO phase such

that the synthesizer combines the four

PLL/VCO outputs for a 6 dB improvement in

output power and a corresponding 6 dB

improvement in phase noise.

Use Phase Adjust Feature in ADF4355 To

Implement This

Challenges:

REFIN.

Isolation of each PLL.

Combining four outputs

Measurement A borted

R&S FSUP 26 Signal Source A nalyzer LOCKED

Set t ings Residual Noise [T3 w / o spurs] Phase Detector +20 dB

Signal Frequency: 5.995000 GHz Int PHN (1 .0 k .. 30.0 M) -48.0 dBc

Signal Level: -20.24 dBm Res idual PM 0.323 °

C ross C orr Mode Harmonic 1 Res idual FM 2.612 kHz

Internal Ref Tuned Internal P hase Det RMS Jitter 0 .1498 ps

P hase Noise [dBc/Hz] Marker 1 [T1] Marker 2 [T1]

RF A tten 0 dB 100 kHz 1 MHz

Top -80 dBc/Hz -109.14 dBc/Hz -131.96 dBc/Hz

10 kHz 100 kHz 1 MHz 10 MHz1 kHz 30 MHz

-150

-140

-130

-120

-110

-100

-90

LoopBW 1 kHz

1 CLRW R

SMTH 1%

2 CLRW R

3 VIEW

SMTH 1%

A

SPR OFF

TH 0dB

Frequency Offset

1

2

Date: 12.MAY.2015 19:59:36


Challenge: Four PLL/VCOs on Single PCB Without Injection Locking

Shielding reduces far field effects

Provides 40 – 50 dB of isolation

Improved Board Layout


Remedy: Import Layout to Keysight ADS

Cadence Allegro permits export to .adfi which is easily imported

to Keysight ADS software for 2.5D simulation

Highlighted layout weakness, reduced board iterations

1st Prototype: Suffered Coupling Between PLL/VCOs


3D Visualization of Coupling Mechanisms


Long interface lines acting as antennae.

– Solution: Shorten or where possible, remove.

More vias to GND required.

Increase physical distance between synthesizers.

New Layout With Added Isolation


Shortened / Moved digital interface lines.

Increased physical distance between synthesizers. (Used board area).

New symmetrical routing of RF stage.

Additional GND vias.

Equal length lines ensure all synthesizers are at same phase, which helps minimises injection locking.

Calibration circuit placed at output.

Simulation Results


Old Board Simulation New Board Simulation

20 -30 dB improvement in isolation.

Work complete. Board arrived in late January.

Solved injection locking issues!

ADL6005 30 GHz TruPower RMS Responding Detector

Use coupler plus RMS detector to measure power levels.

ADL5501 produces an output that is more accurate at high power levels than at lower

power levels.

– Maximum power level is when four waveforms are in-phase.

• Rotate ADF4355 phase, check power, keep rotating until maximum power has

been achieved.

– Fine tuning phase is more important as maximum power approaches, whereas

lower power levels don’t need much accuracy. Hence use Linear V/V detector in

preference to linear-in-dB Log Amp based detector

– Use software to rotate phase of each PLL/VCO in sucession until combined output

power of all four PLL/VCOs has been maximized.

AD7091R12-BIT,

1MSPS ADC

5V

ADL5501 DETECTORRF INPUTPOWER

VPOSMAXIMUM

OUTPUT = 5VINPUT RANGE:

0V TO 5V

COMM

RFIN VRMS VIN

200Ω

340Ω

5V

SPI

VDD

GND

FLTR

ENBL

Calibration Circuit – Aligned Phases by Tuning For Maximum Output Power


Digitizing The Last IF:

AD6676 IF Receiver Subsystem

BANDPASS ∑Δ ADC WITH BUILT-IN DIGITAL FILTERING


Noise Spectral Density (NSD) vs. Oversampling Ratio Trade-off vs. IF

Bandwidth


AD6676 IF Receiver Subsystem

Enables Programmable Multiband/Multimode Signal Analysis


http://www.analog.com/AD6676

http://www.analog.com/AD6676

Summary of Results


Signal Analyzer Boards Connected Together


Measured Results – Receiver Board

Composite 2nd IF and 3rd IF Filter Response

Design target: 100 MHz BW


Worst-Case Spurious: RF input = -15 dBm, 1st LO = 8.333 MHz, 15 dB/DIV

Spurs are <-90 dBc measured at Receiver Board IF output

Measured Results – Receiver Board

IP3 Measurement Setup IP3 Results (Keysight EXA)

IIP3 = -4 dBm (fix identified); OIP3 = +28 dBm

NF (measured separately) is 16.4 dB


Measured Results – Synthesizer Board

Four PLL/VCOs Aligned in Phase

6 dB Improvement as predicted by Theory


Measurement A borted

R&S FSUP 26 Signal Source A nalyzer LOCKED

Set t ings Residual Noise [T3 w / o spurs] Phase Detector +20 dB

Signal Frequency: 5.995000 GHz Int PHN (1 .0 k .. 30.0 M) -48.0 dBc

Signal Level: -20.24 dBm Res idual PM 0.323 °

C ross C orr Mode Harmonic 1 Res idual FM 2.612 kHz

Internal Ref Tuned Internal P hase Det RMS Jitter 0 .1498 ps

P hase Noise [dBc/Hz] Marker 1 [T1] Marker 2 [T1]

RF A tten 0 dB 100 kHz 1 MHz

Top -80 dBc/Hz -109.14 dBc/Hz -131.96 dBc/Hz

10 kHz 100 kHz 1 MHz 10 MHz1 kHz 30 MHz

-150

-140

-130

-120

-110

-100

-90

LoopBW 1 kHz

1 CLRW R

SMTH 1%

2 CLRW R

3 VIEW

SMTH 1%

A

SPR OFF

TH 0dB

Frequency Offset

1

2

Date: 12.MAY.2015 19:59:36

Thank You!

Danke!

Merci!

QUESTIONS?

BOB CLARKE

[email protected]

AMATEUR RADIO: N1RC


Documents

Inside the all-ADI 3 GHz Signal Analyzer - Analog Devices Keysight ADS software for 2.5D simulation Highlighted layout weakness, reduced board iterations 1st Prototype: Suffered Coupling