INPUT-OUTPUT ORGANIZATION

1Input-Output Organization

Computer Organization Computer Architectures Lab

• Peripheral Devices

• Input-Output Interface

• Asynchronous Data Transfer

• Modes of Transfer

• Priority Interrupt

• Direct Memory Access

• Input-Output Processor

• Serial Communication

INPUT-OUTPUT ORGANIZATION



PERIPHERAL DEVICES

Input Devices

• Keyboard• Optical input devices - Card Reader - Paper Tape Reader - Bar code reader - Digitizer - Optical Mark Reader• Magnetic Input Devices - Magnetic Stripe Reader• Screen Input Devices - Touch Screen - Light Pen - Mouse• Analog Input Devices

Output Devices

• Card Puncher, Paper Tape Puncher• CRT• Printer (Impact, Ink Jet, Laser, Dot Matrix)• Plotter• Analog• Voice

Peripheral Devices



* Provides a method for transferring information between internal storage (such as memory and CPU registers) and external I/O devices

* Resolves the differences between the computer and peripheral devices

- Peripherals - Electromechanical Devices CPU or Memory - Electronic Device

- Data Transfer Rate Peripherals - Usually slower CPU or Memory - Usually faster than peripherals Some kinds of Synchronization mechanism may be needed

- Unit of Information Peripherals - Byte CPU or Memory - Word

- Operating Modes Peripherals - Asynchronous CPU or Memory - Synchronous

INPUT/OUTPUT INTERFACESInput/Output Interfaces



I/O BUS AND INTERFACE MODULES

Each peripheral has an interface module associated with it

Interface- Decodes the device address (device code)- Decodes the commands (operation)- Provides signals for the peripheral controller- Synchronizes the data flow and supervises the transfer rate between peripheral and CPU or Memory

I/O command (Function codes) : Control CommandStatus CommandInput CommandOutput Command

Input/Output Interfaces

Processor

Interface

Keyboardand

displayterminal

Magnetictape

Printer

Interface Interface Interface

DataAddressControl

Magneticdisk

I/O bus

Interface Modules : (VLSI Chip)» PCI» IDE » SATA» RS-232» USB



I/O BUS AND MEMORY BUS

* MEMORY BUS is for information transfers between CPU and the MM

* I/O BUS is for information transfers between CPU and I/O devices through their I/O interface

* Some computers use a common single bus system for both memory and I/O interface units

- Use one common bus but separate control lines for each function - Use one common bus with common control lines for both functions

* Some computer systems use two separate buses, one to communicate with memory and the other with I/O interfaces

Functions of Buses

Physical Organizations




» I/O Bus versus Memory Bus• 1) Use two separate buses, one for memory and the other for I/O :

– I/O Processor is required (IOP)

• 2) Use one common bus for both memory and I/O but have separate control lines for each : Isolated I/O

– IN, OUT : I/O Instruction

– MOV or LD : Memory read/write Instruction

• 3) Use one common bus for memory and I/O with common control lines : Memory Mapped I/O

– MOV or LD : I/O and Memory read/write Instruction

Intel, Zilog

Motorola

* Control LinesI/O Request, Mem Request, Read/Write

* Control LinesRead/Write



ISOLATED vs MEMORY MAPPED I/O

- Separate I/O read/write control lines in addition to memory read/write control lines

- Separate (isolated) memory and I/O address spaces

- Distinct input and output instructions

Isolated I/O

Memory-mapped I/O

- A single set of read/write control lines (no distinction between memory and I/O transfer)

- Memory and I/O addresses share the common address space

-> reduces memory address range available

- No specific input or output instruction

-> The same memory reference instructions can be used for I/O transfers

- Considerable flexibility in handling I/O operations




I/O INTERFACE

- Information in each port can be assigned a meaning depending on the mode of operation of the I/O device -> Port A = Data; Port B = Command; Port C = Status

- CPU initializes(loads) each port by transferring a byte to the Control Register -> Allows CPU to define the mode of operation of each port (In, Out, Command, …) -> Programmable Port: By changing the bits in the control register, it is possible to change the interface characteristics

CS RS1 RS0 Register selected 0 x x None - data bus in high-impedence 1 0 0 Port A register 1 0 1 Port B register 1 1 0 Control register 1 1 1 Status register

Programmable Interface


Chip select

Register select

Register select

I/O read

I/O write

CS

RS1

RS0

RD

WR

Timingand

Control

Busbuffers

Bidirectionaldata bus

Port Aregister

Port Bregister

Controlregister

Statusregister

I/O data

I/O data

Control

Status

Inte

rna

l b

us

CPU I/ODevice

Example of I/O Interface : 4 I/O port : Data port A, Data port B, Control, StatusAddress Decode : CS, RS1, RS0



ASYNCHRONOUS DATA TRANSFER

Synchronous - All devices derive the timing information from common clock lineAsynchronous - No common clock

Asynchronous data transfer between two independent units requires that control signals be transmitted between the communicating units to indicate the time at which data is being transmitted

Strobe pulse - A strobe pulse is supplied by one unit to indicate the other unit when the transfer has to occur

Handshaking - A control signal is accompanied with each data being transmitted to indicate the presence of data - The receiving unit responds with another control signal to acknowledge receipt of the data

Synchronous and Asynchronous Operations

Asynchronous Data Transfer

Two Asynchronous Data Transfer Methods




* The strobe may be activated by either the source or the destination unit

STROBE CONTROL

Sourceunit

Destinationunit

Data bus

Strobe

Data

Strobe

Valid data

Block Diagram

Timing Diagram

Source-Initiated Strobe for Data Transfer

Sourceunit

Destinationunit

Data bus

Strobe

Data

Strobe

Valid data

Block Diagram


Destination-Initiated Strobe for Data Transfer

Timing Diagram



HANDSHAKING

Strobe Methods

Source-Initiated

The source unit that initiates the transfer has no way of knowing whether the destination unit has actually received data

Destination-Initiated

The destination unit that initiates the transfer no way of knowing whether the source has actually placed the data on the bus

To solve this problem, the HANDSHAKE methodintroduces a second control signal to provide a Replyto the unit that initiates the transfer




SOURCE-INITIATED TRANSFER USING HANDSHAKE

* Allows arbitrary delays from one state to the next * Permits each unit to respond at its own data transfer rate * The rate of transfer is determined by the slower unit

Block Diagram

Timing Diagram

Accept data from bus.Enable data accepted

Disable data accepted.Ready to accept data(initial state).

Sequence of EventsPlace data on bus.Enable data valid.

Source unit Destination unit

Disable data valid.Invalidate data on bus.

Sourceunit

Destinationunit

Data bus

Data accepted

Data bus

Data valid

Valid data

Data valid

Data accepted




DESTINATION-INITIATED TRANSFER USING HANDSHAKE

* Handshaking provides a high degree of flexibility and reliability because the successful completion of a data transfer relies on active participation by both units* If one unit is faulty, data transfer will not be completed -> Can be detected by means of a timeout mechanism

Block Diagram

Timing Diagram

Sourceunit

Destinationunit

Data bus

Ready for dataData valid

Sequence of Events

Place data on bus.Enable data valid.

Source unit Destination unit

Ready to accept data.Enable ready for data.

Disable data valid.Invalidate data on bus(initial state).

Accept data from bus.Disable ready for data.

Ready for data

Data valid

Data busValid data




ASYNCHRONOUS SERIAL TRANSFER

- Employs special bits which are inserted at both ends of the character code - Each character consists of three parts; Start bit; Data bits; Stop bits.

A character can be detected by the receiver from the knowledge of 4 rules;- When data are not being sent, the line is kept in the 1-state (idle state)- The initiation of a character transmission is detected by a Start Bit , which is always a 0- The character bits always follow the Start Bit- After the last character , a Stop Bit is detected when the line returns to the 1-state for at least 1 bit time

The receiver knows in advance the transfer rate of the bits and the number of information bits to expect

Four Different Types of Transfer

Asynchronous Serial Transfer

Start bit(1 bit)

StopbitsCharacter bits

1 1 0 0 0 1 0 1

(at least 1 bit)


Computer System Architecture Dept. of Info. Of Computer.Chap. 11 Input-Output OrganizationChap. 11 Input-Output Organization

Modes of Transfer The final target of I/O data is memory of the system Memory data transfer to and from peripherals

1) Programmed I/O 2) Interrupt-initiated I/O 3) Direct Memory Access (DMA) 4) I/O Processor (IOP)

Example of Programmed I/O

Interrupt-initiated I/O 1) Non-vectored : fixed branch address 2) Vectored : interrupt source supplies the branch address (interrupt vector)

Interface

C PUI/ O

device

Data register

Statusregister

F

Data bus

I/ O write

I/ O read

Address bus

Data accepted

Data valid

I/ O bus

F = Flag bit

Read status register

C heck flag bit

Read data register

Transfer data to memory

C ontinuewith

program

F lag

O perationcom ple te ?

= 0

= 1

yes

no


Priority Interrupt Priority Interrupt

Identify the source of the interrupt when several sources will request service simultaneously

Determine which condition is to be serviced first when two or more requests arrive simultaneously

» 1) Software : Polling

» 2) Hardware : Daisy chain, Parallel priority


Polling Identify the highest-priority source by software means

» One common branch address is used for all interrupts

» Program polls the interrupt sources in sequence

» The highest-priority source is tested first Polling priority interrupt

» If there are many interrupt sources, the time required to poll them can exceed the time available to service the I/O device

Daisy-Chaining :

Device 1PI PO

Device 3PI PO

Device 2PI PO To next

Device

C PU

INT

INTAC K

Interrupt request

Interrupt acknowledge

Processor data bus

VAD 1 VAD 3VAD 2

“1” “1” “0”Device 2

Interrupt Request


One stage of the daisy-chain priority arrangement :

No interrupt request

Invalid : interrupt request, but no acknowledge

No interrupt request : Pass to other device (other device requested interrupt )

Interrupt request

S Q

R

Vector address

Delay

Enable

RF

PIPriority in

Interruptrequest

from device

Open-collectorinverter Interrupt request to CPU

Priority outPO

VAD

RFPI PO Enable

INTACK

INT


Parallel Priority Priority Encoder

» Interrupt Enable F/F (IEN) : set or cleared by the program

» Interrupt Status F/F (IST) : set or cleared by the encoder output

Priority Encoder Truth Table Interrupt Cycle

At the end of each instruction cycle, CPU checks IEN and IST

if both IEN and IST equal to “1” CPU goes to an Instruction Cycle

» Sequence of microoperation during Instruction Cycle

0

3

2

1

0

3

2

1

Priority encoder

I0

I2

I3

I1

disk

Keyboard

Reader

Printer

Interruptregister

y

0

0

0

0

0

0

x

ISTIEN

VADto C PU

Enable

Interruptto C PU

INTAC Kfrom C PU

Maskregister

ninstructionext Fetch to

0

1

][

1

Go

IEN

VADPC

INTACK

PCSPM

SPSP

: Decrement stack point

: Push PC into stack

: Enable INTACK

: Transfer VAD to PC

: Disable further interrupts

Branch to ISR


Software Routines

J MP DISK

Main program

J MP KBD

J MP RDR

J MP PDR

Stack

750256

Memory

0

3

2

1

Address

750

Program to servic emagnetic disk

Program to servic eKeyboard

Program to servic ec harac ter reader

Program to servic eline printer

DISK

256

KBD

RDR

PTR

I/ O service programs

KBD Int. Here 749

DISK Int. Here 255


Initial Operation of ISR» 1) Clear lower-level mask register bit » 2) Clear interrupt status bit IST» 3) Save contents of processor registers» 4) Set interrupt enable bit IEN » 5) Proceed with service routine

Final Operation of ISR» 1) Clear interrupt enable bit IEN » 2) Restore contents of processor registers» 3) Clear the bit in the interrupt register belonging to the source that has been

serviced» 4) Set lower-level priority bits in the mask register » 5) Restore return address into PC and set IEN

Direct Memory Access (DMA) DMA

DMA controller takes over the buses to manage the transfer directly between the I/O device and memory

C PU

BR

BG

DBUS

WR

ABUS

RD

Bus request

Bus grant

Address bus

Write

Read

Data bus High- impedance

(disable)when BG is

enabled

DMAC ontroller

BR

BG


DMA Transfer (I/O to Memory) 1) I/O Device sends a DMA request 2) DMAC activates the BR line 3) CPU responds with BG line 4) DMAC sends a DMA acknowledge

to the I/O device 5) I/O device puts a word in the data

bus (for memory write) 6) DMAC write a data to the address

specified by Address register 7) Decrement Word count register 8) if Word count register = 0

EOT interrupt 9) if Word count register 0

DMAC checks the DMA request from

I/O device

I/OPeripheral

device

DMA acknowledge

Addressselect

CPU

Interrupt

Address Data

BG

BR

RD WR

Random accessmemory ) RAM(

Address DataRD WR

Direct memory access ) DAM(

controller

Interrupt

Address DataRD WR

BG

RS

DS

BRDMA request

Read control

Write control

Address bus

Data bus


Transfer Modes 1) Burst transfer : 2) Cycle stealing transfer :

DMA Controller ( Intel 8237 DMAC ) DMA Initialization Process

» 1) Set Address register : memory address for read/write

» 2) Set Word count register : the number of words to transfer

» 3) Set transfer mode : read/write, burst/cycle stealing, I/O to I/O, I/O to Memory, …..

» 4) DMA transfer start » 5) EOT (End of Transfer)

Interrupt

C ontrol logic

C S

Data busbuffers

C ontrol register

Data bus

DMA selec t

Inte

rnal

bus

RS

Interrupt

BG

BR

RD

WR

Register selec t

Read

Write

Bus request

Bus grant

Interrupt

Address register

Word count register

Address busbuffers

Address bus

DMA request

DMA Acknowledgeto I/ O device


Input-Output Processor (IOP) IOP :

Communicate directly with all I/O devices Fetch and execute its own instruction

» IOP instructions are specifically designed to facilitate I/O transfer

» DMA Controller (DMAC) must be set up entirely by the CPU Designed to handle the details of I/O processing

Command Instruction that are read from memory by an IOP

» Distinguish from instructions that are read by the CPU

» Commands are prepared by experienced programmers and are stored in memory

» Command word = IOP program

Memory unit

C entral Processingunit (C PU)

Input- outputprocessor (IOP)

Mem

ory

bus

PD PDPDPD

Peripheral devices

I/ O bus


CPU - IOP Communication : Memory units acts as a message center :

» each processor leaves information for the other

C PU operations IOP operations

Send instruc tionto test IOP path Transfer status word

to memory location

If status OK. , sendstart I/ O instruc tion

to IOPAccess memory for

IOP program

C PU continues withanother program

C onduct I/ O transferusing DMA ; prepare

status report

I/ O transfer completedinterrupt C PU

Request IOP status

Transfer status wordto memory location

C heck status wordfor correc t transfer

C ontinue

Message Center

IOP ProgramCPU Program

Documents

INPUT-OUTPUT ORGANIZATION