Input and OutputInput and Output

CS 215 Lecture #20CS 215 Lecture #20

MotivationMotivation

I/O devices make computers useful to I/O devices make computers useful to humans.humans.

Input devices may be arbitrarily slow and Input devices may be arbitrarily slow and must have a way to tell the computer that must have a way to tell the computer that they are ready to supply data.they are ready to supply data.

Output devices must have a way of Output devices must have a way of refusing more data until they are ready to refusing more data until they are ready to receive more.receive more.

General Categories of I/OGeneral Categories of I/OUser interface devicesUser interface devices. Input devices detect changes . Input devices detect changes and output devices changes the physical world. and output devices changes the physical world.

– Input devices: mouse, keyboardInput devices: mouse, keyboard

– Output devices: terminal display, printerOutput devices: terminal display, printer

Mass storage devicesMass storage devices. These devices hold large . These devices hold large quantities of data. For example, disks and tape drives.quantities of data. For example, disks and tape drives.

Gateways and networksGateways and networks. Computers communicate . Computers communicate with each other and these communication exhibit with each other and these communication exhibit delays relative to computer speed. Networks can be delays relative to computer speed. Networks can be treated as if they were conventional I/O devices.treated as if they were conventional I/O devices.

The KeyboardThe Keyboard

The keyboard detects when keys are pressed The keyboard detects when keys are pressed and sends a designated sequence of and sends a designated sequence of characters to the computer. A table is used to characters to the computer. A table is used to map the keys to characters.map the keys to characters.

Some keys like Some keys like SHIFTSHIFT, , CTRLCTRL, , ALTALT, and , and METAMETA either change the mapping of the keyboard or either change the mapping of the keyboard or modify the effect of other keys.modify the effect of other keys.

The bits are usually sent serially at a rate The bits are usually sent serially at a rate given in bits per second (bit rate). given in bits per second (bit rate).

The keyboard must have a way of indicating to the The keyboard must have a way of indicating to the computer that it has a character to send.computer that it has a character to send.

This is done using extra bits called start bit and stop This is done using extra bits called start bit and stop bit. The start bit signals the beginning of a bit. The start bit signals the beginning of a transmission and the stop bit signals its end.transmission and the stop bit signals its end.

The computer then knows that data is going to follow The computer then knows that data is going to follow after receiving the start bit. The following sequence after receiving the start bit. The following sequence of bits are saved to an input register. Both start and of bits are saved to an input register. Both start and stop bits are stripped off at the receiving end.stop bits are stripped off at the receiving end.

In MAL, we can access the input via In MAL, we can access the input via $v0$v0 or or $2.$2.

The Video DisplayThe Video Display

Each time a printable character is sent to the Each time a printable character is sent to the display it reacts by displaying the character in the display it reacts by displaying the character in the position where the cursor was, and moving the position where the cursor was, and moving the cursor one position to the right.cursor one position to the right.

A terminal consists of a display unit and a A terminal consists of a display unit and a keyboard. Thus it is both an input and an output keyboard. Thus it is both an input and an output device.device.

When When crcr is received, the cursor moves to is received, the cursor moves to beginning of the current line and does not scroll.beginning of the current line and does not scroll.

When When nlnl is received, scrolling is initiated but the is received, scrolling is initiated but the cursor does not move. Combining both moves the cursor does not move. Combining both moves the cursor to the beginning of the next line.cursor to the beginning of the next line.

Hard DiskHard Disk

The disk must first be informed where the The disk must first be informed where the data is to be read or written. The disk’s data is to be read or written. The disk’s read/write arm seeks to the proper cylinder read/write arm seeks to the proper cylinder and rotates to the correct sector.and rotates to the correct sector.

When the read/write arm is in proper position When the read/write arm is in proper position it then informs the computer that it is ready to it then informs the computer that it is ready to receive or transmit.receive or transmit.

At this point it can either transmit data or write At this point it can either transmit data or write data.data.

Hardware: I/O instructionsHardware: I/O instructionsThe hardware implements special instructions The hardware implements special instructions to read from/write to I/O devices.to read from/write to I/O devices.– Perhaps lwio (load word I/O) and swioPerhaps lwio (load word I/O) and swio

The devices have a separate address space The devices have a separate address space from memoryfrom memory– lwio $s0, 16 and lw $s0, 16 access different datalwio $s0, 16 and lw $s0, 16 access different data

lwio $s0, 16 reads the next word from device 16lwio $s0, 16 reads the next word from device 16

lw $s0, 16 reads the word stored in memory location 16.lw $s0, 16 reads the word stored in memory location 16.

MIPS does NOT use special I/O instructionsMIPS does NOT use special I/O instructions

Memory-Mapped I/OMemory-Mapped I/O

The hardware can be designed in such a way The hardware can be designed in such a way that some memory addresses are not really that some memory addresses are not really memory at all but a collection of memory at all but a collection of communication channels to I/O devices.communication channels to I/O devices.

In memory-mapped I/O, load and store from/to In memory-mapped I/O, load and store from/to the communication channels provide a means the communication channels provide a means of performing I/O, i.e., load and store of performing I/O, i.e., load and store instructions with an I/O address are treated as instructions with an I/O address are treated as I/O operations.I/O operations.

lw $2, KeyboardDatalw $2, KeyboardData

sw $5, DisplayDatasw $5, DisplayData communication

channels

MIPS RISC architecture uses memory-mapped MIPS RISC architecture uses memory-mapped I/O. Note that the hardware must support this.I/O. Note that the hardware must support this.

Memory-mapped I/O is one method by which the Memory-mapped I/O is one method by which the processor and I/O devices communicate via a processor and I/O devices communicate via a common bus. In this case, one common bus for common bus. In this case, one common bus for memory and I/O are used with common control memory and I/O are used with common control lines.lines.

The I/O devices unlike memory may unavailable. The I/O devices unlike memory may unavailable. If a device is not If a device is not readyready to accept or transmit data to accept or transmit data then it is said to be not ready or then it is said to be not ready or busybusy..

The processor communicates with I/O using two The processor communicates with I/O using two addresses: one for data exchange and the other addresses: one for data exchange and the other to obtain status of the I/O device.to obtain status of the I/O device.

Memory mapped addresses in Memory mapped addresses in SPIMSPIM

keyboard_control = 0xffff0000keyboard_control = 0xffff0000

display_control = 0xffff0008display_control = 0xffff0008

keyboard_data = 0xffff0004keyboard_data = 0xffff0004

display_data = 0xffff000cdisplay_data = 0xffff000c

1 0

Interrupt enable (1 = enabled)

Device busy/ready (1 = ready)

Control

7 6 5 4 3 2 1 0Data

Memory mapped addresses in Memory mapped addresses in SPIMSPIM

Define the memory mapped constants like Define the memory mapped constants like this:this:.data 0xffff0000.data 0xffff0000

keyboard_control: .space 4keyboard_control: .space 4

keyboard_data: .space 4keyboard_data: .space 4

display_control: .space 4display_control: .space 4

display_data: .space 4display_data: .space 4

Programmed I/OProgrammed I/O

wait: lw $14,keyboardstatusbeqz $14,waitlw $2,keyboardData

wait: lw $14,displaystatusbeqz $14,waitsw $2,displayData

1 = ready0 = busy

most significant bit

In programmed I/O, the CPU stays in a loop untilthe I/O unit indicates that is ready for data transfer orif the CPU has issued a command to the I/O moduleit must wait until the operation is complete.

Direct Memory Access (DMA)Direct Memory Access (DMA)

A controller is a device that has registers and can A controller is a device that has registers and can execute routines on its own given necessary execute routines on its own given necessary parameters. parameters.

A DMA controller is given by the CPU the starting A DMA controller is given by the CPU the starting address into which a block of data will be transferred address into which a block of data will be transferred and the amount of data to be transferred. It also has a and the amount of data to be transferred. It also has a control register and a status register.control register and a status register.

The DMA controller requests memory cycle from the The DMA controller requests memory cycle from the memory controller. During a DMA transfer the CPU memory controller. During a DMA transfer the CPU executes from cache while control of the memory bus executes from cache while control of the memory bus is given to the DMA controlleris given to the DMA controller

.datacount: .word 1024begin_file: .space 1024.textinitialize: lw $15,count #number of characters la $16,begin_file #address where to storewaitloop: lw $14,diskstatus beqz $14, waitloop lb $2,diskdata #read a character sb $2,($16) #store into the array sub $15,1 #decrement counter add $16,1 #adjust array pointer bgtz $15,waitloop

A code a DMA controller might execute

Exception MechanismException MechanismInstead of spin-waiting or doing a regular check Instead of spin-waiting or doing a regular check whether an I/O device is ready, the I/O device whether an I/O device is ready, the I/O device can just inform the CPU that it is ready to receive can just inform the CPU that it is ready to receive or transmit data. The I/O device sends an or transmit data. The I/O device sends an interrupt interrupt signal to the system.signal to the system.

In this mechanism, control is transferred to a In this mechanism, control is transferred to a different program which saves the current state of different program which saves the current state of the interrupted program. The requests are then the interrupted program. The requests are then serviced and control is given back to the serviced and control is given back to the interrupted program. This mechanism is called an interrupted program. This mechanism is called an exceptionexception..

An An interruptinterrupt is one class of exception. is one class of exception.

An interrupt can occur at any time. An interrupt can occur at any time.

Hardware and software are needed to Hardware and software are needed to support interrupt handling. The hardware support interrupt handling. The hardware must choose the appropriate time in which to must choose the appropriate time in which to interrupt the executing program and transfers interrupt the executing program and transfers control to an exception handler.control to an exception handler.

The exception handler must save the current The exception handler must save the current state of the interrupted program. state of the interrupted program.

The exception handler also determines which The exception handler also determines which event has caused the exception and decides event has caused the exception and decides what should be done based on it.what should be done based on it.

Since an exception handler can be invoked Since an exception handler can be invoked anytime, an exception handler can not have anytime, an exception handler can not have parameters nor it can return values.parameters nor it can return values.

It must also save register values being used by It must also save register values being used by the interrupted program and restore them before the interrupted program and restore them before returning control to the interrupted program.returning control to the interrupted program.

Exceptions come in two varietiesExceptions come in two varieties– Interrupts are generated by hardwareInterrupts are generated by hardware

I/O deviceI/O device

ClockClock

Power downPower down

– Traps are generated by code executionTraps are generated by code executionDivision by zeroDivision by zero

Illegal memory addressIllegal memory address

System call System call

Software: Interrupt Driven Software: Interrupt Driven I/OI/O

How interrupt driven I/O worksHow interrupt driven I/O works

.text

.la $a0, Ali $v0, 4syscall...dataA: .asciiz “cat”

User code/data

Output buffer

Kernel data Display

How interrupt driven I/O worksHow interrupt driven I/O works

.text

.la $a0, Ali $v0, 4syscall...dataA: .asciiz “cat”

User code/data

Output buffer

Kernel data Display

c a t

How interrupt driven I/O worksHow interrupt driven I/O works

.text

.la $a0, Ali $v0, 4syscall...dataA: .asciiz “cat”

User code/data

Output buffer

Kernel data

c

Display

c a t

How interrupt driven I/O worksHow interrupt driven I/O works

.text

.la $a0, Ali $v0, 4syscall...dataA: .asciiz “cat”

User code/data

Output buffer

Kernel data

ca

Display

c a t

How interrupt driven I/O worksHow interrupt driven I/O works

.text

.la $a0, Ali $v0, 4syscall...dataA: .asciiz “cat”

User code/data

Output buffer

Kernel data

cat

Display

c a t

Role of the Operating SystemRole of the Operating SystemThe operating system is a program that allocates The operating system is a program that allocates and controls the use of all system resources: the and controls the use of all system resources: the processor, memory, and I/O devices.processor, memory, and I/O devices.

Since there are many processes that can run Since there are many processes that can run concurrently, the operating system uses interrupt concurrently, the operating system uses interrupt to allocate the processor to different processes to allocate the processor to different processes periodically -- allowing processes to share periodically -- allowing processes to share processing time with each other.processing time with each other.

The exception handler plus other codes used to The exception handler plus other codes used to decide what process should be executed next is decide what process should be executed next is called the called the kernelkernel..

In saving the current values of registers in In saving the current values of registers in MIPS RISC architecture, addresses needed MIPS RISC architecture, addresses needed to be formed to store them into memory. to be formed to store them into memory.

The formation of addresses requires the use The formation of addresses requires the use of registers -- thus of registers -- thus $26$26 and and $27$27 are reserved are reserved for the operating system so that when an for the operating system so that when an interrupt is to be serviced there is no need to interrupt is to be serviced there is no need to save the contents of these two registers.save the contents of these two registers.

The other type of exception is aThe other type of exception is a trap trap. A trap . A trap occurs when an event happens as a direct occurs when an event happens as a direct result of executing a program, e.g. caused by result of executing a program, e.g. caused by an overflow or an attempt to access a an overflow or an attempt to access a memory outside of the legal range.memory outside of the legal range.