Industry Trends in 3D and Advanced Packaging– Gartner Forecast Analysis Semiconductor Outsourcing Services, Worldwide, 2010-2015, 3Q11 Update 26-Sep-11.pdf – Linley Communications

IBM Custom Logic

© 2011 IBM Corporation

Industry Trends in 3D and Advanced Packaging

© 2011 IBM Corporation IBM Custom Logic 2

Outline

– Industry System and Component Challenges & Trends

– 3D and Advanced Packaging Value-proposition and Client Examples

– 3D Technology Details

– 3DIC / 3DTSV Markets


The Future of Data Rates

Source: IEEE BWA Report ‘12

1 Gigabit Ethernet

10 Gigabit Ethernet

100 Gigabit Ethernet

1 Terabit Ethernet


Year of Announcement

1950 1960 1970 1980 1990 2000 2012

Module

Heat

Flu

x (

watts/c

m2)

0

2

4

6

8

10

12

14

Bipolar CMOS

Vacuum tube

Integrated Circuit

Junction Transistor

Water Cooling

IBM 360

?

CPU 1

CPU 2

L2 Cache

“Lower-Power” Multi-core

Multi-Core SoC / eDRAM

Innovation Required

3D, FinFET’s, Optics…

As “GHz” (classical scaling) went up in

power, new innovation drives performance


Traditional Migration: Drive To Better Performance

Semiconductor Migration

• Wafer Fabs expensive $7 – $10 Billion

• New process nodes every 2 years

• Short life for leading edge

• PCB limiting system performance

Source: Semico Research, Dec. ‘11


As clock frequency flat lines, multi-core extends performance

1990 1995 2000 2005 2010

Clo

ck S

peed

(A

rb.)

10 2

10

10 3

1

10

100

1000

1994 1996 1998 2000 2002 2004 2006 2008

Historical Growth Trend=45% per year

• Single thread performance growth

slows significantly

•

>4 Core

4 Core

1 Core

2 Core

Single -

Pe

rfo

rma

nc

e (

Arb

.)

1

10

100

1000

1994 1996 1998 2000 2002 2004 2006 2008

Historical Growth

Trend

>4 Core

4 Core

1 Core

2 Core

>4 Core >4 Core

4 Core 4 Core

1 Core 1 Core

2 Core 2 Core

But… multi-cores become starved for data at some point in time (I/O limited)

3D Motivation – Four Drivers

Multi-core Solution to Achieve Performance


A New Way to Achieve Performance

200mm 300mm

Mixed technology 3D Packaging

• 3D packaging up to 10X system performance

• Will extend process node and wafer size life

• Be a catalyst for new applications

• Allow for smaller form factor

• Need to improve price points



System and Component Challenges and Trends

Traffic Mgmt IBM ASIC (w/ eDRAM, HSS)

Switch-Router/Transport/MI

NPU/Packet Engine IBM ASICs (w/ eDRAM, eTCAM, HSS)

Control Processor/SoC IBM ASICs (ARM or PPC SoCs) w/ partner IP

NPU

Traffic Mgmt

CP

Port PHY

Switch

I/F

MAC

DRAM

TCAM

QDR

DRAM

• Inflection points – Exponential growth – Exponential increase in data rate

• Throughput scaling, Port density, Computing/Watt

– Exponential increase in power density – Demand for QoS - B/W guarantee & low-

latency – Real-estate premium - rack & floor space

• Telecom CO, Enterprise data center

• Solution trends - Integration – Functional Integration

• Monolithic – Multi-use, DE amortization – Digital CMOS – Mixed-signal SoCs

• Non-monolithic -- More than Moore – SIP, 3D stack, MCM – Memory & PHY integration (40Gbps & 100Gbps)

– Architectural Integration • SoCs w/ eDRAM -- Multi-core, multi-thread • Control & Data plane convergence; virtualization • Clock gating, Voltage island

++Perf

--Pwr


Outline





STG

© 2003 IBM Corporation 10 13-Apr-12

Advanced Packaging Market Trends

Heterogeneous integration of multiple technologies.

The slowing of Moore’s Law forces the market to higher integration which leads to larger die.

Networking and mobile architects are moving to 3D stacking, 2.5D and multi-chip module

(MCM).

Organic MCM

Silicon Interposer

3D TSV


What does 3D integration buy for you?

– Performance

– Reduced interconnect length

– z direction latencies are smaller

– Improved transmission speed (reduced parasitic)

– Power

– Drive smaller interconnect loads

– Reduced power consumption

– Form Factor

– Reduced footprint, volume and weight

– Improved integration density

– TSV interconnect overcomes the space limitations of POP & SiP packages.

– Heterogeneous Integration – Enable More than Moore

– Integration of different technologies

– Integrate different functional layers (RF, memory, logic, MEMS, imagers, etc.) based on different optimized process nodes

STG

© 2003 IBM Corporation 12 13-Apr-12

Range of Advanced Packaging Solutions

Several approaches to meet “More Than Moore” performance requirements.

Key attributes:

1. High bandwidth

2. Low power I/O

3. Low latency

Lid

Sensor

Logic TSV die

Thin core laminate

3D Module

Sensor

Laminate

Package Logic

Organic MCM

Logic

Sensor Sensor

Silicon Interposer

Relative Aggregate Bandwidth on Module

~5Tbps ~10Tbps ~100Tbps


3D early manufacturing is happening now

In 4Q10 IBM announced a custom silicon interposer development project with Semtech. In 4Q11 IBM announced manufacturing of a custom 32nm 3DIC logic die for Micron’s Hybrid Memory Cube (HMC). Xilinx shipping high end FPGA silicon interposer product today.

Advanced Packaging Product Announcements


Customer Example: ADC/DSP Platform

http://www.i-micronews.com/news/IBM-Semtech-team-3D-TSV-interposers,5969.html

– High-performance ADC/DSP platform

– The platform will use IBM’s 3-D interposer technology to interconnect ADC functions in IBM custom logic SOI-based Cu-45HP technology with interleaver ICs in IBM’s 8HP BiCMOS SiGe technology.

– These two different technologies are connected through a single wiring layer on an interposer, which supports a bandwidth of greater than 1.3Tbps in this design.

– IBM’s 3-D technology combines 90-nm BEOL (back-end-of-line) wiring levels for high speed signaling between die as well as providing ultra high capacitance density by integrating deep-trench (DT) capacitors at the top surface of the interposer.

– Applications

– Fiber optic telecommunications

– High performance RF sampling and filtering

– Test equipment instrumentation

– Sub-array processing for phased array radar systems.

– 100Gb Optical transport component

– Challenge of PCB parasitic at high data rate

– Issue of signal integrity & noise

– Form-factor constraints


Customer Example: Micron HMC Gen2

Memory Control

Vault Control

DRAM Sequenc

er

Crossbar Switch

Write

Buffer

Read Buffe

r

Refresh Controll

er Request

Write

D

ata

Read D

ata

DRAM Repair

TSV Repair

MPU

ECC ECC

I/F

Host Links

Link Interface Controller

PHY

Link Interface Controller

PHY

Rx Tx

Rx Tx

– HMC is a new class of memory -- Serial Memory

– 10x better throughput than DDRx memories

– 30% pin reduction compared to DDRx memories

– Higher capacity, smaller footprint


Example: Organic MCM with a eDRAM and Logic Die

– Logic - 17.55mm x 17.55mm

– eDRAM – 11.02mm x 16.96mm

– Package 2892pin FCPBGA

– 57.5 mm body size, 1.0mm

– 120W

– Aggregate Bandwidth

– Die to Die >4Tbps

– Off Module >1Tbps

11.02 5.0 17.55 6.71 6.71 3.0 3.0

15

3.0

3.0

1.0

1 4 4 1 5 G S e r d e s

64 lanes 30G Serdes

1 4 4 1 5 G S e r d e s

55mm x55mm FCPBGA Off Module IO

64 lanes 25G Serdes 144 lanes 15G pico Serdes

1.0

17.55 X 17.55

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Possibilities for Advanced Organic MCMs

Mix and match die to create integrated product.

Requires a multiple partner ecosystem around an industry standard I/O and package.

Values:

1. Greater performance due to serial I/O running at high frequency, >10Gbps

2. Lower power communication with use of ultra short reach I/O

3. Flexibility to create products with heterogeneous die

Logic HMC

FPGA Sensor

System on an organic package


Outline






3D Technology Options at IBM

Shorted TSVs

200mm wafers

SiGe and RF technologies on wafer

TSVs short together through the silicon wafer

Insulated TSVs

300mm wafers

Silicon interposer without active devices

32nm, 22nm or 14nm CMOS on wafer

TSVs insulated from bulk silicon and each other


Shorted Tungsten TSV Array*

Optical Image Top View

X-Section View

Angled X-Section View

* Polysilicon can be

substituted for W


Insulated Cu TSV Structures

MODULE LID

TOP CHIP

ORGANIC LAMINATE

THINNED BOTTOM CHIP

C4

TOP CHIP

IEDM 2011, Farooq et al.


TSV Allows Top and Bottom Electrical Connection

BEOL

TSV

Devices

Top down view

X-section view


Detailed TSV Integration

TSV Bottom

Active chips with 13 levels of metal

TSVs connect to last few levels of metal

TSV

Capture level

E1 Via

Cu 11 level

Cu 12 level

Cu 13 level

IEDM 2011, Farooq et al.


Outline






Interposer & 3D TSV IC Application Roadmap

2012 2014 2016


Server Memory

Infrastructure

Routers

Base stations

Central Office Switch

High-end

Computing

GPU

Tablet PC Notebooks

SmartPhones


Hype Cycle for Semiconductors

Source: Gartner (July 2011)


TSV Market Forecast


Mobile Computing – Handsets, Smart phones, Tablets, etc.

Digital Baseband

Processor (s)

Transceiver/ABB

Memory

Po

wer

Ma

na

gem

en

t

Applications

Processor (s)

TV

Tuner

WLAN/

WiMax BT2.0 GPS

Power

Cntrl. SPXT Switch

PA

PA

PA

PA

3G iPhone

Source: Openmoko, Aug.’08


Wide IO DRAM (JEDEC JC42.6)

– WideIO DRAM die is stacked on top of the mobile processor in the same package to reduce

interconnect capacitance

– Face-to-Back stacking with Through Silicon Vias (TSVs) in the mobile SoC flip-chip die

Source: ST-Ericsson


3D and Advanced Packaging Availability from IBM

Silicon Interposer

32nm High-K CMOS

11 level metal

Deep trench capacitor

Cu Through Silicon Via (TSV)

TS

V

J. Golz, et al., 2011 Symposia on

VLSI Technology and Circuits

IBM plans to use this technology internally as well making it externally availability.

•In production with organic multi-chip modules •Successfully built stacked 32nm eDRAM module (2011 VLSI Technology Paper, Golz) •TSV technology passed extensive reliability testing (IEDM 2011, Farooq) •Integrated 3D design rules into 32nm design system •Client 3D and silicon interposer designs in progress and prototypes for products in build


References

– Gartner Market Definitions and Methodology Semiconductor Devices & Applications 18-Jan-11.pdf

– Gartner Hype Cycle for Semiconductors and Electronics Technologies, 2011 25-July-11.pdf

– Gartner Forecast Memory, Worldwide, 2005-2015, 3Q11 Update 19-Sep-11.xls

– Gartner Market Share Semiconductor Memory, Worldwide, 2010 7-Apr-11.xls

– Gartner Forecast Semiconductor Consumption by Electronic Equipment Type, Worldwide, 4Q11 Update.xls

– Gartner Forecast Analysis Semiconductor Outsourcing Services, Worldwide, 2010-2015, 3Q11 Update 26-Sep-11.pdf

– Linley Communications Semiconductor Market Forecast 2009-2014 Aug 2010.xls

– Linley Communications Semiconductor Market Share, 2010 June '11.xls

– iSuppli Wireless Communications Q4 2011 Topical Report - AFT-CD Database.xls

– iSuppli Smart Phones & Converged Devices Q4 2011 Market Tracker Database.xls

– 3D Copper TSV Integration, Testing and Reliability, M. G. Farooq et al., International Electron Devices Meeting, Dec.

2011.

– 3D Stackable 32nm High-K/Metal Gate SOI Embedded DRAM Prototype J. Golz, et al., 2011 Symposia on VLSI

Technology and Circuits.

Documents

Industry Trends in 3D and Advanced Packaging– Gartner Forecast Analysis Semiconductor Outsourcing Services, Worldwide, 2010-2015, 3Q11 Update 26-Sep-11.pdf – Linley Communications