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http://wps.prenhall.com/chet_floyd_digitalfun_
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EMT 235 DIGITAL PRINCIPLES II
Chapter 1:
Digital Design Concepts
Part 2
Week 2
Digital Hardware
Standard Chips
Programmable Logic Devices
Custom Designed Chips
Integrated Circuits
Plasticcase
Pins
Chip
Cutaway view of DIP (Dual-In-line Pins) chip:
• TTL chips (7400
series)
• CMOS chips
(4000 series)
SN 74 ALS 00 N
SN : Manufacturer (Texas Instruments)
74: 74-series
ALS: Logic Family (Advanced Low Power)
00: Logic Function (Quad 2-input NAND)
N: Package (Plastic DIP)
Logic circuits may be implemented …
on single chip, or
using many chips interconnected on a printed circuit board
(PCB)
Main types of IC chips are:
Standard chips
Programmable Logic Devices (PLD)
Custom chips
Digital Hardware
(Basic IC Chip Types)
Standard Chips
Small number of transistors (< 100)
Simple and fixed functions
Logic designer must decide how to interconnect
multiple chips for desired function
Agreed upon / standard functionality
Popular in the 1980s – too large in physical size for
much industry use now (good for teaching though!)
7400 Series TTL Logic Chips
– The 7400 NAND Chip: pin layout
Vcc = +5V
Gnd e (to pin 11)
no connection
c (to pin 14)
g (to pin 13)
b (to pin 16)
d (to pin 9)
+5 V (anode)
+5 V (anode)
decimal point
(pin 8)
7400
1
2
3
4
5
6
7
14
13
12
11
10
9
8
001
4
9
12
2
5
10
13
3
6
8
11
The equivalent logic layout
7400 Series Implementation
– Implementing f = x1x2 + x2'x3 using 7400 series ICs
V DD
x 1
x 2
x 3
f
7404
7408 7432
Why TTL is Only Used For Small
Systems
Programmable Logic
?
Programmable Logic Devices (PLDs) are ICs with a
large number of gates and flip flops that can be
configured with basic software to perform a specific
logic function or perform the logic for a complex
circuit. Major types of PLDs are:
Programmable logic.
Programmable Logic Devices
Field Programmable
Gate Arrays
Simple PLDs Complex PLDs
PROM, Programmable ROMs
Programmable Logic
Advantages to PLDs include
Reduced complexity of circuit boards
• Lower power requirements
• Less board space
• Simpler testing procedures
Higher reliability
Design flexibility
PLDs
Programmable chips – functionality determined by the
designer
Can even be reprogrammed
Can handle more complex functions than standard
chips (approx 100 million transistors per PLD)
FPGA: Field Programmable Gate Arrays
CPLD: Complex Programmable Logic Devices
PAL: Programmable Array Logic
PLA: Programmable Logic Arrays
These are used very extensively in industry
What is inside the PLD that
makes it programmable?
Minute Fuse Links
MOS Transistors
A single line can represent multiple gate inputs.
The logic shown is for the XOR gate.
X
X
X
X
2
2
Input buffer A A B B
Single line with slash
indicating multiple AND
gate inputs
Fuse blown
Fuse intact
AB
AB
AB + AB
Basic PLD design flow Design Entry
• Schematic
• Source Codes (HDL,
hardware description
language)
Functional Simulation
- verify that the circuit
functions as expected
Timing Simulation
-Considers propagation
delay of the circuit
Program the PLD chip
Synthesis
-Converts schematic or
HDL codes into logic
gates
circuit
Programmable Logic Software
In schematic entry, the design is drawn on a computer screen by
placing components and connecting then with simulated wires. You do
not need to know the details of an HDL. After drawing the schematic, it
can be reduced to a single block symbol:
Design entry
Schematic
HDL
Functional Simulation
After entering the circuit into (either using schematic
or HDL), the circuit is tested in a functional simulation.
Waveforms are used to verify the operation of the circuit.
The waveforms for a counter:
Functionalsimulation
Synthesis
After the simulation, the computer program optimizes
the logic by eliminating redundant terms and
generating a netlist, (a connection list) that is a
complete description of the circuit.
Synthesis
Z
A1
A0
A2
A3
net1net2
net3
net4
and1net5
net6
net7
net9
and2net10
net8
net11inv1
net14 and3net15
net13
net12
net16inv2
net17and4
net20
net19
net18
net21
inv3
net23
net25
net24
and5inv4 net22
I1
I2
I3
I4
or1net26
O1
Netlist (Logic3)
net<name>: instance<name>, <from>; <to>;
instances: and1, and2, and3, and4, and5, or1, inv2,
inv3, inv4;
Input/outputs: I1, I2, I3, I4, O1;
net1: and1, inport1; I1;
net2: and1, inport2; I2;
net3: and1, inport3; I3;
net4: and1, inport4; I4;
net5: and1, outport1; or1, inport1;
net6: and2, inport1; I1;
net7: and2, inport2; I3;
net8: and2, inport3; inv2,outport1
net9: and2, inport4; inv4,outport1
net10: and2, outport1; or1,inport2;
net11: and3, inport1; inv2,outport1
net12: and3, inport2; inv3,outport1
net13: and3, inport3; I4;
net14: and3, inport4; I1;
5: and3 Netlist
Implementation
The computer next “maps” the design from the netlist
to fit it to a target device. Data for all potential target
devices are in a software library. The computer must
account for the I/O pins and fit the logic to the target
device.
Implementation
Timing Simulation
After implementation, a timing simulation is done that
takes into account the specific delays in the target
device and verifies that there are no problems with the
timing.
Timingsimulation
Waveform Editor
Name:
A0
4 sm
A1
A2
A3
Z
1 sm 8 sm 12 sm 16 sm
0
0
0
0
X
Glitch
If a problem is revealed, it is
not too late to correct it
before downloading the file.
Device Programming
The final step is to send the programming file from
the computer to the target device and test the
implementation.
Deviceprogramming(downloading)
Testing
Interface board PLDT-2 board
Traffic Lights
Controller System
Programmable Logic Disadvantage
?
Programmable chips have two major
drawbacks:
1. Consume space due to large number of switches
for programmability
2. Slow speed also limited by excessive
switches (resistance/capacitance)
Custom Chips
Custom chips
Logic designer builds a custom chip
Manufactured by a special fabrication facility ($$$!)
ASIC: Application Specific Integrated Circuit
Fast, small
Expensive! And takes time to build and manufacture
Hierarchical Design
To control the complexity of the function mapping inputs to outputs:
Decompose the function into smaller pieces called blocks
Decompose each block’s function into smaller blocks, repeating as
necessary until all blocks are small enough
Any block not decomposed is called a primitive block
The collection of all blocks including the decomposed ones is a
hierarchy
Example: 9-input parity tree (see next slide)
Top Level: 9 inputs, one output
2nd Level: Four 3-bit odd parity trees in two levels
3rd Level: Two 2-bit exclusive-OR functions
Primitives: Four 2-input NAND gates
Design requires 4 X 2 X 4 = 32 2-input NAND gates
Hierarchy for Parity Tree Example
NANDs
B O
X 0 X 1 X 2 X 3 X 4 X 5 X 6 X 7 X 8
Z O
9-Input
odd
function
(a) Symbol for circuit
3-Input
odd
function
A 0
A 1
A 2
B O
3-Input
odd
function
A 0
A 1
A 2
B O
3-Input
odd
function
A 0
A 1
A 2
B O
3-Input
odd
function
A 0
A 1
A 2
X 0
X 1
X 2
X 3
X 4
X 5
X 6
X 7
X 8
Z O
(b) Circuit as interconnected 3-input odd
function blocks
B O
A 0
A 1
A 2
(c) 3-input odd function circuit as
interconnected exclusive-OR
blocks
(d) Exclusive-OR block as interconnected
Reusable Functions and CAD
Whenever possible, we try to decompose a complex design into common, reusable function blocks
These blocks are
verified and well-documented
placed in libraries for future use
Representative Computer-Aided Design Tools:
Schematic Capture
Logic Simulators
Timing Verifiers
Hardware Description Languages
Verilog and VHDL
Logic Synthesizers
Integrated Circuit Layout
Top-Down versus Bottom-Up
A top-down design proceeds from an abstract, high-level
specification to a more and more detailed design by
decomposition and successive refinement
A bottom-up design starts with detailed primitive blocks and
combines them into larger and more complex functional
blocks
Designs usually proceed from both directions simultaneously
Top-down design answers: What are we building?
Bottom-up design answers: How do we build it?
Top-down controls complexity while bottom-up focuses on
the details
IC Levels of Integration
Integrated circuit (informally, a “chip”) is a
semiconductor crystal (most often silicon) containing
the electronic components for the digital gates and
storage elements which are interconnected on the
chip.
Terminology - Levels of chip integration
SSI (small-scale integrated) - fewer than 10 gates
MSI (medium-scale integrated) - 10 to 100 gates
LSI (large-scale integrated) - 100 to thousands of gates
VLSI (very large-scale integrated) - thousands to 100s of
millions of gates
Digital Logic Families Refers to the the basic component of the circuit and the
circuit technology used.
RTL: Resistor-Transistor Logic
DTL: Diode-Transistor Logic
TTL: Transistor-Transistor Logic
ECL: Emitter-Coupled Logic
MOS: Metal-oxide Semiconductor
CMOS: Complementary Metal-oxide Semiconductor
BiCMOS: Bipolar Complementary Metal-oxide Semiconductor
GaAs: Gallium-Arsenide
SiGe: Silicon-Germanium
RTL & DTL – now obsolete
TTL – widely used
ECL – high speed
CMOS – low power consumption
GaAS & SiGe - very high speed circuit
Technology Parameters
Specific gate implementation technologies are characterized by the following parameters:
Fan-in – the number of inputs available on a gate
Fan-out – the number of standard loads driven by a gate output
Noise Margin – the maximum external noise voltage superimposed on a normal input value that will not cause an undesirable change in the circuit output (a measure of the capability of a circuit to operate reliably in the presence of induced noise)
Cost for a gate - a measure of the contribution by the gate to the cost of the integrated circuit
Propagation Delay – The time required for a change in the value of a signal to propagate from an input to an output
Power Dissipation – the amount of power drawn from the power supply and consumed by the gate
Propagation Delay
Propagation delay is the time for a change on an input of a gate
to propagate to the output.
Delay is usually measured at the 50% point with respect to the H
and L output voltage levels.
High-to-low (tPHL) and low-to-high (tPLH) output signal changes
may have different propagation delays.
High-to-low (HL) and low-to-high (LH) transitions are defined with
respect to the output, not the input.
An HL input transition causes:
an LH output transition if the gate inverts and
an HL output transition if the gate does not invert.
Determines the
speed of the
circuit!!
Propagation Delay (continued)
tPD= max (tPHL, tPLH) Propagation delays
measured at the midpoint
between the L and H values
Definition 1
Definition 2 tPD= average (tPHL, tPLH)
Propagation Delay Example
• Find tPHL, tPLH and tpd for the signals given
IN (
vo
lts)
O
UT
(v
olt
s)
t (ns) 1.0 ns per division
Fan-out
Fan-out can be defined in terms of a standard
load
Example: 1 standard load equals the load
contributed by the input of 1 inverter.
Transition time -the time required for the gate
output to change from H to L, tHL, or from L to H,
tLH
The maximum fan-out that can be driven by a
gate is the number of standard loads the gate can
drive without exceeding its specified maximum
transition time
Fan-out and Delay
The fan-out loading a gate’s output affects
the gate’s propagation delay
Example:
One realistic equation for tpd for a NAND gate
with 4 inputs is:
tpd = 0.07 + 0.021 SL ns
SL is the number of standard loads the gate is
driving, i. e., its fan-out in standard loads
For SL = 4.5, tpd = 0.165 ns
Cost
In an integrated circuit:
The cost of a gate is proportional to the chip area occupied
by the gate
The gate area is roughly proportional to the number and
size of the transistors and the amount of wiring connecting
them
Ignoring the wiring area, the gate area is roughly
proportional to the gate input count
So gate input count is a rough measure of gate cost
If the actual chip layout area occupied by the gate is
known, it is a far more accurate measure
Positive and Negative Logic
The same physical gate has different logical meanings depending on interpretation of the signal levels.
Positive Logic HIGH (more positive) signal levels represent Logic 1
LOW (less positive) signal levels represent Logic 0
Negative Logic LOW (more negative) signal levels represent Logic 1
HIGH (less negative) signal levels represent Logic 0
A gate that implements a Positive Logic AND function will implement a Negative Logic OR function, and vice-versa.
Positive and Negative Logic (continued)
Given this signal level table:
What logic function is
implemented?
Positive
Logic
(H = 1)
(L = 0)
Negative
Logic
(H = 0)
(L = 1)
0 0 0 1 1 1
0 1 1 1 0 0
1 0 1 0 1 0
1 1 1 0 0 0
Input
X Y
Output
L L L
L H H
H L H
H H H
Logic Symbol Conventions
Use of polarity indicator to represent use of negative
logic convention on gate inputs or outputs
X
CKT X
Y Z
Logic Circuit
X
L
L
H
H
Y
L H
L
H
Z
L
H
H
H
Y Z
Positive Logic Negative Logic
X
Y Z
Questions ??