488 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 36, NO. 3. MARCH 1989

Increased Junction Breakdown Voltages in Silicon-on-Insulator Diodes

Abstract-A junction breakdown model and the results of PISCES I1 simulations are presented for silicon-on-insulator (SOI) devices. This model shows the dependence of breakdown voltage in a fully depleted (FD) SO1 diode on the backgate bias, the properties of the buried oxide layer, and the device parameters. Breakdown in a thin FD SO1 diode is quite different from that observed in a thicker, partially depleted (PD) diode. The analysis is supported by breakdown voltage measure- ments of Separation by Implantation of Oxygen (SIMOX) based SO1 diodes and the results suggest that body breakdown is dominant in FD SO1 diodes, and the junction curvature effect is dominant in PD SO1 diodes. Furthermore, the results also show that breakdown voltage in the FD SO1 diode is higher than their bulk-silicon counterpart and can be further increased by applying the appropriate backgate bias.

I. INTRODUCTION T is well known that the junction curvature effect dom- I inates breakdown in planar-diffused diodes. Since the

cylindrical and/or spherical regions of the junction have a higher field intensity, the avalanche-breakdown voltage is determined by these regions [ 11. A device requiring a high-breakdown voltage faces the problem of excessive surface electric field in the vicinity of the junction. There- fore, it is desirable to design semiconductor devices with the electric field at the junction surface significantly less than that in the body of the device, so that body break- down instead of surface breakdown will occur. Moreover, reduction of the field at the junction surface will improve the stability of the device by reducing the probability of migration of ionized-surface impurities. Various contours and design principles have evolved in an effort to reduce surface electric fields, such as the guard ring and beveled

The device fabricated on silicon-on-insulator (SOI) substrate is different from the conventional bulk device because the body is thin and floating and the underlying (back) oxide is thin enough to be an effective backgate. In this paper, we present a junction breakdown model and PISCES I1 simulations which describe avalanche-break-

edge [I], P I .

Manuscript received July 5, 1988; revised October 27, 1988. This work was supported by the Harris Semiconductor Corporation and the Florida High Technology and Industry Council.

H. S. Chen, S . S . Li, and R. M. Fox are with the Integrated Electronics Center, University of Florida, Gainesville, FL 3261 1 ,

W. A . Krull is with the Harris Semiconductor Corporation, Melbourne, FL 32901.

IEEE Log Number 8825694. 'In this work, diodes fabricated by the planar process are referred to a5

planar diodes, while diodes characterized by a geometrically flat junction are called plane diodes.

down characteristics in thin-film SO1 devices. The anal- ysis yields a description of breakdown voltage in terms of the backgate bias, the properties of top-silicon/buried- oxide interface, and the device parameters. Results of breakdown voltage measurements of Separation by Im- plantation of Oxygen (SIMOX) diodes are discussed and shown to support the analysis. These measurements re- veal, in accord with the analysis, that junction-curvature effect is greatly reduced in a fully depleted (FD) SO1 diode which results in increased breakdown voltage. However, if the device were not properly designed, breakdown volt- age would be even lower than their bulk silicon counter- part. The results therefore indicate how the device param- eters must be designed to ensure acceptable breakdown voltage. Furthermore, they suggest how the backgate bias may provide a control by which breakdown voltage can be increased. It should be noted that although the analysis is based on junction diodes, it can be applied to the drain- body junctions of SO1 MOSFET's. Also, SO1 substrate tends to be an excellent candidate for high-voltage circuit applications since it needs no additional contour tech- nique to reduce the surface electric field.

11. DEVICE FABRICATION A N D EXPERIMENTAL SETUP SIMOX wafers implanted by Eaton were used in this

study. The starting si!icon substrate had a resistivity of 3-5 0 cm. The buried-oxide structure was produced by implanting 0' ions using the prototype Eaton NV-200 oxygen implanter. The final buried-oxide thickness was about 0.35 pm. The wafer temperature was maintained at 500°C during the oxygen implant. The implant energy was 150 KeV and the oxygen dose was varied from 1.8 to 2.2 X 10" cmP2. High-temperature annealing ( 1250"C, 2-16 h ) was applied to the wafer following ox- ygen implantation. n-type silicon epilayers of thicknesses ranging from 0.7 to 2.5 pm and a dopant density of 3 x lOI5 cm-3 were grown on the SIMOX wafers. The p+-n abrupt-junction diodes were formed in the epilayer with a junction depth of 0.4 + 0.1 pm and junction area of 450 X 450 pm2.

Fig. 1 shows the schematic cross section of a p+-n sil- icon-on-insulator (SOI) diode and the experimental setup used in the breakdown-voltage measurement. A constant current source was connected across the diode to force reverse current through the junction and a dc power sup- ply was connected to the substrate so that the dependence

0018-9383/89/0300-0488$01 .OO O 1989 IEEE

CHEN ci < I / . . I N C R t A S E D JUNCTION B R E A K D O W N V O L T A G t S 489

( ‘OR\FR I l l

\ GI> ih7 Fig. 1 . Schematic cross section of a SO1 diode and the experimental setup

for breakdown-voltage measurement. A coiistant current sourcc and a digital voltmeter ( D V M ) are connected across the junction. A dc power supply is connected to the backgate.

of breakdown voltage on the backgate bias could be de- termined.

111. THE BREAKDOWN MODEL A lateral SO1 diode fabricated by driving the highly

doped side of the diode to the buried oxide is similar to a lateral plane junction from the geometrical viewpoint. Thus, the junction-curvature effect is essentially elimi- nated and the breakdown voltage should be close to that of the ideal plane junction. This technique has been em- ployed to form bidirectional blocking junctions in SO1 for power devices and protection circuit applications 131. Ideal plane junction breakdown was observed in this back- to-back junction structure.

For partially depleted SO1 diodes, the silicon film is sufficiently thick so that it is not completely depleted. As a result, there will be no interaction between the device and the buried oxide. In this case, junction breakdown is similar to that of a bulk-silicon diode which is dominated by the junction-curvature effect. The use of surface-con- tour techniques to prevent premature breakdown across the edge of the junction may improve the breakdown volt- age in the PD SO1 diodes. However, the film thickness of a typical SO1 device is thin enough that full depletion oc- curs prior to avalanche breakdown. Thus, it is important to investigate the avalanche breakdown of a FD SO1 diode occurring in the surface or in the body of the junction.

Simulations of the PD, FD, and lateral diodes were per- formed using PISCES I1 Poisson and continuity equation solver. To save computation time, the dopant density in the lightly doped side was set to 10l6 cmp3 for all three device structures. Junction depth used in the simulation was 0.2 pm, oxide thickness was 0.35 pm, and the epi- layer thicknesses were 0.3 and 12 pm for FD and PD diodes, respectively. The results of PISCES I1 simulation are shown in Fig. 2 , which plots the total electric field in the devices parallel to the surface at a depth of 0.1 pm. The reverse bias is 10 V and the backgate is grounded.

5

4

- - x

- 3 E P v

w

I

0 B 0.0 0 5 1.0 1.5 2.0

I’OSI 1 IOZ [ , m i

Results of PISCES 11 simulation of the PD. FD. and lateral SO1 Fig. 2 . diodes. The plot shows the total electric field in the devices parallel to the surface at a depth of 0. I gm. The metallurgical junctions are located at the peak of the curves.

The simulation results suggest that the electric-field inten- sity near the surface of a FD SO1 diode is between that of a PD (or bulk planar) diode and a lateral SO1 (bulk plane) diode. Similar conclusions were also obtained from the simulation of diodes with the same device parameters as the experimental ones under a 15 V reverse bias. The re- sults indicate that the junction-curvature effect is reduced in a FD SO1 diode compared to that of a PD SO1 diode. The reduction of the surface electric field is mainly due to the combination of voltage sharing between silicon film and buried oxide and the semilateral nature of the FD SO1 diode. This result is consistent with our experimental ob- servation of breakdown voltages for bulk diodes of about 35 f 3 V and for FD SO1 diodes ranging from 39 to 90 V. The increased breakdown voltages in FD SO1 diodes are attributed to the reduced junction-curvature effect. This effect makes SO1 substrate attractive for high-volt- age circuit applications, since additional process is not necessary to reduce the surface electric field.

If the voltage applied to a FD SO1 diode is increased, an inversion layer is formed in the buried oxide-substrate interface. Once strong inversion is reached, the potential at the buried oxide-substrate interface remains relatively constant and the depletion-layer thickness below the in- version layer remains at its maximal value. However. the depletion layer within the silicon film continues to extend laterally. Thus, competition between the surface electric field and the body electric field at the metallurgical junc- tion determines the region of breakdown. With some de- vice parameters, breakdown in FD SO1 diodes can occur in the body rather than in the region of maximum junction curvature. Thus a one-dimensional analysis (across the body of the diode) can be used to describe the junction breakdown in such FD SO1 diodes.

The potential drop in the substrate is not included in the analysis, since this potential drop is about twice the Fermi potential of the substrate. This means that the breakdown voltage would simply shift by this drop. The electrostatic potential at the metallurgical junction ( $,f) of a pf-n diode

490 IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 36. NO. 3, MARCH 1989

and at the top-silicon/buried-oxide interface ( $ & ) , in analogy to SO1 MOSFET theory 141, can be expressed by

$sf = Vu (1 )

where V, and VGb are the applied voltages on p+ contact and backgate, is the potential drop across the buried oxide, and 4 Ls is the back-gate metal-semiconductor work-function difference. If the epilayer is completely de- pleted, then the charge density is qNd. An integration of Poisson's equation across the epilayer yields

( 3 )

where Esf is the electric field at the metallurgical junction, tb is the distance between the metallurgical junction and the top-silicon/buried-oxide interface, Qb = qNdtb is the depletion region areal charge density, and Nd is the dop- ing density in the epilayer, which is assumed to be uni- form.

Applying Gauss' law to the top-silicon-buried-oxide interface gives

(4) 1

-$ob = - ( E s E s f + qNdtb 4- Q f l ) cob

where Cob = eo/ tob is the buried-oxide capacitance, tob is the buried-oxide thickness, and Qfl. is the fixed charge density at the top-siliconlburied-oxide interface, which implicitly includes any fast-interface states. Combining (l) , ( 2 ) , ( 3 ) , and (4), one can obtain the electric field at the metallurgical junction, i.e., the maximum electric field (E, ) in the diode:

where V"FB = 4Ls - Qfl/Cob is the backgate flat-band voltage and c b = e , / t b is the depletion capacitance.

In a lateral SO1 diode, the maximum electric field can be approximately determined from ideal p-n junction the- ory (by neglecting the junction-curvature effect). This is given by

6, = i" (Vbi + V,) 6 ,

where V, is the reverse bias voltage applied to the diode. In a PD SO1 diode the maximum electric field occurs at

the point of maximum junction curvature, and the rela- tions between the maximum electric field and the applied reverse-bias voltage can be calculated from Poisson's equation [ 5 ]

( 7 )

where x, is the depth of junction and is also the radius of cylindrical p-n junction curvature.

IV. RESULTS A N D DISCUSSION The dependence of E,,,, on the applied reverse bias, as

calculated from ( 5 ) , (6), and (7), is shown in Fig. 3 . De- vice parameters used in this calculation are the same as those of the experimental ones. The fixed charge density Qfl is assumed to be zero in this plot. The maximum elec- tric field of a FD SO1 diode which occurs at maximum junction curvature under small bias conditions and at the body of the junction under large bias shows different de- pendence on the applied reverse bias. Before the epilayer is fully depleted, the dependence of G , on the applied bias, which is similar to that of a bulk planar diode, fol- lows (7). Once the depletion edge reaches the buried ox- ide, the maximum electric field, which occurs at the max- imum junction curvature, is between the values calculated from the lateral diode and the PD diode, (6) and (7). This is due to the existence of the buried oxide and the semi- lateral nature of the FD SO1 diode, as suggested by the PISCES I1 simulation. Since the buried oxide absorbs part of the potential, the electric field across the body remains low. For simplicity, we use (6), which gives a minimum value of E,, to approximate the maximum electric field under a medium bias condition, as shown in Fig. 3 . As the bias increases, the inversion layer forms. Due to the limited depletion region depth, the electric field in the body increases faster than that at the junction corner. Fi- nally, maximum electric field occurs in the body, which is consistent with ( 5 ) .

To verify that breakdown in our samples occurred in the body rather than at the junction corner, the depen- dence of the breakdown voltage on the backgate bias was measured. Fig. 4 shows the typical results of the break- down-voltage measurements. In a PD SO1 diode with rel- atively high dopant density (5.9 x 10l6 ~ r n - ~ ) , the break- down voltage is independent of backgate bias. In the FD SO1 diodes the breakdown voltage increases as the back- gate bias increases. Note that the difference between the applied bias on the junction diode and the backgate bias is essentially constant. This implies that the electric field across the body remains constant, i.e., the constant ava- lanching current is supplied by this region rather than at the junction corner. This is consistent with our PISCES I1 simulation which predicts that the junction-curvature effect is less significant in FD SO1 diodes. Also, the linear relation between the breakdown voltage and the backgate bias is consistent with ( 5 ) . It should be noted that the backgate bias may provide a convenient way to increase the diode-breakdown voltage. This backgate bias tends to reduce the electric field across the body, thus increasing diode-breakdown voltage. As shown in Fig. 4, applying a - 30 V to the backgate of a FD diode with a 1.4-pm- epilayer thickness can increase breakdown voltage from 66 to 92 V, which is near the theoretically ideal break- down in a plane junction diode.

Crystallographic defect density has a direct influence

CHEK ~f nl INCREASED JUNCTION BREAKDOWN VOLTAGES

Fig. 3 . Calculated niaximum electric field versus applied bias in the PD. FD. and lateral SO1 diodes.

100

f ,= 1 4 iinl

80 - 80 - 70 - (Io - 50 7

I I

0 1 I I I I I

-40 -20 0 20 40

X ' L h I \ - o l t i i

Fig. 4 . Breakdown voltages as a function of backgate bias in the FD and PD SO1 diodes.

on the breakdown voltage of a p-n junction diode. Lattice defects, impurities, and oxygen precipitates in p-n junc- tions are known to reduce the breakdown voltage [ 6 ] . A high density of fixed charges in the silicon-filmiburied- oxide interface also tends to reduce the breakdown volt- age. Nonuniform breakdown, usually due to the presence of impurities and imperfections, results in "softening of the knee" of the reverse Z-V curves. The fact that soft breakdown occurs in our SO1 samples is an indication of the high densities of defects in the epilayer. Fig. 5 shows the breakdown voltage as a function of distance between the metallurgical junction and the top-silicon-buried- oxide interface ( r , , ) . Solid lines are calculated from (5) with Q f h / q = 0, 5 X lo", and 1 x 10" cmP2 eV-' . The squares are experimental results which represent an av- erage of five devices receiving the same post-implantation anneal. The critical electric field ( 8 , ) was calculated from the empirical formula G , = 4140N::"' V cm-I, with N,, in reciprocal cubic centimeters [7]. The experimental re- sults are qualitatively in agreement with theoretical val-

120.0

100 0

80.0

- < 60.0 ,

40.0

20.0

0.0 0.5 1.0 1.5 2 0 2.5

I,, 1,11111

Fig. S . Breakdown voltage as a function of distance between the metal- lurgical junction and the top-silicon/buried~oxidc interface ( r , , ) , Solid lines are calculated from equation ( 6 ) . with Q , , / q = 0. S X I O " . and I x cm-2 e v - ' in curves I. 2. and 3 . respectively. Squares are experimental results.

ues. The discrepancy is attributed to the high density of localized states and high-field spots caused by impurities and imperfections. Uncertainties in determining buried oxide and epilayer thicknesses are also important. As shown in the figure, the thicker the epilayer, the higher the breakdown voltage. To improve the breakdown volt- age it is also important to control the quality of the buried- oxide layer, i .e.. the fixed charge and surface-state den- sities. High density of these charges can effectively mod- ulate the carrier concentration near the top-sili- con/buried-oxide interface which in turn degrades the breakdown voltage. The buried-oxide layer can be im- proved by high-temperature annealing [8] and low-im- plantation dose [9]. The high-temperature anneal repairs the damage introduced during implantation and allows ex- cess oxygen in the top-silicon layer to out-diffuse, in- creasing the dielectric strength of the buried-oxide layer. The low implantation dose has also been shown to reduce the fixed charges and surface-states densities.

V. CONCLUSION

An analytical breakdown model and PISCES I1 simu- lation are used to characterize junction breakdown in SO1 diodes. The results indicate that in FD SO1 diodes 1 ) the junction-curvature effect is reduced which gives higher breakdown voltage than their bulk-silicon counterparts; 2) breakdown voltages are limited by finite silicon-film thicknesses; 3 ) breakdown voltages can be increased to a value close to the theoretically ideal plane junction by ad- justing backgate bias; and 4) high densities of fixed-oxide charges and surface states at silicon-film-buried-oxide in- terface tend to reduce the breakdown voltage.

ACKNOWLEDGMENT

The authors acknowledge their helpful discussions with F. T. Brady.

492 IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 36, NO. 3, MARCH 1989

REFERENCES 1975- 1976. His research interests include transport and defect characteri- zation in semiconductor materials and devices, solar cells, detectors, high- speed devices, and SIMOX-based SO1 materials and devices. He has served as a consultant to several industrial laboratories and companies. He has authored and coauthored more than 100 conference and journal papers.

S . M. Sze. Physics of Semiconductor Devices. New York: Wiley, 1981. 0. M. Clark. “Voltage breakdown of silicon as influenced by surface angle,” J . Electrochem. Soc., vol. 107, p. 269C, Dec. 1960. B. A. MacIver, K. C . Jain, and S . J . Valeri, “Bidirectional blocking junctions in SOI,” IEEE Circuits Devices Mag., pp. 27-30, Nov. 1987. H. K. Lim and J . G. Fossum, “Threshold voltage of thin-film silicon- on-insulator (Sol) MOSFET’S,” IEEE Trans. Electron Devices, vol. ED-30, pp. 1244-1251, Oct. 1983. H. L. Armstrong, “A theory of voltage breakdown of cylindrical ppn junctions, with applications,” IRE Trans. Electron Devices, vol. 4, pp. 15-16, Jan. 1957.

Dr. Li is a member of the APS, the ECS, and Eta Kappa Nu.

*

K. V. Ravi. Imperfection and Impurities in Semiconductor Silicon. New York: Wiley, 1981. B. J . Baliga, “Silicon Integrated Circuits, Part B, suppl. 2 , ” in Ap- plied Solid State Science, D. Kahng, Ed. New York: Academic, 1981.

[8] B-Y. Mao, P-H. Chang, H . W. Lam, B. W. Shen, and J. A. Keenan, Appl. Phys. Lett., vol. 48, p. 794, 1986.

[9] F. T. Brady, S . S . Li, D. E. Burk, and W. A. Krull, Appl. Phys. Lett., vol. 5 2 , pp. 886-888, 1988.

Hung-sheng Chen received the B.S. degree in electrophysics from National Chiao Tung Univer- sity in 1984 and the M.S. degree in electrical en- gineering from the University of Florida, Gaines- ville, in 1988.

From 1986 to 1988, he was a Research Assis- tant at the University of Florida, working on the defect and electrical characterization of SIMOX- based SO1 devices. His main research interests are in the characterization and modeling of SO1 de- vices, and compound semiconductor optoelec-

tronic devices and materials

Robert M. Fox (S’78-M’80) was born in Bir- mingham, AL, on November 12, 1950. He re- ceived the B.S. degree in physics from the Uni- versity of Notre Dame, Notre Dame, IN, in 1972 and the M.S. and Ph.D. degrees in electrical en- gineering from Auburn University, Auburn, AL, in 1981 and 1986, respectively.

Since 1986, he has served as an Assistant Pro- fessor of Electrical Engineering at the University of Florida. His research interests center on circuit design in advanced technologies including cry-

ogenic CMOS, bipolar, and silicon-on-insulator, and on radiation effects in semiconductors.

Dr. Fox is a member of Eta Kappa Nu, Phi Kappa Phi, the Audio En- gineering Society, and the ASEE.

*

* Wade A. Krull (S’83-M’84) was born in January

Sheng S. Li (M’68-SM’86) received the B S E E 1957 in Aiken, SC He received the B E E de- degree from National Cheng-Kung University, gree, with highest honor, from Georgia Tech and Taiwan, in 1962, and the M S and Ph D de- the M E and Ph D degrees from the University grees, both in electrical engineering, from Rice of Florida. all in electrical engineering University in 1966 and 1968, respectively Since 1984, he has been employed at Harris

He joined the faculty of the Department of Semiconductor, Melbourne, FL as a Staff Engi- Electrical Engineering of the University of Flor- neer working in device technology development ida in 1968 as an Assistant Professor, and became His current interests include all forms of silicon- a full Professor in 1978 He was on sabbatical on-insulator, the development of radiation-hard- leave working at the Electronic Technology Di- ened IC’s, and technology for IC operation at high vision of the National Bureau of Standards in temperatures