INBAND-FEC AS A LOW-COST PERFORMANCE ......INBAND-FEC AS A LOW-COST PERFORMANCE UPGRADE TO ALREADY-DEPLOYED SDH/SONET OPTICAL COMMUNICATION CHANNELS A. Tychopoulos 1, *, P. Zakynthinos

*Corresponding author: E-mail: [email protected]

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Copyright © 2010 SoftMotor Ltd. ISSN: 1744-2400

The Mediterranean Journal of Electronics and Communications, Vol. 6 , No. 2, 2010 46

INBAND-FEC AS A LOW-COST PERFORMANCE UPGRADE TO ALREADY-DEPLOYED SDH/SONET

OPTICAL COMMUNICATION CHANNELS A. Tychopoulos 1, *, P. Zakynthinos 2, H. Avramopoulos 2, O. Koufopavlou 1

1 Department of Electrical and Computer Engineering, University of Patras, Greece 2 School of Electrical and Computer Engineering, National Technical University of Athens, Greece

ABSTRACTWavelength-Conversion (WC) is an essential building-block forall-optical networks. In today’s “state of the art”, it is possible toimplement all-optical WC quite efficiently using Silicon OpticalAmplifiers (SOA). Yet, the high sensitivity of error-performanceto the randomly fluctuating relative-polarization of SOAoptical- inputs, imposes rigid tuning requirements. In order to relaxthese requirements, a sufficient performance-margin must beprovided to the channel. Obtaining this margin by means ofForward Error Correction (FEC) is commonplace nowadays.Inevitably though, existing/legacy FEC-methods will becomeinsufficient as optical transparency scales. To substantiallyupgrade the performance of already-deployed SDH/SONETchannels at an affordable overall cost, we propose a hybridFEC-scheme. Specifically, our scheme combines a standardoutband-FEC method (ITU-T G.975) with a novel inband-FECmethod, called “FOCUS”. The latter has been designed toeffectively combat burst-form errors. This particular property of“FOCUS” meets the distribution of errors, which are generated bythe outband-FEC decoder (former method), when it isoverwhelmed. We evaluate the performance of our proposedinband/outband hybrid FEC-scheme in protecting a 10.66 Gb/slightwave-channel, which has been subjected to all-optical WC bymeans of a SOA-based Mach-Zehnder Interferometer (MZI)switch. Moreover, the MZI-switch was purposely misadjusted toincrease the sensitivity. We show that all-optical WC is renderederror-free and that polarization-control before the converter is nolonger required. We also determine the Coding-Gain (CG) of thehybrid FEC-scheme as well as the net contribution of “FOCUS”.

KeywordsInband-FEC, Reed-Solomon, FOCUS, OpticalCommunications, Wavelength Conversion, Silicon OpticalAmplifier.

1. INTRODUCTIONImpressive laboratory experiments have indicated that all-optical networking is feasible [1-3]. To date however, theperformance of key all-optical devices tends to critically relyon the precise adjustment of signal-parameters, such as powerand polarization. As a result, all-optical networks are currentlylimited to tightly-controlled environments.The performance-margin, required to render all-opticalnetworks field-deployable, can be obtained by introducingForward Error Correction (FEC). The implementation ofFEC-coding by means of electronic devices is an establishedtechnology, which can be efficiently applied at the end-nodesof communication channels, this way sparing the intermediateoptoelectronic conversions.FEC-methods can be classified as, either “outband” or“inband”. The term “outband” indicates that encoding ispayload-agnostic. Implicit in the above definition is that inorder to compensate for redundancy, the line-rate mustincrease relative to the input-rate, inversely proportional to thecoding-rate. Noteworthy is also that on successful decoding,the decoder’s output will be identical to the encoder’s input.As opposed to “outband”, the term “inband” indicates that theunderlying data have a structure that encoding is aware of;furthermore, underlying data are assumed to containsuperfluous overhead, where the encoder can allocate itsparity-symbols. In this case, the line-rate does not need to beincreased, but redundancy is limited by the availability ofoverhead and the decoder’s output is not identical to theencoder’s input. The appropriate figure-of-merit for outband FEC-systems isNet Coding Gain (NCG), because it takes bandwidth-expansion into account [4]. Rather, for inband FEC-systems,NCG falls back to Coding Gain (CG) in the classic sense [5].On the assumption of “unlimited” bandwidth, an outbandmethod can always be found to outperform an inband method,because the performance of the latter is bounded by limitedredundancy. As a result, commercial FEC-systems, designedspecifically for optical communications, generally fall into theoutband class. It is remarkable that during the last fifteenyears, three generations of outband FEC-systems havesucceeded each other, in response to the rapidly increasingrequirements. In particular, a NCG of roughly 6 dB is typicalfor first-generation systems, whereas the second-generationsystems can usually be distinguished by a NCG of roughly 8dB. Lately, a third generation of systems is being deployed orconsidered for deployment. These systems leverage on Turboand LDPC codes to achieve NCG in excess of 10 dB [6, 7].The Synchronous Digital Hierarchy (SDH) and theSynchronous Optical Network (SONET) are the dominantstandards in optical communications. The SDH/SONET

INBAND-FEC AS A LOW-COST PERF. UPG. TO ALREADY-DEPLOYED SDH/SONET OPTICAL COMM. CHANNELS47

synchronous networks share a common frame-format;furthermore, provision has been made for an abundance oftransmission-overhead (OH). Consequently, synchronousSDH/SONET networks lend themselves for Inband Coding(IBC). No doubt, an outstanding performance should not beexpected by inband FEC (iFEC) methods as explained earlier;yet, iFEC-methods have some clear advantages over theoutband FEC (oFEC) ones, such as for instance:• The lower-cost in activating legacy/dark fiber.• The higher potential in dealing with long burst-errors.• The native uniformity in scaling to higher STM-rates.Under the prism of iFEC, the SDH and SONET standards canbe regarded as identical. Without loss of generality, mentionwill be made hereinafter only to the SDH terms; each time, it isimplicit that exactly the same applies to the equivalent ofSONET.Since the early days of SDH, several researchers haveelaborated on the idea of iFEC-coding for opticalcommunications [8-12]. Evidently, these approaches were notintended to be exhaustive. In an interesting advancement,recommendation G.707 of ITU-T specified in 2000 an iFEC-method too [13]. However, optimality of iFEC-coding withregard to SDH was first considered in 2004 [14]. Specifically,the structure of SDH transmission-frames was subjected to athorough optimization, spanning all the linear and systematicFEC-codes. The objective of this optimization was todetermine the code, which is optimal for iFEC-coding overSDH with respect to a number of well-grounded criteria. Theoutcome of optimization was named “FOCUS”, anabbreviation of phrase “Free-Of-Charge Uniform Shield”[14-18].In particular, FOCUS is a sophisticated iFEC-method,applicable to the Regenerator- and Multiplex-sections of anySDH network. Every STM-0 tributary inside the transmittedsynchronous signal is encoded independently. Encoding relieson the Reed-Solomon code RS(244,240,9), which operatesover finite field GF(29) and has been shortened to ~47.8% ofits natural length. Decoding, on the other hand, is possible intwo modes: a) the “strong” mode, where the full redundancy(1.67%) of RS(244,240,9) is utilized, and b) the “weak” mode,where only one half of the redundancy (0.83%) is utilized.“Weak” decoding targets the applications that require only amoderate CG, such as METRO; these applications benefit fromthe reduced implementation-complexity.Initially, FOCUS was evaluated as an independent FEC-method. The evaluation was conducted at the rate of 9.95 Gb/s(STM-64) in a “point-to-point” experimental optical link,whose maximum length was 88 km. The above link wascustomized to isolate the major impairments of opticaltransmission, in succession (one at a time): chromaticdispersion (CD), amplification of noise by the opticalamplifiers (ASE), and non-linear behavior (NL). A CG inexcess of 3.5 dB was demonstrated in combating the ASEnoise with FOCUS in its strong decoding-mode [15, 16]. ThisCG is remarkably close to 3.8 dB, the value theoreticallyachievable by the standard iFEC-method, as claimed in [13].Due to the gradually increasing degree of transparency inoptical networks, we believe that demand for performanceupgrades will soon rise. In this respect, FOCUS could be usedas a supplement to the performance of optical links that wereoriginally equipped with a form of oFEC. Furthermore, such anupgrade would come at a quite low-cost, because the opticalpart of the network is not subject to change. This is in sharp

contrast to the alternative way of upgrading performance, i.e.by introducing a stronger form of oFEC. In this case, transitionto a subsequent oFEC generation is deemed necessary;moreover, if the coding-rate is not preserved, a full redesign ofthe optical part of the network will be required. Hence,upgrades by introduction of stronger oFEC are inevitablyassociated with high-cost. Granted the above, our purpose inthis paper is to demonstrate and evaluate the benefit ofupgrading the performance by combination of iFEC withexisting oFEC.

Specifically, we connect FOCUS in series with anoFEC-system, which adheres to rec. G.975 of ITU-T [19]. Inthis hybrid FEC-concatenation scheme, FOCUS is the outercode that acts as the “safety-valve” which prevents the inner-code from deteriorating the error-rate, when overwhelmed bysevere channel-distortions. To evaluate our proposed FEC-scheme, we choose Wavelength-Conversion (WC), as one ofthe essential building-blocks for all-optical networks. WC wasperformed in a purely optical manner by using a Mach-Zehnder Interferometer (MZI) switch, which is made ofSilicon Optical Amplifiers (SOA) [20]. Evaluation wasconducted at a rate of 10.66 Gb/s (STM-64 x 15/14). Thefollowing measurements have been obtained: a) the reductionof sensitivity of the above all-optical WC device to the randomphase-changes of its optical inputs, and b) the net contributionof FOCUS, when acting as a “safety valve”. To the best of ourknowledge, it is the first time that experimental results arebeing published regarding the combination of an iFEC-methodwith an oFEC-method.

In Section 2, we highlight the most important aspects ofFOCUS functionality; we next outline the functionality ofIXD80102, the evaluation board, used to perform G.975 oFEC.In Section 3, we describe the experimental setup, used toevaluate the hybrid FEC scheme, proposed above. Results arepresented and discussed in Section 4. Finally, conclusions aresummarized in Section 5.

2. IMPLEMENTATION In this section, the implementations of FOCUS and theoFEC-system, which have been concatenated in series tocompose the aforementioned hybrid FEC scheme, areanalyzed.

2.1 The “FOCUS” Inband FEC-SystemThe prototypes of FOCUS have been implemented by buildingon top of “10g-Tester”, a microwave system designed byIntel® to facilitate testing at rates ranging from 10.0 to12.5 Gb/s. In the following paragraphs, the “10g-Tester”system is described first. Thereafter, the functionality ofFOCUS is outlined.

2.1.1 The “10g-Tester” testing-system2.1.1.One of the 10g-Tester systems, used to prototype onFOCUS, is depicted in Fig. 1. In this figure, the most importantparts of a 10g-Tester system are delimited and marked withcapital letters of the English alphabet. With respect to themarks on Fig. 1, a 10g-Tester system consists of:

A) Motherboard: includes a basic user-interface throughbuttons and LED.

B) Programmable logic: a Xilinx® Virtex-II™ FPGA, coded as“XC2V-3000-4-BF957”, whose equivalent ASIC-gate countamounts to 3 million gates.

:

INBAND-FEC AS A LOW-COST PERF. UPG. TO ALREADY-DEPLOYED SDH/SONET OPTICAL COMM. CHANNELS 48

C) Non-volatile memory: a 6-tuple of Xilinx® EPROM, codedas “XC18v04-VQ44™”, which permanently store the FPGAbit-stream, loaded on the FPGA (B) at power-cycle.D) Voltage-controlled oscillators: a 4-tuple of Vectron® VCO,coded as “VS-500-LFF-GNN™”, whose central-frequenciesare 155.52, 166.62, 167.33 and 161.13 MHz.E) High-speed interface: any SerDes daughtercard can be used,provided that it adheres to the MSA300 industrial connectorstandard and supported rates fall into the 10.0 to 12.5 Gb/srange [21].F) Micro-controller: a Bright-Star-Engineering® µ-Ctrl, codedas “NanoEngine™”, which relies on the StrongARM™ CPUand allows for complete remote-control over the 10g-Testerthrough either a FastEthernet (100 Mb/s) LAN port or aRS-232 (19.2 Kb/s) serial port.Importantly, the high-speed interface can be either electrical oroptical. Shown in Fig. 1 is a GiGA® SerDes module, coded as“GD70584/585™”, which is electrical and operates at10 Gb/s.

Figure 1. The “10g-Tester” testing-system. A) motherboard, B) FPGA, C) EPROM, D) VCO, E) SerDes, F) µ-Ctrl

The functionality of 10g-Tester is outlined in Fig. 2. Bulk dataprocessing takes place inside the FPGA. The optical network isinterfaced through the SerDes. In specific, the interfacebetween FPGA and SerDes adheres to agreement SFI-4 of theOIF [22]. Jitter generation and transfer are controlled, using a155.52 MHz local-oscillator as “reference”. Transmitting andreceiving rates, denoted as T and R respectively, are notnecessarily equal to each other. Valid T and R rates arespecified as follows:

The implementation of Tx-bus and Rx-bus is of keyimportance to the operation of 10g-Tester. Each bus consists of16 data-lines and a single clock-line, which synchronizes incommon the data-lines. Data-lines operate at 1/16 of the serial-rate; in accordance, the associated clock-line operates at 1/16of the serial-frequency, which is equal to 1/8 of thecorresponding serial-rate. However, the max rate at whichXilinx® Virtex-II™ FPGA differential I/O ports are operable,is 840 Mb/s. Therefore, assuming the lowest possible T and R

(9.95 Gb/s), the above max I/O rate suffices for data-lines(622.08 < 840 Mb/s), but not for the associated clock-line,since I/O rate doubles in the latter case (622.08 MHz * 2 =1244.16 Mb/s > 840 Mb/s). This shortcoming was remedied bytaking advantage of the DDR logic inside the FPGA. InDDR-mode, FPGA flip-flops are triggered at both edges oftheir clock-input. In specific, the forward clocks TxPCLK andRxPCLK had to be frequency-divided by 2 and the backwardclock TxPICLK had to be frequency-multiplied by 2 (Fig. 2)[22].

Figure 2. An outline of 10g-Tester’s functionality

Figure 3. The main elements of the prototypes of FOCUS, which were implemented by means of a Xilinx® Virtex-II™

FPGA, situated on 10g-Tester (S: serial, P: parallel)

2.1.2 Outline of the FOCUS methodFOCUS has been prototyped at the rate of STM-64 (10 Gb/s)by means of the Xilinx® Virtex-II™ FPGA, situated on10g-Tester. The structure of FOCUS prototypes is shownabove, in Fig. 3. In particular:

A) FOCUS-Transmitter: SDH STM-64 frames, which areeither generated internally (test frames for BER measurement)or looped-back from the FOCUS receiver (rear loop-back), areencoded, according to the FOCUS method.

⎭⎬⎫

≤≤≤≤

sGbRsGbT

/5.1295.9/5.1295.9 (1)


B) FOCUS-Receiver: SDH STM-64 frames, which arriveeither from the optical channel (DDR Rx-bus) or from theFOCUS Transmitter (front loop-back), are decoded, accordingto the FOCUS method.

C) FIFO: a FIFO-buffer of sufficient depth has been introducedin every loop-back path to absorb the jitter of the transmit- andreceive-clocks – it is noteworthy that FIFO-buffers have beenequipped with an overflow-detection mechanism.

D) Converter: the data-bus bitwidth is increased from16 bits (Rx-bus) to 128 bits.

E) Converter: the data-bus bitwidth is decreased from128 bits to 16 bits (Tx-bus).

F) µ-Ctrl Interface: register files for monitoring and control

The block-diagram of “FOCUS-transmitter” is given in Fig. 4.The functionality of each block is briefly analyzed below:

PRBS/Constant Pattern Generator: A stream of data isproduced, whereupon the characteristics of SDH frames will beimprinted. The following options are provided:a) pseudorandom sequence: PRBS-31 (period 2147483647bits) and b) constant data pattern: cyclic repetition of eitherpattern F0F016 (a clock of frequency 1.244-GHz) or pattern00FF16 (a clock of frequency 622-MHz).

SDH/SONET Framing: The major regenerator- and multiplex-section (RS/MS) characteristics of SDH STM-64 frames (e.g.octets A1/A2) are iteratively imprinted on the continuous data-background, created by the previous block.

Figure 4. The block-diagram of “FOCUS-transmitter” as implemented in the prototypes of FOCUS

SDH/SONET Frame Alignment: A variant of thecorresponding block, comprised by the FOCUS-receiver. Allsubsequent blocks remain idle, unless frame-alignment hasbeen achieved.

B1-B2-RS Checksums Overwrite: The B1 & B2 BIPchecksums, which have been computed over the past SDHSTM-64 frame, are placed at the designated timeslots of thecurrently processed SDH STM-64 frame. In addition, theReed-Solomon checksums of FOCUS (RS), which have beencomputed over the past row-triplet of the transmitted SDHSTM-64 frames, are placed at the designated timeslot of thecurrently processed row-triplet.

Modification of Selected Octets: Any octet in the SDHSTM-64 frame can be assigned with a configurable value, orsequence of values (string, 16 or 64 octets long).

FOCUS Encoding: Each of the STM-0 subframes, comprisedby an SDH STM-64 transmission-frame, is encodedindependently. Inside STM-0 subframes, three rows areencoded at a time (row-triplet) and the generated parity-bitsare buffered. When the next row-triplet arrives, these parity-bits are extracted from the buffer and placed at predefinedpositions within the SOH of the current row-triplet. The parity-bits of the previous row-triplet are always excluded from theencoding of current row-triplet, because their inclusion isdamaging: a single error might distort more than one codeword(FOCUS-decoding is not iterative) [14, 17].

B2 Checksum Computation: A BIP-192x8 checksum,computed (prior to scrambling) over the entire STM-64 frame– except for RSOH. Resulting checksum is assigned to the B2MSOH octets of the next frame [13].

Scrambling: The SDH STM-64 signal is scrambled with aframe synchronous scrambler, which operates at line rate witha period of 127 bits. The generating polynomial has beendefined as: g(x) = 1 + X6 + X7. Scrambling is continuousthroughout the SDH STM-64 frame except for the first row ofRSOH [13].

B1 Checksum Computation: A BIP-8 checksum, computed(post to scrambling) over the entire STM-64 frame. Resultingoctet is assigned to the B1 RSOH octet of the next frame [13].

Error Injection: SDH STM-64 frames can be purposelydistorted in order to verify the correct operation of FOCUS. Inparticular, each of the STM-0 subframes of a SDH STM-64transmission-frame is individually selectable forerror-injection. Errors can be either a single-bit or a multiple-bits inversion within an octet. Up to 4 errors can be injectedper STM-0. By enabling the injection of j errors, all distinctcombinations of j error-locations will be applied to the selectedSTM-0 subframes in a frame-synchronous manner, onecombination per frame (125 µs). Upon completion of onerevolution, the injection-algorithm automatically recycles(restarts) until it is manually disabled [14].

Figure 5. The block-diagram of “FOCUS-receiver” as implemented in the prototypes of FOCUS

High-Speed Interface (Tx-Bus): The 128-bit parallelprocessing data-bus is narrowed to 16-bit parallel to meet

S P→

P S→


Tx-Bus bit-width. In accordance, clock-frequency is increasedfrom 77.76 MHz to 622.08 MHz.

The block-diagram of “FOCUS-receiver” is given in Fig. 5.The functionality of each block is briefly analyzed below:

High-Speed Interface (Rx-Bus): The 16-bit wide data output ofthe Deserializer is broadened to 128-bit parallel, as apreparative step for bulk processing to follow. In accordance,the clock-frequency is decreased from 622.08 MHz to 77.76MHz.

Monitoring of Periodic Sequences: The internal 128-bitsparallel processing data-bus is directly mapped to the registerfile (µCtrl I/F) i.e. prior to any processing. In total, 16 registersare required to map the whole data-bus, because the bit-widthof all registers is 8. Any periodic binary sequence, whoseperiod divides exactly the bus bit-width, appears stationary.Therefore, such sequences can be observed through the µCtrlI/F. This feature turned out to be very useful in debugging the10g-Tester, the most common input being a division of theinput clock. With a 155.52 MHz clock as data-input, forinstance, period is equal to 64 bits (128 mod 64 = 0); arandomly shifted version of “FFFFFFFF0000000016” is toappear twice over the bus.

SDH/SONET Frame Alignment: Alignment of the arrivingSDH STM-64 frames with the 128-bits parallel-processingdata-bus is continuously sought. Unless frame-alignment hasbeen achieved, subsequent blocks remain idle. Functionalcharacteristics adhere to ITU-T recommendation G.783 [23].

Count STM-64 failing checksum B1: Computation ofchecksum B1 is identical to the one in FOCUS-transmitter: B1is computed (prior to unscrambling) over the entire STM-64frame. Resulting checksum is compared with the B1 RSOHoctet of the next SDH frame. Mismatches are accumulated overthe statistics’ interval (see: “Timer”) and the associatederror-counter is 16 bits wide.

Unscrambling: Scrambling of SDH STM-64 frames inFOCUS-transmitter is canceled in FOCUS-receiver byapplying exactly the same operation again i.e. unscrambling isidentical to scrambling [13].

Count STM-0 (subframes) failing checksum B2: Computationof checksum B2 is identical to the one in FOCUS-transmitter:B2 is computed (post to unscrambling) over the entire STM-64frame, except for RSOH. The resulting checksum is comparedwith the B2 MSOH octets of the next frame. The count ofSTM-0 subframes with mismatches is accumulated over thestatistics’ interval (see “Timer”); the associated error-counteris 24 bits wide. Post-FEC block is to indicate the improvementdue to FOCUS-decoding.

FOCUS Decoding: Each of the STM-0 subframes, comprisedby an SDH STM-64 transmission-frame, is decodedindependently. Inside STM-0 subframes, three rows aredecoded at a time (row-triplet). In specific, after decoding anentire row-triplet, FOCUS-decoder stalls; FOCUS-decodingcontinues, when the associated parity-bits have been extractedfrom their predefined positions in the SOH of the next row-triplet. Evidently, decoding of adjacent row-triplets overlaps intime. In case the current word is detected to be in error, itscorrection will be attempted. However, FOCUS decoderrefrains from correcting, if the word is early diagnosed as“irreparable”, so as to limit error-extension. Received data aredelayed until decoding is fully completed. Decoding failuresare accumulated over the statistics’ interval (see: “Timer”) andthe associated error-counter is 24 bits wide [14, 17].

Access to Selected Octets: Any octet in the SDH STM-64frame may be optionally accessed through µCtrl I/F either as aconstant value (single octet) or as strings of configurablelength (16 or 64 octets long) [14].

BER Computation: In order to provide BER indications,FOCUS receiver is assumed to be fed with SDH STM-64 test-frames that transport plain PRBS-31 instead of a VC-4-64c;such test-frames can be generated by the FOCUS transmitter.Taking into account the exclusion of SOH, BER-measurementreflects (90-3)/90 = 87/90 96.67% of the serial data-rate.Bit-errors are accumulated over the statistics’ interval (see:“Timer”) and the associated error-counter is 32 bits wide[16, 18].

Timer: The so-called “statistics’ interval” is delimited, i.e. atime interval of configurable periodicity, during whichaccumulation of statistics takes place. At the end of each“statistics’ interval”, statistics are copied from all relevantblocks to the register-file (µCtrl I/F), wherefrom they will beaccessible to the user during the next “statistics’ interval”.Importantly, the copied statistic-values are kept constantthroughout the whole interval to ensure that the µCtrl does notread data at the instant of their updating; such a coincidencewould jeopardize the integrity of the statistic values, possiblycausing false alarms. For the same reason, a µCtrl readoperation prohibits the corresponding statistic-value frombeing updated for as long as it lasts. The duration of “statistics’interval” can be configured between 1 and 256 sec (in 1 secsteps). Max duration has been chosen to allow for BERmeasurements as accurate as 10-12 [14].

FOCUS-encoding leverages on RS(244,240,9), a shortenedReed Solomon code, defined by the generator polynomialgc(x):

The underlying arithmetic is defined on the finite extensionfield GF(29), generated by the binary primitive polynomialgf(x):

Noticeably, gf(x) has the minimum possible weight forprimitive polynomials i.e. only 3 non-zero coefficients. As aconsequence, the cost of the most complex arithmeticoperations (division and multiplication) is minimized as well.(a = 0028) has been chosen as the primitive element of theabove field GF(29) [14].

Assuming that an iFEC-system is concatenated in-series withan oFEC-system, as long as the latter proves to be effectiveagainst channel-errors, the former detects absolutely no errors;however, when the latter is transiently overwhelmed bychannel-errors, the former will be “stormed” by errors, due toerror-extension at the oFEC-decoder. In order to withstand thishigh strain and yield an appreciable coding-gain, FOCUSneeds to secure that itself does not extend errors; this propertytranslates to an early detection of decoding-failures so that allpending corrections are immediately canceled. The mosteffective criterion to detect decoding failures is a comparisonbetween degree & root-count of the error locator polynomialλ(x): if they are equal, then the decoder may proceed with

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corrections; otherwise, corrections should be suspended [5].Nonetheless, the above criterion incurs the doubling ofdecoding latency and a substantial increase of theimplementation-cost. As a result, the prototypes of FOCUScould not afford incorporating it. Instead, a trade-off betweendetection-effectiveness, decoding latency and implementationcost has been achieved. Specifically, FOCUS-decoder checkswhether λ(x) has “multiple” roots. This is convenient withdouble-error correcting Reed-Solomon codes, such asRS(244,240,9). In this case, λ(x) is a trinomial (at most) andthe presence of a double-root is directly indicated by a first-power coefficient equal to zero [17]:

This is in sharp contrast to integer arithmetic, where:

By incorporating the root-multiplicity criterion, FOCUS-decoder detects only part of the decoding-failures, but this isachieved at no additional latency, whereas implementation-cost reduces to a simple comparison with zero. At this point, itis noteworthy that the resistance of FOCUS to error-extensionis also improved due to the shortening of RS(244,240,9):statistically, during an error-overflow, more than 50% ofextended errors will fall outside the length of the code, i.e. atsymbol-positions, ranging between 244 & 510 (counting from0); as a result, these errors will be spared.

Figure 6. State-diagram of frame-alignment as implemented in FOCUS prototypes: = success, X = failure (contiguous)

FEC-performance is also influenced by the robustness offrame-alignment, especially when under high strain, which isdefinitely the case in this paper. Once more, however,implementation-cost took priority over robustness in FOCUSprototypes. Specifically, frame-alignment has been designed toseek and verify only one A1 RSOH octet (out of 192, in total)& one A2 RSOH octet (out of 192, in total); nonetheless, aslong as it remains synchronized, all 192 A1 & A2 RSOH octetsare automatically restored to their correct value. With regard toFig. 6, the relevant state-diagram involves the following states:

• SEEK (seeking): The A1/A2 framing-octets arecontinuously sought; if they are not detected within 3frame-times, the state of input-data multiplexer advances.

• CHK (checking): Correctness of the currently assumedframe-alignment is verified.

• IF (in-frame): Successful synchronization is indicated.

• OOF (out-of-frame): Synchronization-instability is indicated.

• LOF (loss-of-frame): Synchronization-problems are indicated.

Last but not least, FOCUS establishes a channel to allow forthe remote activation / deactivation of FEC decoding. This isrequired for backwards compatibility. 4 bits are committed perrow-triplet in SOH, adding to the ones allocated for parity.These cannot be protected by FOCUS itself (is preposterous).To avoid accidental deactivation of FOCUS-decoder, 4-bitmajority logic is applied.

2.2 The IXD80102 Outband FEC-SystemThe oFEC-system, which acts as inner code in the proposedFEC concatenation scheme, has been implemented by means ofIntel® IXD80102, evaluation board for the Intel® IXF30005ASIC. The latter, more widely known as WRAP100™, is adigital wrapper, which complies with ITU-T recommendationsG.975 (2000) and G.709 (2003) at the STM-64 rate. Theserecommendations adopt the same Outband FEC, i.e. 16-waybyte-interleaved Reed-Solomon RS(255,239) codes [19, 24];notwithstanding, they differ as far as frame-structure andcoding-rate are concerned. Noteworthy is that IXD80102 isclassified as a first generation FEC system; as a result, theNCG is roughly equal to 6 dB at a reference BER of 10-12,assuming AWGN as the only source of distortion. NCG ismore accurately specified in [4] as 5.6 dB, at the same BER.

Figure 7. Notation of Intel® IXD80102 evaluation board

As shown in Fig. 7, the points of the compass are used to mapthe various functions of Intel® IXD80102. Specifically, thereare two major interfaces:

a) The interface to the optical link, called the “western” or“line-side” interface: data-rate is equal to 10.71 Gb/s inG.709-compliant mode and to 10.66 Gb/s in G.975-compliant-mode

b) The interface to the SDH network, called “eastern” or“system side” interface: data-rate is always equal to 9.95 Gb/s

In addition, there are two data-processing buses (Fig. 7):

a) The “southern” bus, which encodes system-side data

b) The “northern” bus, which decodes line-side data

Intel® IXD80102 features a longitudinal symmetry ofoperation, i.e. the axis of symmetry is parallel to the data-processing buses. Granted that the above data-processing busesoperate in opposite directions, symmetry is odd. With respectto the marks on Fig. 8, the major components of Intel®IXD80102 are:

( ) 2222 bxabxa +∗=+∗

( ) 0,2 2222 ≠⋅+⋅⋅⋅+⋅=+∗ babxbaxabxa

(4)

(5)


A) Motherboard: hosts Vectron® VCO’s, tuned at thefollowing central-frequencies: 622.08, 666.25 & 669.37 MHz,mainly acting as a clock-gearbox.

B) WRAP100™ ASIC: implements digital wrapping, accordingto ITU-T G.975 and G.709 (including FEC).

C) Line-side interface: any SerDes daughtercard can be used,provided that it adheres to the MSA300 industrial connectorstandard and supported rates are either 10.66 or 10.71 Gb/s.

D) System-side interface: any SerDes daughtercard can beused, provided that it adheres to the MSA300 industrialconnector standard and the STM-64 rate (9.95 Gb/s) issupported.

E) Micro-controller: a daughtercard, coded as Intel®GD70001, which relies on the ARM™ 7 CPU and allows forcomplete remote-control over the IXD80102 board through aRS-232 (19.2 Kb/s) serial port (user-side).

Figure 8. Intel® IXD80102. A) motherboard, B) WRAP100™ ASIC, C) line-side SerDes, D) system-side SerDes, E) µCtrl.

Figure 9. The specific hybrid inband/outband FEC-scheme, evaluated in this paper. A) Intel® IXD80102: G.975 Tx & Rx,

B) 10g-Tester: FOCUS Tx, C) 10g-Tester: FOCUS Rx

3. EXPERIMENTAL SETUPFig. 9 shows the specific hybrid inband/outband FEC-scheme,which was evaluated in this paper. With respect to the markson Fig. 9, it consists of the following subsystems:A) An Intel® IXD80102 system, configured to performoutband FEC-coding according to ITU-T G.975.B) A 10g-Tester system, which generates SDH STM-64frames, encoded according to the FOCUS inband FEC method.C) A 10g-Tester system, which decodes received SDH STM-64 frames according to the FOCUS inband FEC method and inaddition, measures BER (optionally, prior or post to FEC).At the transmitting 10g-Tester (B), an Intel® LXT16717™MUX is used to serialize the outgoing SDH STM-64 frames,while at the receiving 10g-Tester (C), an Intel® LXT16716™DEMUX is used to parallelize the returning SDH STM-64frames again. The interface between the two 10g-Testersystems and the IXD80102 system is electrical; the signal-modulation is OOK and the line-coding is NRZ. Both10g-Tester systems are controlled remotely throughFastEthernet (10/100 Mb/s). The most frequent remote-operations are: FEC-activation/deactivation and mode-switching (weak/strong), scrambling activation/deactivation,codeword and bit error-count and, interrupt requestacknowledgement.Intel® IXD80102 was configured in G.975-compliant mode; asa result, the exact coding-rate is equal to 14/15 0.93 and theexact line-side rate is 10.66 Gb/s. At the opposite side(system), rate is equal to STM-64, i.e. 9.95 Gb/s. At both thesystem-side and the line-side, an Intel® LXT16785 MUX isused for serialization and an Intel® LXT16784 DEMUX fordeserialization. Consequently, the interface is electrical at boththe system and line-sides, using OOK as signal-modulationand NRZ as line-coding.

Figure 10. Outline of inband-FEC (FOCUS) in serial concatenation with outband-FEC (G.975)

The operation of this inband/outband concatenated-FECscheme is outlined in Fig. 10. With regard to this figure,specifically:Transmission path: 10g-Tester #1 generates STM-64test-frames (9.95 Gb/s). The payload of these test-frames isequal in size and rate with VC-4-64c (9.62 Gb/s); however,this virtual-container has been completely replaced by aPRBS-31, which is generated by the binary primitive

≈


polynomial p(x) = x31+x3+1. Generation of PRBS-31 adheresto the SDH transmission-order. Afterwards, test-frames areencoded according to FOCUS and transmitted to WRAP100™.These encoded frames are received at the system-side ofWRAP100™. Next, they are subjected to a second round ofencoding, this once according to ITU-T G.975 (outband). Thedouble-coded frames are finally transmitted at line-side,feeding the all-optical wavelength-conversion device at10.66 Gb/s.

Reception path: After wavelength-conversion, test-framesreturn to the line-side of WRAP100™ (10.66 Gb/s). Next, theseframes are decoded according to ITU-T G.975 (outband).However, it is underlined that corrections, which result fromoutband decoding, might become malicious, in case thedecoder is overwhelmed by channel-errors. Afterwards,corrected test-frames are transmitted from the system-side ofWRAP100™ to the 10g-Tester #2 (9.95 Gb/s). Test-frames,received by 10g-Tester #2, are subjected to a second round ofdecoding, this once according to FOCUS. Last, the correctedPRBS-31 is detached from test-frames and used to feed theBER-measurement unit.

As explained above, the two FEC-methods (outband andinband) have been concatenated (arranged, connected) inseries, with the outband (ITU-T G.975) acting as the inner andinband (FOCUS) as the outer code. Strikingly, no interleavinghas been introduced between the FEC methods, as opposed tothe approach of Forney [25]. The primary reasons behind thisare: a) the requirement for backwards compatibility, whichsignificantly complicates the “a posteriori” introduction of aninterleaver (Fig. 11) and, b) the fact that FOCUS takesadvantage of the linear octet-interleaving, which is native toSDH frames [13].

Figure 11. “A posteriori” concatenation of an (h,k) inband-FEC code in series with an existing (n,h) outband-FEC code, ensuring that interleaving (π) is transparent to SDH nodes

With regard to the electronic part of the experiment,noteworthy are also the following:

a) The generation of PRBS-31 is asynchronous to the STM-64frames i.e. all of the 231-1 bits are sequentially generated.

b) SDH-scrambling has been disabled, so that it does notmodify the properties of the underlying PRBS-31 pattern.

c) To take the exclusion of SOH into account, BER iscomputed through the following formula:

where:• ErrCnt (Errors Count): The count of bit-errors, detected

over the past statistics interval, indicated by the BER-Computation block.

• StatInt (Statistics Interval): The duration of statisticsinterval (in seconds).

• FrmPerSec (Frames per second): The number of SDHframes, transmitted in one second (i.e. 8000 frames).

• STM64bits (Bits in a STM-64 frame): The total count ofbits, contained in an SDH STM-64 frame (i.e. 1244160bits).

• PayColRat (Payload-Columns Ratio): The ratio of“payload-columns” to the total of columns in STM-0(87/90 = 0.966…).

Figure 12. The experimental setup for SOA-based all-optical wavelength-conversion

The optical circuit, which was used to measure theperformance of the aforementioned hybrid inband/outbandconcatenated-FEC scheme, is shown in Fig. 12. Specifically, aCW optical signal at 1545 nm is injected into a Ti:LiNbO3electro-optic modulator, driven by the output pulses of theoutband-FEC (WRAP100™) transmitter (Fig. 12, stage A). Theoptical modulator’s output is connected as control-signal to ahybrid integrated-SOA Mach-Zehnder Interferometer (MZI),which in this case, acts as an all-optical wavelength-converter(WC); a CW optical-signal at 1556 nm is connected to the MZIas input-signal. Data exit the MZI at the other wavelength i.e.at 1556 nm (Fig. 12, stage B). MZI’s output is filtered by anOptical Band-Pass Filter (OBPF), whose bandwidth is equal to1 nm. Received optical power is controlled by an opticalattenuator (ATT). A photodiode (PIN) converts the incidentNRZ optical pulses to electrical ones, which finally feed theline-side receiver of outband-FEC (Fig. 12, stage C).

4. RESULTSThe previously described experimental setup was used toobtain two sets of measurements. The first set of measurements

StatIntErrCnt

PayColRatbitsSTMFrmPerSecStatIntErrCntBER

*9621504000

*64**

=

=(6)


led to a couple of “output-BER vs. received optical power”plots (Fig. 13 and 14), which accurately characterize theproposed concatenated-FEC scheme. The second set ofmeasurements was taken with outband-FEC (WRAP100™) onthe verge of collapse to highlight the role of inband-FEC(FOCUS) as a safety-valve. The associated “output-BER vs.input-BER” curves are given in Fig. 15. It is underscored thatfor wavelength conversion to be optimum (i.e. to achieve theminimum polarization sensitivity), the average input- andcontrol-signal powers into the MZI must equal 9 and 6 dBmrespectively. Nonetheless, to demonstrate the performance ofthe proposed hybrid FEC system, the sensitivity of MZI to thepolarization of its input-signals, was deliberately enhanced byreducing the input and control-signal powers to 1.5 dBm and2.5 dBm respectively.In measuring BER with respect to received-power (first set),the two following extreme cases were examined: a) optimumand b) worst-case polarization of the optical control-signal, asshown in Fig. 13 and Fig. 14 respectively. Polarization of theinput-signal was always kept constant at its optimum value.Optimum- and worst-case polarizations were determined withrespect to the received-power, as providing the lowest- andhighest-BER at the receiving end, respectively.As of Fig. 13, error-free communication is achievable withoutFEC at the optimum polarization of the control-signal, whenthe received optical power is greater than or equal to -15dBm.Yet, the activation of FEC incurs a negative power-penalty ofapprox. 10.5 dB at an output-BER of 10-12, regardless ofFOCUS-mode (weak/strong). On the other hand, a residualerror-floor is always observable (regardless of the received-power), when polarization of the control-signal departs fromits optimum value. In specific, Fig. 14 shows the curves of“output-BER versus received-optical power” at the worst ofcontrol-signal polarization. In this case, an error-floor of 10-5

manifests itself, even at the maximum power tolerated by theoptical receiver, as long as FEC remains inactive; by activatingthe proposed FEC scheme, the error-floor is practicallyeliminated; error-free reception is now achievable at-20.5 dBm with FOCUS in the weak mode and, at -21.2 dBmwith FOCUS in the strong one. System-response atintermediate values of polarization has been found similar.Noteworthy is that the concatenated-FEC scheme does notonly correct the errors induced by the polarization drift, but italso improves the performance of the wavelength-converter interms of received optical-power. To obtain a measure ofefficiency, we computed the coding-gain (CG) of the proposedFEC-scheme, according to the definitions of ITU-Trecommendation G.975.1 (2004). In particular, the net coding-gain amounts to ~6.5/7.0 dB at an output-BER of 10-12, withFOCUS in its weak- and strong- mode, respectively.Fig. 15 highlights the particular contribution of FOCUS in theproposed hybrid concatenated-FEC scheme. As long as theinner code (WRAP100™) dominates over the channel, fullycorrecting the errors, the outer code (FOCUS) observes error-free data and therefore, remains idle. However, when the innercode succumbs to an overwhelming error-rate, error-extensionwill be observed. Then, it is the task of the outer code toeliminate the errors to the best possible degree. Wedemonstrate the protective intervention of FOCUS by actuallydriving WRAP100™ to the verge of error extension. At thispoint, we measure performance by modifying the polarizationof the control-signal, while keeping the received powerconstant. Measurements were obtained in succession for 3different values of the received optical power: -18.2 dBm,-17 dBm and 16 dBm. The associated “output-BER vs. input-

BER” curves, shown in Fig. 15, reveal an orders of magnitudeimprovement, fully attributable to FOCUS.

Figure 13. Output-BER versus Received Optical Power, when control-signal polarization is at the optimal-point.

Figure 14. Output-BER versus Received Optical Power, when control-signal polarization is at the worst-point.

As reported in ITU-T G.975.1 [3], the theoretical NCG of ITU-T G.975-compliant FEC (WRAP100™) amounts to ~5.6 dB atan output-BER of 10-12. The proposed hybrid FEC scheme hasbeen found in practice to outperform the above standard by~0.9 dB with FOCUS in the weak mode and by ~1.4 dB withFOCUS in the strong mode. This “head” in performance can beconsidered as the nominal net contribution of FOCUS.Strikingly, the CG of FOCUS turns out to be (less than) half ascompared with the one reported in [16]. This markeddiscrepancy is due to the different role of FOCUS: In [6],FOCUS is characterized as a stand-alone FEC-method and isevaluated against a non-biased transmission-errors distribution(ASE). Notwithstanding, in this case, FOCUS is evaluated inconjunction with another (outband) FEC-method: FOCUSeither observes error-free data or has to deal with highly biasederrors (i.e. with bursts of errors), which result from error-extension at the outband decoder (WRAP100™). It isreasonable that when the error-rate becomes excessive,error-extension may also manifest itself at theFOCUS-decoder. The net contribution of FOCUS results lower


because it is a macroscopic quantity i.e. the sum of all positiveand negative contributions in the statistics interval. Overall, weregard this performance as an achievement. The measurednet-contribution of FOCUS per received-power is reported inTable 1.

Figure 15. Output-BER versus input-BER, when outband-FEC (G.975) is deliberately driven to overflow.

5. CONCLUSIONSOur work builds on the experimental evaluation of FOCUS asan independent inband-FEC method [16]. In this paper,FOCUS has been concatenated in series with a first-generationoutband-FEC method [19]. The experimental evaluation of theresulting hybrid inband/outband concatenated-FEC scheme,reveals a remarkable performance improvement, as comparedto the standard outband first-generation FEC; the additionalcoding-gain is attributable to FOCUS. It is noteworthy that thecoding-gain was increased without resorting to a customredesign of the optical link (i.e. employing more complex andlower code-rate outband-FEC methods). This property isespecially important in upgrading legacy networks.

The proposed hybrid inband/outband concatenated-FECscheme was evaluated in a purposely misadjusted all-opticalwavelength converter (a SOA-based MZI). Even so, theintroduction of FEC ensures error-free wavelength-conversionand moreover, renders polarization control unnecessary. Wededuce that FEC may relax requirements for criticaladjustment, when all-optical devices are used in-the-field. Inother words, our results indicate that the use of FEC can bringall-optical techniques and transparent optical networks closer.

To the best of our knowledge, the experimental evaluation of ahybrid inband/outband-FEC scheme is reported for the firsttime. As a consequence, this work is also the proof-of-conceptof the previously claimed seamless integration of inband-FECwith any other form of outband-FEC [7, 14]. Today, FOCUS isa mature and low-cost solution; notably, it offers two modes ofoperation, the weak mode and the strong mode, which

constitute a trade-off between complexity and performance[17].

GLOSSARY OF ABBREVIATIONSADM Add / Drop MultiplexerASE Amplified Spontaneous EmissionsAWGN Additive White Gaussian NoiseBER Bit Error Ratio/RateBIP-n Bit-Interleaved Parity (n: interleaving depth)CG Coding GainDDR Double Data Ratedmin Minimum Distance in the Hamming senseEDFA Erbium-Doped Fiber-AmplifierFEC Forward Error CorrectionFIFO First-In First-Out (buffer mode)FPGA Field-Programmable Gate ArrayGF “Galois” Field HDL Hardware Description LanguageHS High-SpeedIBC In-Band (FEC) CodingIC Integrated CircuitiFEC In-band FECITU International Telecommunication UnionITU-T ITU- Telecommunications standardization sectorLDPC Low-Density Parity-CheckLED Light Emitting DiodeMSA Multi-Source AgreementMSOH Multiplex Section OverheadMZI Mach-Zehnder InterferometerMZM Mach-Zehnder ModulatorNCG Net CGNF Noise-FigureNL Non-Linear effectsNRZ Non Return to ZeroOA Optical AmplifierOBC Out-Band (FEC) CodingOBPF Optical Band-Pass FilteroFEC Out-band FECOIF Optical Internetworking ForumOSNR Optical SNRPOH Path OverheadPRBS Pseudo-Random Binary-SequencePRBS-n: PRBS with period 2n-1PTE Path Terminating EquipmentRS Reed-Solomon / Regenerator SectionRSOH Regenerator Section OverheadRTOS Real-Time Operating SystemSDH Synchronous Digital Hierarchy

Table 1. The measured net-contribution of FOCUS in the proposed hybrid concatenated-FEC system


SerDes Serializer - Deserializer

SNR Signal to Noise Ratio

SOA Silicon Optical Amplifier

SOH Section Overhead

SONET Synchronous Optical Network

STM-M Synchronous Transport Module – rate level M

VC Virtual Container

VCO Voltage Controlled Oscillator

VHDL Very high speed IC HDL

WC Wavelength Conversion

WDM Wavelength Division Multiplexing

XC Xilinx Component

µ-Ctrl micro-Controller

AcknowledgementThe authors would like to thank the Intel Corp. for granting theIXD80102 system (WRAP100™ evaluation board). This workwas financially supported by EU Commission throughprojects: “IST e-Photon/ONe+” (027497) and “ICT-BONE”(216863).

REFERENCES[1] K. E. Stubkjaer, “Semiconductor Optical Amplifier-based

All-Optical Gates for High-speed Optical Processing”, IEEEJournal of Selected Topics Quantum Electronics, Vol. 6,Nov.-Dec. 2000, pp. 1428-1435.

[2] D. J. Blumenthal, J. E. Bowers, L. Rau, Chou Hsu-Feng, S.Rangarajan, Wang Wei and K. N. Poulsen, “Optical SignalProcessing for Optical Packet Switching Networks”, IEEECommunications Magazine, Vol. 41, No. 2, Feb. 2003,pp. S23 - S29.

[3] S. J. B. Yoo, “Optical Packet and Burst SwitchingTechnologies for the Future Photonic Internet”, IEEELightwave Technology Journal, Vol. 24, No. 12, Dec. 2006,pp. 4468-4492.

[4] ITU-T Recommendation G.975.1, “Forward Error Correctionfor High Bit-rate DWDM Submarine Systems”, in Series G ofITU-T recommendations, ITU, Feb. 2004.

[5] I. S. Reed, X. Chen, “Error Control Coding for DataNetworks”, Kluwer Academic Publishers, Dordrecht, TheNetherlands, 1999, ISBN-13: 978-0792385288.

[6] A. Tychopoulos, O. Koufopavlou and I. Tomkos, “FEC inOptical Communications: a tutorial overview on the evolutionof architectures and the future prospects of outband andinband FEC for optical communications”, IEEE Circuits &Devices Magazine, Vol. 22, No. 6, 2006, pp. 79-86.

[7] T. Mizuochi, “Recent Progress in Forward Error Correctionand Its Interplay with Transmission Impairments”, IEEEJournal of Selected Topics in Quantum Electronics, Vol. 12,2006, pp. 544-554.

[8] W. Grover, “Forward Error Correction In Dispersion-LimitedLightwave Systems”, IEEE Journal of LightwaveTechnology, Vol. 6, No. 5, May 1988, pp. 643-654.

[9] S. Sistla, J. Gort, D. Lemay, “Error Correcting Codes forSTS-1”, In ECSA T1 contrib., June 1988, pp. 88-95.

[10] W. Grover, D. Moore, “Design and Characterization of anError-Correcting Code for the SONET STS-1 Tributary”,IEEE Transactions on Communications, Vol. 38, No. 4, Apr.1990, pp. 467-476.

[11] V. Paxal, P. Jourdain, G. Karam, “Error-Correction Codingfor High Speed Optical Transmission Systems Based on theSynchronous Digital Hierarchy”, European Transactions onTelecommunications, Vol. 4, No. 6, Nov./Dec. 1993,pp. 623-628.

[12] M. Tomizawa, Y. Yamabayshi, K. Murata, T. Ono,Y. Kobayashi, K. Hagimoto, “Forward Error CorrectingCodes in Synchronous Fiber Optic Transmission Systems”,IEEE Lightwave Technology Journal, Vol. 15, No. 1, Jan.1997, pp. 43-52.

[13] ITU-T Recommendation G.707/Y.1322, “Network NodeInterface for the Synchronous Digital Hierarchy (SDH)”, inSeries G of ITU-T recommendations, ITU, Oct. 2000.

[14] A. Tychopoulos and O. Koufopavlou, “In-Band CodingTechnique to Promptly Enhance SDH/SONET Fiber-OpticChannels with FEC Capabilities”, European Transactions onTelecommunications, Vol. 15, pp. 117-133, Apr. 2004.

[15] A. Tychopoulos, I. Papagiannakis, D. Klonidis, A. Tzanakaki,O. Koufopavlou, I. Tomkos, “Demonstration of a Low-CostInband FEC Scheme for STM-64 Transparent MetroNetworks”, in Proc. of the IEEE International Conference onTransparent Optical Networks (ICTON), Tu.A3.4 (invited),Nottingham, United Kingdom, June 18-22, 2006, pp. 87-90.

[16] A. Tychopoulos, I. Papagiannakis, D. Klonidis, A. Tzanakaki,J. Kikidis, O. Koufopavlou and I. Tomkos, “A Low-CostInband FEC Scheme for SONET/SDH Optical MetroNetworks”, IEEE Photonic Technology Letters, Vol. 18, Jan.1997, pp. 2581-2583.

[17] A. Tychopoulos, O. Koufopavlou, “Optimization of theFOCUS Inband FEC Architecture for 10Gb/s SDH/SONETOptical Communication Channels”, in Proc. of the Design,Automation and Test in Europe (DATE) Conf., 11.2, NiceFrance, April 16-20, 2007.

[18] A. Tychopoulos, P. Zakynthinos, O. Koufopavlou and H.Avramopoulos, “Employing Concatenated-FEC to MitigatePolarization Sensitivity in All optical WavelengthConversion”, in Proc. of the 6th Symposium onCommunication Systems, Networks and Digital SignalProcessing (CSNDSP), Graz, Austria, July 23-25, 2008,pp. 345-348.

[19] ITU-T Recommendation G.975. “Forward Error Correctionfor Submarine Systems”, in Series G of ITU-Trecommendations, ITU, 2000.

[20] A. Poustie, “SOA-based All-Optical Processing”, invitedtutorial OWF1, OFC2007, Anaheim, USA, 2007.

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Document for 300-pin 10Gb Transponder”, edition 1, Apr.16, 2001.

[22] OIF Spec. SFI-4 (OC-192 SerDes-Framer Interface),“Proposal for a Common Electrical Interface betweenSONET Framer and Serializer-Deserializer Parts for OC-192Interfaces”, Physical and Link Layer Working Group,Implementation Agreement rev. 1.0, OIF, Sep. 26, 2000.

[23] ITU-T Recommendation G.783, “Characteristics ofSynchronous Digital Hierarchy (SDH) Equipment FunctionalBlocks”, in Series G of ITU-T recommendations, ITU, Mar.2006.

[24] ITU-T Recommendation G.709, “Interfaces for the OpticalTransport Network”, in Series G of ITU-T recommendations,ITU, Mar. 2003.

[25] G. D. Forney, Jr., “Concatenated Codes&#8221, MIT- Technical Report 440, Cambridge, Massachusetts, Dec.1965

BiographiesAfxendios Tychopoulos received the Diploma of ElectricalEngineering in 2000 from the University of Patras, Greece.From 1999 till 2002, he was at the design center of Intel Corp.in Patras (Greece), focusing on the design and prototyping ofhigh-speed fiber-optic networks. From 2003 till 2005, he wasat the RnD center of Intracom Telecommunications S.A inPeania (Greece), focusing on the design and prototyping ofhigh-speed wireless microwave networks. He is currentlypursuing a PhD degree at the Department of Computer andElectrical Engineering, University of Patras, Greece. His

research interests include SDH/SONET networks, error-correcting codes and rapid-prototyping.Panagiotis Zakynthinos received the Diploma of ComputerEngineering and Informatics department from University ofPatras, Greece, with specialization in telecommunicationnetworks in 2005. He is currently working towards the PhDdegree at the Photonics Communications Research Laboratory,School of Electrical and Computer Engineering, NationalTechnical University of Athens. His current research interestsinclude high capacity optical networks, and design anddevelopment of optical processing systems/subsystems.Hercules Avramopoulos is currently heading the PhotonicsCommunications Research Laboratory of the NationalTechnical University of Athens (NTUA). He received his PhDdegree from Imperial College, London University, UK, in 1989and from 1989 to 1993 he worked for AT&T Bell Laboratories,Holmdel, NJ, USA. His primary research interest is thedemonstration and application of novel concepts in photonictechnologies for telecommunications.Odysseas Koufopavlou received the Diploma of ElectricalEngineering in 1983 and a PhD degree in ElectricalEngineering in 1990, both from University of Patras, Greece.From 1990 to 1994 he was at the IBM Thomas J.WatsonResearch Center, Yorktown Heights, NY, USA. He is currentlyan Associate Professor with the Department of Electrical andComputer Engineering, University of Patras. His researchinterests include VLSI, low power design, VLSI cryptosystems, and high performance communication subsystemsarchitecture and implementation. Dr. Koufopavlou haspublished more than 100 technical papers and received patentsand inventions in these areas.

Documents

INBAND-FEC AS A LOW-COST PERFORMANCE ......INBAND-FEC AS A LOW-COST PERFORMANCE UPGRADE TO ALREADY-DEPLOYED SDH/SONET OPTICAL COMMUNICATION CHANNELS A. Tychopoulos 1, *, P. Zakynthinos