Materials Science and Engineering A304–306 (2001) 914–917

In situ interface characterization of silicon surface in fluoride media

B.K. Patel, S.N. Sahu∗Institute of Physics, Sachivalaya Marg, Bhubaneswar 751005, India

Abstract

The porous Si/HF-electrolyte junction has been studied by capacitance (C)–voltage (V) and current (I)–voltage (V) measurements. Theobserved current under forward bias shows an exponential increase like a Schottky diode with two oscillations around 1.0 and 2.4 V(SCE), respectively, whereas the reverse bias current shows negligible contribution. The low-frequency capacitance spectrum exhibits apeak structure in forward bias regime, which can be ascribed to the charge trapping/detrapping at Fermi level of porous Si under forwardbias. The potential and charge distribution for a p-semiconductor/electrolyte junction is discussed © 2001 Elsevier Science B.V. All rightsreserved.

Keywords:Silicon interface; Interface characterization; Fluoride media

1. Introduction

In recent years, the characterization of Si/HF-electrolytejunction [1–10] has drawn a renewed interest both from ex-perimental [11–17] and theoritical [18] understanding of thesystem and fabrication of practical devices [19–21]. In situcharacterization of the interface were characterized origi-nally by the electrochemist who attempted to study the sili-con dissolution and simultaneous oxide formation. Measur-ment of capacitanceC (V) with low frequency played a keyrole, and identified the presence of surface states in the sys-tem. In general p-Si/HF junction form a Schottky barrier[5] due to the electronic and electrochemical charge trans-fer between the Si and electrolyte. Searson and Zhang [8]reported about the growth of an oxide layer along with thesilicon dissolution under forward bias. According to them,electropolishing occurs with complete formation of oxidelayer and the transition region is characterised by a defectiveoxide. Simillarly Ozanam and his group [1] studied the in-terface through impedance measurement and have observedthe high-frequency loop in impedance spectra ascribed tothe dielectric response of the oxide layer formed at the in-terface during silicon dissolution whereas the low-frequencycapacitive loop suggested the presence of surface state asreported by other groups [8,22–25].

In this article, we considered general charge and poten-tial distribution at p-semiconductor/electrolyte interface andstudied the in situI (V) andC (V) characteristics.

∗ Corresponding author. Fax:+91-674-581142.E-mail address:sahu@iopb.stpbh.soft.net (S.N. Sahu).

2. Experimental

P-type (10−2� cm) silicon with (1 0 0) orientation werecleaned by standard procedure and the back side of thewafers were coated with evaporated aluminium in or-der to provide an ohmic electrical back contact. Then,non-anodized parts of wafers were covered first by quick fixand then an acid-proof wax. The solution was prepared byadding ethanol in to 49% HF to the desired concentration.The experiments were conducted in the dark and at roomtemperature, about 22◦C. The electrode potential was con-trolled with an EG&G PAR Model 273 potentiostat and thecurrent was plotted with anX-Y recorder. For capacitancemeasurements, variable LCR meter HP4284A was used inconjuction with the POTENTIOSTAT. The pertubating sig-nal was a sine wave of 50 mV rms amplitude. The simplestcell which we used to anodize silicon is shown in Fig. 1where silicon was shown as an anode. The cathode is madeof platinum. The cell body and stirrer itself is in generalmade of highly acid-resistance polymer such as Teflon.

3. Result and discussion

3.1. Potential distribution

The charge and potential distribution at the semi-conductor–electrolyte interface is shown in Fig. 2 whichdepicts a symmetry with interface surfaces oppositelycharged. Underneath the surface there exist space-chargelayers extending into the neutral regions of both the phasesas schematically shown in Fig. 2. In this example (Fig. 2)

0921-5093/01/$ – see front matter © 2001 Elsevier Science B.V. All rights reserved.PII: S0921-5093(00)01645-2

B.K. Patel, S.N. Sahu / Materials Science and Engineering A304–306 (2001) 914–917 915

Fig. 1. Schematic of electrochemical cell.

the charge in the surface states are assumed to be negative.Since their density is small, they do not influence the poten-tial distribution. Accordingly, the Galvani potential consistsof three regions: the potential,Usc across the space chargelayer within the semiconductor, the potential,Ug acrossthe Gouy layer within the electrolyte and the potential,Uhacross the compact double layer (Helmholtz layer) given

Fig. 2. Charge and potential distribution at the p-Si/electrolyte interface.Usc: potential across the space charge;Uga: Galvani potential;Uh: potentialacross the Helmholtz layer;Ug: potential across the Gouy layer.X is thedistance from the interface.

as [26]

Uga = Usc + Ug + Uh (1)

Any variation of the Galvani potential,1Uga can be detectedby determining the change of the electrode potential,1Ue[3]

1Ue = 1Uga = 1Usc +1Ug +1Uh (2)

3.2. Current–voltage analysis

When the p-Si is anodically biased, porous Si (PS) for-mation is observed as long as the reaction is limited by thecharge supply of the electrode and not by the ionic diffu-sion in the electrolyte and this condition is fulfilled by ad-justing the HF concentration. Minority carriers are alwaysnecessary for the dissolution of Si which can be generatedby the illumination of light for n-type Si and for the p-typeSi it is generated by the breakdown mechanism [17]. Butin case of the highly doped p-Si/HF-electrolyte system thespace charge width formed in p-Si electrode is very smallsuch that the charge transfer occur via tunneling of electronsor holes. This effect will also occur for highly doped n-typesubstrate. Since we have used a highly doped p-type Si cur-rent flow in p-Si/HF-electrolyte system is expected to occurvia a tunneling mechanism.

Fig. 3 shows the in situI–V characteristic of p-Si/HF-electrolyte interface under bias in the range 0.5–3.5 V (SCE).The characteristic depicts a normal forward biased Schottkydiode [16] behavior with some exceptions, viz. two currentmaxima around 1.0 and 2.4 V (SCE), respectively whichneed explanation. A small cathodic current in the range1.0–0.0 V (SCE) suggests to be due to reverse bias Schottkyjunction. However, the magnitude of current is neverthelesssmall which can be accounted to be due to reduction of H+ion [16] and the presence of native oxide of silicon. With asmall increasing forward bias an anodic current flows acrossthe junction thus giving the first current maximum around1.0 V (SCE). Increasing the forward bias further, again thecurrent increases exponentially (dashed line) and gives asecond current maximum around 2.4 V (SCE). Note that thecurrent in between the two maxima increases exponentiallyin contrast to the observed current in case Ozanam et al.[1] and Vanmaekelbergh and Searson [2] who observed a

Fig. 3. I–V characteristics of p-Si/electrolyte junction. The dotted linerepresent the exponential growth contribution from Schottky barrier.

916 B.K. Patel, S.N. Sahu / Materials Science and Engineering A304–306 (2001) 914–917

constant current which they ascribe to the growth of an ox-ide layer. The oxide layer as described in [1] and [2] is ex-pected to be a thicker one. In our case, the oxide thicknessappears to be small and the p-Si is heavily doped(nd '1019 cm−3) compared to Vanmaekelbergh and Searson [2](nd ' 1015 cm−3). Higher nd value is expected to yieldhigher magnitude of anodic current. The overall feature canbe treated as a forward biased Schottky current and addedto that of an extra current contribution from Butler–Volmerrate equation [16], where the two current peaks are as ifadded and the anodic current is controlled by the supply ofmajority carriers to the surface.

3.3. Theoretical interpetation of C(ss)

Charges on the semiconductor side of the interface mustnot only be distributed within the space charge region butalso exist in surface state. There are energy states at the sur-face located within the forbidden gap as shown in Fig. 4(a)and (b). They can be formed by adsorption of foreign speciesor simply by interruption of lattice periodicity at the inter-face. However, we believe the surface state are generateddue to the growth of an oxide layer, as no surface state con-tribution is seen in the reverse bias. Whether these energylevelsEssi occupied by electron or hole depends also on therelative position of the Fermi level,EF of porous silicon atthe Si/SiOx interface. A variation of the band bending maylead to a change of occupation of the surface state.

Fig. 4. (a) and (b): Energy band scheme of porous Si/electrolyte interfaceunder forward biasψs is the surface potential assigned with respect tointrinsic Fermi level,EFi . (a) ψs > 0 correspond to weak accumulationand (b) strong accumulationψs > 0; Edss1 andEdss2 are two interfacedonar states;EC, EV and EF are conduction band edge, valance bandedge and Fermi level of semiconductor;EF,el is pseudo Fermi level ofelectrolyte andδ is oxide thickness. The parameterdnss1 anddnss1 densityof surface state of state 1 and 2, respectively; (c) is theC–V characteristicof p-Si/electrolyte junction at 0.5 kHz. Two capacitance peaks are comingaround 1.0 and 2.4 V (SCE), respectively.

Since surface charges exist in the surface states, a variationof the potential, across the space charge may lead to a changeof charge in surface stateqssand to an additional capacitancedefined by [27]

C(ss) = − dqss

d1Vs=

∑i=1,2

dCssi (3)

where

qss = (e0)dn+ssi (4)

anddn+ssi the ionized surface state can be represented by

dn+ssi = dnssi

[1+ dgssi exp

(EF − dEssi + e01Vs

kT

)]−1

(5)

wherei denotes the states 1 and 2.1V s = V a − V FB andVa is the potential applied to p-Si electrode. Other quantitiesVa, VFB, q anddgssi are, respectively the applied potential,flat band potential, electronic charge and degeneracy factorfor statedEssi . The minus sign in Eq. (3) accounts for theinversion in sign of1Vs and qss. Upon application of avoltage, the surface state position as well as the band edgeswill change whereasEF will remain fixed. Relation (3) andrelation (5) clearly suggests that with the change of1Vs,the effective energy level of surface state will change andwhen just cross overEF, one would expect the capacitancemaximaCdss1andCdss2corresponding to two surface statesi = 1 andi = 2 as shown in Fig. 4(a) and (b).

3.4. Capacitance–voltage (C–V) analysis

Shown in Fig. 4(c) is theC–Vcharacteristic at 0.5 kHz ofa p-Si/HF-electrolyte interface taken at 300 K in dark. Twocapacitance maxima around 1.0 and 2.4 V (SCE), respec-tively are clearly seen. The region around−1.0 to −0.5 V(SCE) is the capacitance contribution from the inversionlayer in reverse bias condition whereψs > 0. As the bias isincreased to a positive value, the depletion layer (not resolv-able) contribute to the capacitance and a fiat band situationatψs = 0 is attained. Increasing forward bias, increases theoxide thickness shown in Fig. 4(a) and (b). Further increas-ing the forward bias accumulation layer contribute to thecapacitance (ψs < 0) and thedEss1, state also move up dueto the band bending of the energy bands. WhendEss1 justcross overEF at 1.0 V (SCE) charge trapping/detrapping oc-curs and the first capacitance maximum is observed. Furtherincreasing the forward bias for a value whenψs < 0 (strongaccumulation region Fig. 4(b)), thedEss2 state cross overEF and a second charge trapping/detrapping occurs whichgive rise to the second capacitance maximum around 2.4 V(SCE). A similar two capacitance maxima have been ob-served for n-Si/HF-electrolyte interface [3]. However, thepositioning of the two peaks and the voltage difference be-tween them in the present study are relatively large com-pared to [3]. Such large values are expected as the applied

B.K. Patel, S.N. Sahu / Materials Science and Engineering A304–306 (2001) 914–917 917

potential is bound to be distributed across the porous siliconand the oxide layer (Vox) given by [28]

Va = Vox + ψs (6)

In fact, presence of high density of surface traps may injectminority carriers under high forward bias which diffuse tothe depletion layer,Cdl and contribute significantly to thejunction capacitance [29] at low frequency. On the otherhand, the contribution at higher frequency will be much lessand capacitance maxima is not expected. Hence, knowingthe peak capacitance, Fig. 4(c) the surface state densitiesdnss1, anddnss2can be estimated using relation (6) and foundto be 3.2×1011 and 2.4×1011 cm−2, correspondinglydEss1anddEss2, respectively. These values are comparable to thatdescribed in [3].

4. Conclusion

p-Si/HF-electrolyte interface have been characterised byin situ I–V and low-frequencyC–V studies. The observedtwo capacitance maxima were explained in terms of chargetrapping/detrapping of the surface state when it cross overthe Fermi level of the porous silicon.

Acknowledgements

Thanks are due to Prof. S.N. Behera, Institute of Physicsand Prof. S.C. Agrawal, IIT Kanpur for their helpful discus-sion and constant encouragement. Partial financial supportreceived from IFCPAR project no. 1508-4 is gratefully ac-knowledged.

References

[1] F. Ozanam, J.-N. Chazalviel, A. Radi, M. Etman, J. Electrochem.Soc. 139 (1992) 2491.

[2] D. Vanmaekelbergh, P.C. Serson, J. Electrochem. Soc. 141 (1994)697.

[3] G. Oskam, P.M. Hoffmann, P.C. Searson, Phys. Rev. Lett. 76 (1996)1521.

[4] N. Koshida, M. Nagasu, K. Echizenya, Y. Kiuchi, J. Electrochem.Soc. 133 (1986) 2283.

[5] I. Ronga, A. Bsiesy, F. Gaspard, R. Herino, M. Ligeon, F. Muller,A. Halimaoui, J. Electrochem. Soc. 138 (1991) 1403.

[6] H.O. Finklea (Ed.), Semiconductor Electrodes, Elsevier, Amsterdam,1998, Chapter 1, pp. 27–30.

[7] F. Muller, A. Halimaoui, J. Electrochem. Soc. 138 (1991) 1403.[8] P.C. Searson, X.C. Zhang, Electrochim. Acta 38 (1991) 499.[9] J.N. Chazalviel, J. Electrochem. Soc. 129 (1982) 963.

[10] M. Tomkiewicz, Electrochim. Acta 35 (1990) 1631.[11] N. Koyama, N. Koshida, J. Electrochem. Soc. 138 (1991) 254.[12] D. Xu, G. Guo, L. Gui, Y. Tang, B. Zhang, G. Qin, Electrochem.

Solid State Lett. 5 (1998) 227.[13] A.I. Belogorokhov, L.I. Belogoroklmova, A. Perez-Rodriguez, R.

Morante, S. Gavrilov, Appl. Phys. Lett. 78 (1998) 2766.[14] W. Cai, Y. Zhang, J. Jia, L. Zhang, Appl. Phys. Lett. 73 (1998)

2709.[15] C. Levy-Clement, A. Lagoubi, R. Tenne, M. Neumaun-Spallart,

Electrochem. Acta 37 (1992) 877.[16] R.L. Smith, S.D. Collins, Appl. Phys. Lett. 71 (1992) R1.[17] V. Lehman, U. Gosele, Appl. Phys. Lett. 58 (1991) 856.[18] G.C. John, V.A. Singh, Phys. Rep. 263 (1995).[19] A. Bisey, F. Muller, M. Ligeon, F. Gaspard, R. Herino, R. Romestain,

J.C. Vial, Phys. Rev. Lett. 71 (1993) 637.[20] R.T. Collins, P.M. Fauchet, M.A. Tischler, Phys. Today 50 (1997)

31.[21] K.D. Hirschman, L. Tsybeskov, S.P. Duttagupta, P.M. Fauchet, Nature

384 (1996) 338.[22] A. Venkateswara Rao, F. Ozanam, J-N. Chazalviel, J. Electrochem.

Soc. 138 (1966) 153.[23] M.J. Madon, B.H. Loo, K.W. Frese, S.R. Morrison, Surf. Sci. 108

(1981) 135.[24] R. Memming, G. Schwandt, J. Electrochem. Soc. 5 (1966) 97.[25] J.D. L’Ecuyer, J.P.G. Farr, in: D.N. Schmidt (Ed.), Fourth

International Symposium on Silicon-on-Insulator Techology andDevices, PV 90-6, The Electrochemical Society SoftboundProceedings Series, Pennington, NJ, 1990, p. 375.

[26] V.A. Myamlin, Y.V. Pleskov, Electrochemistry of Semiconductors,Plenum Press, New York, 1967.

[27] H. Gerischer, Semiconductor Electrochemistry, Academic Press, NewYork, Chapter 5, p. 473.

[28] S.M. Sze, Physics of Semiconductor Devices, Wiley, New York,1981.

[29] B.K. Patel, K.K. Nanda, S.N. Sahu, J. Appl. Phys. 85 (1999) 3666.