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In-memory Multi-valued Associative ProcessorMira Hout, Mohammed E. Fouda, Rouwaida Kanj, and Ahmed M. Eltawil

Abstract—In-memory associative processor architectures areoffered as a great candidate to overcome memory-wall bottleneckand to enable vector/parallel arithmetic operations. In thispaper, we extend the functionality of the associative processorto multi-valued arithmetic. To allow for in-memory computeimplementation of arithmetic or logic functions, we proposea structured methodology enabling the automatic generationof the corresponding look-up tables (LUTs). We propose twoapproaches to build the LUTs: a first approach that formalizesthe intuition behind LUT pass ordering and a more optimizedapproach that reduces the number of required write cycles. Todemonstrate these methodologies, we present a novel ternaryassociative processor (TAP) architecture that is employed toimplement efficient ternary vector in-place addition. A SPICE-MATLAB co-simulator is implemented to test the functionalityof the TAP and to evaluate the performance of the proposed APternary in-place adder implementations in terms of energy, delay,and area. Results show that compared to the binary AP adder,the ternary AP adder results in a 12.25% and 6.2% reduction inenergy and area, respectively. The ternary AP also demonstrates a52.64% reduction in energy and a delay that is up to 9.5x smallerwhen compared to a state-of-art ternary carry-lookahead adder.

Index Terms—Associative Processor, Multi-valued Logic,Ternary, Adder, In-memory Computing, Compute-in-Memory.

I. INTRODUCTION

MANY applications in Machine Learning, big data anal-ysis, search engines, and network routing require mas-

sive parallelism. As the amount of data to be analyzed con-tinues to grow, power dissipation and data transfer betweenmemory and processing units have limited the scalability ofparallel architectures [1].

This has led researchers to consider Associative Processors(APs) as in-memory platforms for carrying-out massivelyparallel computations inside the memory without the need tomove the data [2]. The ability of APs to unify data processingand data storage has drastically decreased compute energyand latency cost. An AP constitutes of an array of ContentAddressable Memories (CAMs) which are storage devices thatallow concurrent access to all data rows. A CAM searches for astored word based on an inputted search key. The AP improvesits functionality by allowing parallel writing into masked bitsof the matching CAM rows [3].

While binary CAMs perform exact-match searches for‘0’ and ‘1’ bits, a more powerful ternary CAM (TCAM)can search a third “don’t care” value, allowing for very

M. Hout and R. Kanj are with ECE Dept., American University of Beirut,Lebanon, 1107 202

M. Fouda is with Center for Embedded & Cyber-physical Systems, Uni-versity of California-Irvine, Irvine, CA, USA 92697-2625, with EngineeringMathematics and Physics Dept., Faculty of Engineering, Fayoum University,Egypt and with Nanoelectronics Integrated Systems Center (NISC), NileUniversity, Giza, Egypt. (Email:foudam@uci.edu)

A. Eltawil is with King Abdullah University of Science and Technology(KAUST), Thuwal 23955, Saudi Arabia and with Center for Embedded &Cyber-physical Systems, University of California-Irvine, Irvine, CA, USA92697-2625

Manuscript received xxx, xxx; revised xxxx, xxx.

flexible pattern matching between search keys and storedvalues [3]. Considering its promising applications potential,different implementations for the TCAM have been proposedincluding SRAM-based TCAM [4], [5]. However, they werenot widely adopted due to their low density and nonvolatility[6]. Nowadays, emerging devices such as resistive memo-ries have relaxed these constraints, leading to the revival ofthe TCAM-based AP approach in the research community[7]. New TCAM implementations based on resistive randomaccess memory (ReRAM) have been proposed [8], [9] toreduce power and improve area density in comparison tothe conventional complementary metal-oxide semiconductor(CMOS) solutions.

Memristive-based TCAM (MTCAM) designs have beenproposed to build 1D and 2D in-memory computing architec-tures based on AP [6], [10]. The AP architecture presented in[6] was designed to perform in-memory compute in the contextof the binary full adder. It relies on a look-up table (LUT)-based 1-bit addition that employs four compare and writeoperations applied in parallel to the different rows, resultingin significant runtime savings.

Recently, ternary logic has gained interest among the circuitdesign community for its ability to increase power efficiencyand reduce the complexity of arithmetic circuit designs. How-ever, the implementation of ternary logic circuits requires theuse of devices with multiple threshold voltages which is diffi-cult to accomplish with the current CMOS technology withreasonable devices’ area and latency [11], [12]. Therefore,recent studies have shed light on alternative devices for thedesign of ternary arithmetic circuits such as carbon nanotubefield-effect transistors (CNTFETs) [11]–[13] and memristors[14], [15].

In order to carry-out ternary addition, different approacheswere adopted in the literature. In [11], authors included aternary-to-binary decoder stage for the inputs, and the additionwas performed using binary logic gates before converting backthe outputs to ternary logic. In [13], the authors expressedthe arithmetic function using a K-Map, and they used theobtained equations to determine the logic gates needed for theCNTFET-based implementation. In [14], the authors custom-designed the desired arithmetic function and implemented itusing ternary logic gates composed of both memristors andCNTFETs.

In this paper, we propose a scalable CAM cell design andmethodology for purposes of multi-valued logic AP applica-tions. To enable the implementation of in-memory computeoperations, we propose two novel algorithms that guide theautomatic generation of the LUT for in-place multi-valuedarithmetic or logic functions. The first relies on a depth-firstsearch exploration of the state diagram obtained from thefunction’s truth table, and the second capitalizes on commonoutputs to reduce the number of required write cycles. Theproposed methodology is universal and can be employed fordifferent logic or arithmetic functions such as NOR, XOR,

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AND, multiplication, addition and subtraction. To illustrate,we present a novel implementation of a ternary AP (TAP)architecture based on a novel quaternary CAM (QCAM)design. We demonstrate the proposed design in the context ofa LUT-based ternary full adder application. Specifically, ourcontributions are as follows:

1) We propose a “nTnR” CAM cell for multi-valued AP(MvAP) arithmetic and logic operations. To exemplifyour design, we present a TAP architecture using a “3T3R”QCAM cell as a building block.

2) We propose a scalable cycle-free state diagram mappingof the multi-valued arithmetic or logic function’s truthtable. The state diagram forms the core data structureto implement the proposed algorithms. These algorithmsbuild on the states’ connectivity along with other relevantattributes to structurally traverse the state diagram for asystematic generation of the LUTs.

3) A first approach that relies on depth-first search (DFS)parsing of the state diagram to determine the order of thepasses.

4) A second optimized approach that exploits common writeactions to reduce the number of required write cycles.It relies on breadth-first search (BFS) parsing and agrouping heuristic for the different state diagram nodes.

5) We test the algorithms for implementing a LUT-basedternary full adder (TFA) relying on a TAP architecture.We evaluate the energy, delay and area efficiency of theternary adder implementations using the first and secondapproaches and compare them against each other as wellas to the AP binary adder and other ternary full adderimplementations.

The rest of this paper is organized as follows. Section IIproposes the multi-valued AP architecture and discusses theCAM implementation and operation. Then, an illustrative ex-ample of ternary AP is discussed in Section III. The extendedfunctional operations from binary AP is proposed utilizinga novel state diagram interpretation in Section IV, and anoptimized version is introduced in Section V. Experimentationresults and analysis are performed on a novel ternary AP fulladder implementation in Section VI. Finally, the conclusionof this work is given.

II. PROPOSED MVAP ARCHITECTURE

Traditionally, digital arithmetic computation is performedusing two-valued logic: ‘0’ or ‘1’. However, in modern dig-ital design, researchers are increasingly looking into multi-valued logic (MVL) as a way to replace the classical binarycharacterization of variables. MVL, notably ternary logic,constitutes a promising alternative to the traditional binarylogic [16] as it provides multiple advantages such as reducedinterconnects, smaller chip area, higher operating speeds andless power consumption [17]. The voltage levels for multi-valued logic of radix-n are n levels spanning from 0 to VDD.Hence, the ith logic value is realized with i ∗ VDD/(n − 1)where i ∈ [0, n − 1]. For instance, ternary logic systemuses 0, 1, 2 logic values with 0, VDD/2, VDD voltagelevels, respectively. This representation is referred to as theunbalanced representation unlike the balanced which uses−1, 0, 1 logic values and is realized with −VDD, 0, VDD

TABLE IMAPPING BETWEEN THE NIT VALUE STORED IN THE MVCAM CELL AND

THE CORRESPONDING n MEMRISTOR STATES.

Logicvalue

Stored stateMn−1 Mn−2 · · · M1 M0

x H H · · · H H0 H H · · · H L1 H H · · · L H...

......

. . ....

...n− 2 H L · · · H Hn− 1 L H · · · H H

voltage levels [18]. In this paper, we focus on the unbalancedternary logic system.

Fig. 1 presents an illustration of the MvAP architecturecomprised of a multi-valued CAM (MvCAM) array, a con-troller, a decoder and a set of Key, Mask and Tag registers. AMvCAM array consists of multiple rows containing MvCAMcells where n-valued digits (nits) are stored. The followingsections present the proposed implementation of the differentcomponents.

A. MvCAM Cell

A compact design of a memristor-based MvCAM cell withn transistors and n memristors (“nTnR”) is presented as anatural extension to the “2T2R” TCAM cell designated forbinary AP applications [19]. The proposed design is illustratedin the context of a multi-valued AP in Fig. 1. The memristorsin the cell function as storage elements whose states determinethe stored nit value. The stored value is obtained by settingonly one of the memristors to the low resistance state RLRS

and maintaining the other (n − 1) memristors in the highresistance state RHRS , as indicated in Table I. Without loss ofgenerality, the location of the single RLRS among the (n−1)remaining RHRS memristors determines the logic state storedin the cell. Specifically, to store nit value i, memristor Mi isthe one set to RLRS . A “don’t care” state is represented byall memristors set to RHRS . To test the functionality of the“nTnR” cell, the matchline (ML) is initially precharged high.The signal vector (Sn−1, Sn−2 ... S1, S0) illustrated in Fig.1 is then sent to check for a specific stored nit value in thecell. When searching for nit value i, signal Si is set to lowwhile the other signals are set to high. The search outcomeresults in a match only when memristor Mi is in the RLRS andthe other memristors are in the RHRS . Otherwise, the searchoutcome results in a mismatch. In the case of a match, thevoltage of the ML discharges slowly and is hence preservedhigh, whereas in the case of a mismatch, the ML dischargesquickly to ground.

B. Search Key n-ary Decoder

The n-ary decoder allows mapping the key-mask pair tothe signal vector (Sn−1, Sn−2 ... S1, S0). Table II presents thetruth table for the n-ary decoder. The inputs to the decoderare a binary mask and nit-valued key. In the signal outputsof the decoder, the place of the signal set to zero is equal tothe search key value. Specifically, to search for logic value j,the signal Sj is the one set to zero. It is worth noting thatthe decoder logic is inverting since the target signal is set tolow whereas all other signals are set to high. When the key

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Mn-1 Mn-2

Tn-1 Tn-2

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T1 T0

...

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S[n-1:0]S[n-1:0]

Fig. 1. An illustration of the MvAP architecture highlighting the proposed MvCAM cell.

is masked, i.e., the mask bit is a zero, all decoded signals areset to zero. One simple and generic way to implement suchdecoder is with simple successive approximation ADC withmodified operation. But, in the case of the ternary decoder, itwill be shown in the next section that it can be realized withsome ternary logic circuits.

TABLE IIMAPPING BETWEEN THE KEY-MASK PAIR AND THE CORRESPONDING

DECODED SIGNALS SENT TO THE MVCAM CELL.

Mask Key Decoded signalsSn−1 Sn−2 · · · S1 S0

0 x 0 0 · · · 0 0n− 1 0 n− 1 n− 1 · · · n− 1 0n− 1 1 n− 1 n− 1 · · · 0 n− 1

......

......

. . ....

...n− 1 n− 2 n− 1 0 · · · n− 1 n− 1n− 1 n− 1 0 n− 1 · · · n− 1 n− 1

C. MvCAM Array

A MvCAM array consists of several MvCAM rows. AMvCAM row contains several “nTnR” cells along with asensing circuit to distinguish between the full match and themismatch states. A full match state is obtained when all cells inthe row match the searched nits, while a mismatch is obtainedwhen at least one cell in the row does not contain the searchednit. An essential requirement for the array is to concurrentlycompare the stored data in all rows with an inputted key andmask pair. For purposes of in-memory compute, we overwritethe activated columns of the matched rows with new data. Thekey determines the nit value to be searched for, while the maskdetermines the columns of interest to be separately activatedduring each of the compare and write operations. The nit keyand its binary mask are inputted to a decoder that generates

the corresponding signal vector (Sn−1, Sn−2 ... S1, S0), asindicated in Table II.

1) Compare: The compare operation includes a prechargeand an evaluate phase (see Fig. 2). During precharge, thecapacitor is charged high, then a masked key is applied to thearray in the evaluate phase. This leads the capacitor of eachMvCAM row of cells to discharge through a resistor whosevalue is equal to the equivalent resistance of the correspondingrow. In the case of a full match (fm), the capacitor retains mostof its charges due to the presence of only high-resistance paths.In the case of one mismatching cell per row (1mm) or more(2mm, 3mm, etc.), the capacitor discharges quickly to groundthrough one, two or more low-resistance paths.

2) Write: After the compare operation, the sense amplifierconnected to the output of the matching circuit senses thevoltage across the capacitor and generates correspondencesbetween a row match and logic ‘1’, and a row mismatch andlogic ‘0’. Hence, all matching rows are “tagged”, meaningtheir Tag field is set to logic ‘1’. For example, in Fig. 1, cellsin the first row match the masked key and the row is tagged,whereas cells in the last row do not match the masked key.We note that the sensing amplifier is followed by a latch thatholds the Tag bit throughout the write action. The write enablesignal is asserted to overwrite the new masked columns of thetagged MvCAM rows with new data. Each write action foran “nTnR” cell triggers one memristor set and one memristorreset, except for writing to (from) a “don’t care” state whichonly requires one reset (set). This is attributed to the fact thateach stored nit is associated with a distinct memristor set toRLRS , except for the “don’t care” value in which no memristoris set to RLRS .

Finally, we note that in an optimized architecture, theprecharge phase can be performed in parallel with the writeoperation to reduce the combined compare and write cycletime. As such, a transmission gate powered by the write

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Fig. 2. Sketch showing consecutive compare and write operations and theresulting memristor state changes for a “3T3R” CAM cell, assuming thecompare operation results in a match.

enable signal is used to relay to the ML the proper pro-gramming voltage to program the memristors, while anotherpass gate powered by the inverse of the write enable isolatesthe precharge capacitor from the programming voltage, asillustrated in Fig. 1. The ML programming voltage is set tohigh during reset, and to low during set. The “nTnR” virtualground is set to zero during reset, and pulled high during set.

III. ILLUSTRATIVE TAP ARCHITECTURE

In [20], the author analyzed the number system to findthe best radix in terms of the economical perspective (i.e.,number of computations). The optimal radix is found to be thenatural number e = 2.718 [21]. So, the ternary logic systemis adopted as the best number system since the integer 3 isthe nearest to e. Herein, we illustrate the MvAP architecturewith a ternary AP (TAP) relying on a “3T3R” quaternaryCAM (QCAM) cell. The “3T3R” cell is built using threetransistors and three memristors and stores the ternary logicvalues ‘0’, ‘1’ and ‘2’ in addition to a “don’t care” value.Trits are stored in the form of one memristor set to RLRS andtwo memristors set to RHRS . For example, the combination(M2, M1, M0) = (RHRS , RHRS , RLRS) indicates a logic‘0’ since M0 is the memristor which is set to RLRS as shownin Table III. For the same stored value, when the decodedsignal triplet sent is (S2, S1, S0) = (2, 2, 0), ML dischargesvery slowly since only high-resistance paths will connectML to ground either through RHRS or Roff , thus resultingin a match. For all other decoded signal combinations, MLdischarges quickly to ground through a low-resistance path,thus resulting in a mismatch.

For the TAP, as is the case for the MvAP, the Key registercontains the ternary values to be searched for inside theQCAM array, while the Mask register indicates which columnor columns of the array are activated during comparisonor writing. Upon compare, each key-mask pair generates adecoded signal triplet in which only one of the signals is set tozero, while the others are set to VDD, i.e., logic value n−1 = 2for the case of ternary logic. For example, to search for logic‘0’, the decoded signal triplet is (S2, S1, S0) = (2, 2, 0) asshown in Fig. 3. Equations (1a), (1b) and (1c) represent thecorresponding logic functions for the signal values obtainedbased on the truth table of Fig. 3. The figure also presents thedecoder circuit for the case of ternary logic comprising positive

TABLE IIIDIFFERENT COMBINATIONS OF SEARCHED AND STORED DATA WHICH CANLEAD TO EITHER A MATCH OR A MISMATCH STATE. “H” AND “L” DONATE

RHRS AND RLRS , RESPECTIVELY.

Searched Data Stored Data

Mask Key Logicvalue M2 M1 M0 State

0 x x x x x Match2 0 0 H H L Match2 1 0 H H L Mismatch2 2 0 H H L Mismatch2 0 1 H L H Mismatch2 1 1 H L H Match2 2 1 H L H Mismatch2 0 2 L H H Mismatch2 1 2 L H H Mismatch2 2 2 L H H Match2 0 x H H H Match2 1 x H H H Match2 2 x H H H Match

Fig. 3. Ternary decoder; truth table (top) and circuit implementation (bottom).The inverters with ‘+’ sign and ‘−’ sign represent PTI and NTI, respectively.The rest of the gates are conventional binary gates

ternary inverters (PTIs), negative ternary inverters (NTIs) [22],binary AND, binary OR and binary inverter gates. The truthtables for the ternary inverters are depicted in Table IV [22].

S2 = Mask · PTI(Key) (1a)

S1 = Mask · (NTI(Key) + PTI(Key)) (1b)

S0 = Mask ·NTI(Key) (1c)

For purposes of in-memory compute, matching rows areoverwritten by new data. Each write operation of a ternarylogic value includes one memristor set and one memristorreset, except for writing to (from) a “don’t care” state whichonly requires one memristor reset (set).

To implement a specific ternary arithmetic function, weiterate through the LUT entries for 1-trit operation, and theprocess is repeated to perform multi-trit operations. For each1-trit operation, the Key register is set to the correspondingLUT input values and applied concurrently to all rows of the

TABLE IVTRUTH TABLE FOR THE STI, PTI AND NTI TERNARY INVERTERS.

x STI(x) PTI(x) NTI(x)0 2 2 21 1 2 02 0 0 0

5

TABLE VA WRITE EXAMPLE FOR THE TERNARY “3T3R” CELL. ‘X’, ‘R’ AND ‘S’

MEAN NO CHANGE, RESET AND SET, RESPECTIVELY.

A B Cin

Current state 0 1 2Current stored (M2, M1, M0) (H, H, L) (H, L, H) (L, H, H)Next state 0 0 1Next stored (M2, M1, M0) (H, H, L) (H, H, L) (H, L, H)Action (x, x, x) (x, R, S) (R, S, x)

array in the columns specified by the Mask register. Theserepresent the operand columns. Each key-mask pair is fedto a decoder that generates the signal triplet (S2, S1, S0).After the compare operation, the rows of the QCAM arraywill generate either a match or a mismatch. Then, the writeoperation is performed on the matching rows of the array.New data consisting of the LUT output for the correspondinginput replaces the stored value in the newly masked columnsof the array. Table V illustrates an example where trit Binitially takes on ternary value ‘1’ which is equivalent to initialmemristor states (M2, M1, M0) = (H, L, H). Assuming thatthe function’s LUT dictates that B should be overwrittenby ternary value ‘0’ post the compare operation, the finalmemristor states will be (M2, M1, M0) = (H, H, L). Assuch, for this example, M1 should be reset and M0 should beset, whereas M2 remains the same as illustrated in Fig. 2.

IV. AP OPERATION

A general-purpose AP enables the implementation of arith-metic functions such as addition, subtraction, multiplicationand division as well as logical operations by relying on thetruth tables of the desired function applied in a specific order.We refer to this as the look-up table based approach. Theprocess is performed digit-wise and is repeated for multi-digitoperations. The rows of the MvCAM array store the inputvectors. For in-place operation, the output is written back tosome or all of the input locations. All rows of the data array areprocessed in parallel. Each digit-wise operation is comprisedof consecutive compare and write steps.

1) Compare: For every pass of the LUT, a masked key takeson the input vector values of this pass (see Table VI forthe example of binary AP addition [6]). The masked keyis applied to all rows of the array and compared againstthe stored input data.

2) Write: A match for a row sets its Tag bit to a ‘1’, whilea mismatch for a row sets its Tag bit to a ‘0’. Taggedrows are overwritten by the corresponding output fromthe LUT consisting of a new masked key. For the exampleof the binary AP, the sum bit S and the carry-out bitCout are written back to the input locations B and Cin

respectively, keeping A untouched. The in-place write-back of the output dictates the order of the passes in theLUT. This is required to avoid mistakenly revisiting infuture passes rows that have already been overwritten, aswill be discussed later.

A. Proposed State Diagram for LUT Generation

The proper pass order for a given arithmetic function can beensured as follows. Consider that x appears in the truth tableof the function as both an input in one entry and an output in

some other entry, then the order of processing x as an inputmust satisfy one of the two properties below:

1) The pass in which x appears as an input must be testedbefore the pass in which x appears as an output.

2) x as an input results in ‘No action’, i.e., the output to beoverwritten is identical to the stored input. Such an inputhas no pass number because no action is needed, henceit will never be tested after the pass in which x appearsas an output. This implies that the order of the pass inwhich x appears as an output is independent of the passin which x appears as an input.

These properties ensure that the resulting passes are visitedcorrectly.

Herein, we propose a directed state diagram representationof the truth table of the arithmetic or logic function to beimplemented using AP. Our objective is to rely on this statediagram representation to identify the proper processing orderof the function’s truth table and, accordingly, generate its LUT.The elements of the state diagram can be best described asfollows.• Directed edge: application of the arithmetic function

under consideration.• State: stored input to be operated upon.• Next state: corresponding output as per the LUT.• noAction state: state that remains the same upon in-

place operation, that is, the LUT input is identical to itscorresponding LUT output.

Without loss of generality, Fig. 4 first illustrates the statediagram of the binary adder’s truth table. In this example,the edge corresponds to the binary add operation, the statecorresponds to the 1-bit input triplet (Ai, Bi, Cin) and thenext state corresponds to the output triplet (Ai, Si, Cout).Finally, the noAction state is the one pointing to itself,indicating that it remains the same upon in-place addition, thatis, (Ai, Si, Cout) = (Ai, Bi, Cin). The binary adder statediagram in Fig. 4 is also labeled with the LUT pass order [6].An analysis of the pass order shows that they were ordered toavoid erroneously performing multiple consecutive additionson the same entry. This translates in the state diagram to thefirst pass writing ‘110’ by ‘101’, and the second pass writing‘100’ by ‘110’. No other pass can overwrite these outputs oncetheir respective inputs are visited. On the other hand, if passes1 and 2 are exchanged, ‘100’ results in ‘110’ after the firstpass, which will be overwritten by ‘101’ after the second passas indicated by the directional flow of the state diagram. Sucha domino effect is not desired. Therefore, it is evident thatto construct the LUT for a generic arithmetic function, theorder of the passes must be determined through a structuredtraversal of the directed state diagram.

TABLE VILOOK-UP TABLE OF THE BINARY AP ADDER.

Input Output PassorderA B C A B C

0 0 0 0 0 0 No action0 0 1 0 1 0 30 1 0 0 1 0 No action0 1 1 0 0 1 41 0 0 1 1 0 21 0 1 1 0 1 No action1 1 0 1 0 1 11 1 1 1 1 1 No action

6

100 110

011 001

101

010

000

111

Level 0Level 1Level 2

Pass 1Pass 2

Pass 3Pass 4

Fig. 4. State diagram of the AP binary adder. The states store the values forthe triplets (A, B, Cin). The arrow represents the addition operation. Thepass order of Table VI are labeled.

B. Automated LUT GenerationHerein, we build upon our state diagram interpretation

of the truth table to guide the automatic development ofa general-purpose LUT. As we note from Fig. 4, the statediagram comprises of a collection of trees whose roots arenoAction states. We note that the input-output pairs areconnected through backward edges propagating to the roots.Our objective is to identify the proper order of passes forin-place operation so that no pass overwrites the outcome ofearlier ones. This can be guaranteed if and only if the followingholds for the state diagram.

1) The state diagram is a uni-directional graph with nocycles, i.e., no forward edges.

2) If the state diagram has cycles, then we should be ableto break these cycles by redirecting forward edges back-wards. If in the original state diagram input vector x =(x1, x2) has its output y = (x1, y2) creating a forwardedge, we search for an alternate output y′ = (y1, y2) thatforms a backward edge and breaks the cycle. y′ is a validoutput so long y2 remains unchanged since y2 representsthe output digit to be overwritten as per the LUT, whiley1 is a dummy extra written digit. Therefore, we need toinvoke a larger vector write post the compare operation.This will be illustrated in the following example.

For example, we implement the state diagram for the LUT-based ternary full adder (TFA) in the context of TAP. Fig. 5presents the state diagram of the TFA’s truth table. We performin-place ternary addition with inputs (A, B, Cin). The outputs(S, Cout) overwrite (B, Cin), while A is kept untouched. Inthe state diagram, if the input triplet (A, B, Cin) whose output(A, S, Cout) represents a forward edge forming a cycle, wesearch for an alternate output (y1, S, Cout) that forms abackward edge and breaks the cycle. We then invoke a 3-tritwrite post the compare operation instead of the standard 2-tritwrite. Specifically, as illustrated by the dashed red edge in Fig.5, a direct implementation of the in-place ternary addition statediagram results in one cycle: state ‘101’ leads to ‘120’ andstate ‘120’ leads back to ‘101’. To resolve this problem, weoverwrite the A trit value to a ‘0’ for the input ‘101’. Hence,input ‘101’ now results in ‘020’ as an output (see green edgein Fig. 5) and input ‘120’ results in ‘101’ as an output. Thisincurs a minor cost consisting of an extra trit to be written for

210

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Fig. 5. State diagram of AP ternary full adder. For each subtree, the passesare determined based on a depth-first search to enforce the priorities.

one of the passes. However, it eliminates the cycle and enablesa smooth implementation of the LUT-based approach for theTFA.

With a cycle-free state diagram, i.e., a backward propagationbased input-output relation (left to right), we devise that thepasses should progress to visit the trees of the state machinefrom right to left in a depth-first search (DFS) approach, start-ing from the root of each tree. Since the roots are noActionnodes, we do not assign pass numbers to them and, hence,do not include them in the ordering of the passes. Algorithm1 presented herein details the traversal scheme of the statediagram which ultimately determines the proper order of thepasses for in-place operation. Table VII presents the resultingLUT for the TFA after applying Algorithm 1.

Algorithm 1 Ordering of the passes for the LUT-based ternaryfull adder following the non-blocked approach.

1: Global pass number p = 02: Global LUT length L = length(LUT )3: for all Ti do3: BUILDLUT(Ti.root)4: end for5: return

procedure BUILDLUT(state j)1: if j.noAction == 0 then2: p+ +3: j.passNum = p4: end if5: for all v ∈ j.child do6: BUILDLUT(v)7: end for8: return

V. OPTIMIZED AP OPERATION

In the first approach, hereafter referred to as the non-blocked approach, similar to traditional AP operation, each

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TABLE VIILOOK-UP TABLE OF THE LUT-BASED TFA.

Input Output PassorderA B C A B C

0 0 0 0 0 0 No action0 0 1 0 1 0 10 0 2 0 2 0 210 1 0 0 1 0 No action0 1 1 0 2 0 100 1 2 0 0 1 20 2 0 0 2 0 No action0 2 1 0 0 1 30 2 2 0 1 1 111 0 0 1 1 0 151 0 1 0 2 0 121 0 2 1 0 1 161 1 0 1 2 0 141 1 1 1 0 1 171 1 2 1 1 1 181 2 0 1 0 1 131 2 1 1 1 1 191 2 2 1 2 1 202 0 0 2 2 0 82 0 1 2 0 1 No action2 0 2 2 1 1 52 1 0 2 0 1 92 1 1 2 1 1 No action2 1 2 2 2 1 42 2 0 2 1 1 72 2 1 2 2 1 No action2 2 2 2 0 2 6

pass comprises of a compare cycle followed by a write cycle.Often, for a given function, different input vectors result insimilar output vectors. For example, for the TFA, differentinput triplets (A, B, Cin) often result in similar output pairs(S, Cout). Since write cycles are much more expensive thancompare cycles, we can leverage this fact to devise a secondapproach that capitalizes on these common output vectors.As such, we propose a more optimized approach that targetsthe dual objective of determining the proper pass order andgrouping different input vectors that share the same outputvector. The proposed approach starts by processing comparecycles for the input vectors that have the same output vector,then the write action occurs once all input vectors of a group(or block) are visited, thereby improving the efficiency of theLUT-based approach. Hereafter, we refer to this as the blockedapproach.

In order to traverse the state diagram using the blockedapproach in such a way to determine the correct ordering ofthe passes, we adopt a breadth-first search (BFS)-like traversalof the nodes. Every time a new block is determined, the statediagram is dynamically updated to eliminate the most recentlychosen block nodes. Post each update, we group nodes to thesame block in terms of (a) children of the same node, and (b)other nodes at the same level sharing the same write action.Note that the set of nodes (b) may not have necessarily existedin the initial state diagram at the same level as set of nodes (a);however, dynamic updates of the state diagram as we constructthe LUT will enforce such conditions as we explain next.

To implement the algorithm for the automatic generation ofthe LUT using the blocked approach, we consider that eachnode in the state diagram represents an input or output vectordepending on whether the node is subject to or the result of anadd operation, respectively. Each node is also associated witha set of attributes detailed in Table VIII. One of the attributesis writeDim representing the dimension of the output vector

TABLE VIIISTATE ATTRIBUTES DEFINITIONS FOR THE BLOCKED AND NON-BLOCKED

ALGORITHMS.

Attribute Definition

noActionDetermines the type of the state:1 for a No Action state0 for an Action state

grpNum Specific write group of the statelevel State level as indicated in Fig. 5outV al ‘n-ary’-to-decimal conversion of the state vectorwriteDim Write-back dimension for the output vector of the state

parentPointer to the parent of the state which is accessible fromthe state through a backward edge

childPointer to the child of the state which is accessible fromthe state through a forward edge

passNum Pass order assigned to the state in the LUT

to be written when the node is regarded as an input state.Another attribute is the outV al array whose entries representthe ‘n-ary’-to-decimal value of the node’s write action when itis regarded as an output state. The need for the outV al array ofentries is explained as follows using the TFA as an example.For the TFA, when the node is the result of a 2-trit write-back, outV al(writeDim = 2) stores the ternary-to-decimalconversion of the written BC value. In the event of breakingcycles, we may add an extra dummy dimension and invoke a 3-trit write-back. The node that is regarded as the input of the op-eration will have writeDim = 3 and the node that is regardedas the output will have outV al(writeDim = 3) store thecorresponding equivalent decimal written ABC value. Notethat these values will be adjusted as explained later to avoidoverlap between the different decimal value conversions. Forexample, ABC = 000 will be mapped to a different numberthan BC = 00 as indicated in line 5 of Algorithm 2. Thiswill help in properly differentiating grouping of nodes thathave the same parent but different write action dimensions.Thus, nodes at the same level having the same writeDimand parent outV al share the same write action. As such, for aspecific node, we rely on its parent outV al(writeDim) valuefor the grouping and use it as a key component of the dynamicgrpLvl table that we rely on to guide the BFS-like traversalalgorithm. The table stores the number of nodes belonging tothe same group, i.e., having a similar write action, in eachlevel of the tree. The algorithm performs pass ordering andgrouping by updating the grpLvl table after each determinedblock to reflect updates to the state diagram. The algorithmproceeds as follows.

1) grpLvl initialization: To populate the initial grpLvltable, we apply Algorithm 2. Table IX represents the initialgrpLvl table for the TFA state diagram corresponding toFig. 5. For each state which is an Action state, we findl, the level of the node as indicated by Fig. 5, and g, theoutV al(writeDim) value of the node’s parent. For example,the group number g for node ‘101’ in the TFA state diagram ofFig. 5 is outV al(3) of its parent node ‘020’. This correspondsto the adjusted value 6 +

∑2i=0 3i = 19, where ‘6’ is the

ternary-to-decimal conversion of the vector ‘020’. Whereas thegroup number g for node ‘011’ is outV al(2) of its parent node‘020’, corresponding to the adjusted value 6 +

∑1i=0 3i = 10,

where ‘6’ is the ternary-to-decimal conversion of the vector‘20’. Accordingly, for each Action node in level l, an initialgroup number grpNum = g is assigned to the node, andthe entry corresponding to group g and level l in the grpLvl

8

TABLE IXgrpLvl TABLE INITIAL VALUES CORRESPONDING TO FIG. 5. IT INDICATES THAT GROUP 19 SHOULD BE PROCESSED FIRST SINCE IT IS THE ONLY GROUP

THAT HAS NO ENTRIES BEYOND LEVEL 1. NOTE THAT FOR THE TFA EXAMPLE, writeDim = 1 DOES NOT EXIST, AND THUS BY DEFAULT, NO NODESCAN HAVE grpNum = 1, 2, 3.

grpNumparent.outV al(1)+

∑0i=0 3

iparent.outV al(2) +

∑1i=0 3

i parent.outV al(3) +∑2

i=0 3i

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 191 0 0 0 0 1 0 1 2 0 2 1 0 0 0 0 0 0 0 12 0 0 0 0 5 1 0 1 0 1 0 0 0 0 0 0 0 0 03 0 0 0 0 0 0 0 2 0 1 0 0 0 0 0 0 0 0 0level

4 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0

table is incremented. Entries in the grpLvl table thus reflectthe number of nodes that share the same level and writeaction. For example, 5 nodes in Level 2 share the samewrite action BC = 013 = 110, having an adjusted value of1 +

∑1i=0 3i = 5. Thus, grpLvl[l = 2][g = 5] = 5 as shown

in Table IX.

Algorithm 2 Initializing the grpLvl table.Global pass number p = 0# Preparing Action states group table grpLvl

1: S is the set of all states ∀Ti2: for all states j ∈ S do3: if j.noAction == 0 then4: Level l = j.level5: Group number g = j.parent.outV al(writeDim) +∑writeDim−1

i=0 (ni)6: j.grpNum = g7: grpLvl[l][g] + +8: end if9: end for

10: G = max(g)11: L = max(l)# Use grpLvl table to build LUT for Action states12: BUILDLUTBLOCKED(S , grpLvl, G, L)13: return

2) Selecting the next block/group: At each iteration, ourobjective is to find the next target block/group gtgt for anadequate ordering of the passes in the LUT. We keep in mindthe following. Nodes that reside in Level 1 must be processedfirst from a pass ordering perspective (these qualify as nodeswhose parents have already been processed or whose parentsare noAction states). For purposes of grouping, we musttherefore look for groups that are fully or maximally residingin Level 1. In fact, we consider the following two cases asindicated in Algorithm 3.• In an ideal scenario, there exists a group that has nodes

belonging to the top level (Level 1) and no nodes in lowerlevels. This group would qualify as the next target groupgtgt.

• Another possible scenario is that no group has all itsnodes in the top level. In this case, we choose the groupthat has a maximum number of nodes in the top level asgtgt. However, we need to break this group since we canonly process states belonging to the top level. We splitgtgt by creating a new group for the remaining statespresent in lower levels. In this way, the total number ofgroups G is incremented, and gtgt will only contain nodesthat are in the top level.

To illustrate, initial grpLvl values shown in Table IX indicatethat Group 19, should be processed first. It is the only groupthat has entries in the top level and no entries in lower levels.Supplementary Tables 1, 2 and 3 present grpLvl tables for thefollowing three iterations, and at each iteration, we identify allpossible new gtgt groups. We continue until all the entries inthe grpLvl table at the top level become zero.

Algorithm 3 Finding the next block/group gtgt.procedure BUILDLUTBLOCKED(S, grpLvl, G, L)

1: topLevel = 12: while grpLvl[topLevel][.] 6= zeros(1, G) do3: found = −14: for g = 0→ G do5: cond1 = (grpLvl[topLevel][g] > 0)6: cond2 = (

∑Ll=2 grpLvl[l][g] == 0)

7: if cond1 and cond2 then8: gtgt = g9: UPDATELUT(gtgt)

10: found = 111: end if12: end for13: if found == −1 then14: [gtgt,maxgrpLvl] = max(grpLvl[topLevel][.])# Create new group for remaining states of gtgt in# lower levels15: G+ +16: for l = 2→ L do17: grpLvl[l][G] = grpLvl[l][gtgt]18: grpLvl[l][gtgt] = 019: end for20: for all states j do21: if (j.grpNum == gtgt) and (j.level > 1) then22: j.grpNum = G23: end if24: end for25: UPDATELUT(gtgt)26: end if27: end while28: return

3) Updating grpLvl and assigning pass numbers: We relyon Algorithm 4 to order the passes and build the LUT. In eachiteration, once the next gtgt is identified, we extract the nodeswith grpNum = gtgt from the state diagram and assign themas the next block to be processed in the LUT. We label themaccordingly with their corresponding pass number. Note thatwithin the gtgt group, passes can be numbered arbitrarily. Forexample, in Group 2 shown in Table X, triplet ‘102’ order

9

TABLE XLOOK-UP TABLE OF THE LUT-BASED TFA FOLLOWING THE BLOCKED

APPROACH.

Input Output Passorder

Groupnumber

WriteactionA B C A B C

1 0 1 0 2 0 1 1 W0201 0 2 1 0 1 2

2 W011 1 1 1 0 1 31 2 0 1 0 1 42 1 0 2 0 1 51 1 2 1 1 1 6

3 W111 2 1 1 1 1 72 0 2 2 1 1 82 2 0 2 1 1 90 0 2 0 2 0 10

4 W200 1 1 0 2 0 111 1 0 1 2 0 122 0 0 2 2 0 131 2 2 1 2 1 14 5 W212 1 2 2 2 1 150 0 1 0 1 0 16 6 W101 0 0 1 1 0 172 2 2 2 0 2 18 7 W020 1 2 0 0 1 19 8 W010 2 1 0 0 1 200 2 2 0 1 1 21 9 W110 0 0 0 0 0 No action0 1 0 0 1 0 No action0 2 0 0 2 0 No action2 0 1 2 0 1 No action2 1 1 2 1 1 No action2 2 1 2 2 1 No action

can be interchanged with any other triplet order from thesame group, say ‘120’. The children of the selected groupnodes are then elevated to Level 1 and their subtree nodesare elevated by one level as well. grpLvl table and the statediagram are updated to reflect the changes accordingly. Finally,we set the top level entry in the grpLvl table correspondingto gtgt to zero. Hence, as the state diagram is traversed andpass numbers are allocated to the nodes, entries in the grpLvltable will be updated, mimicking updates in the state diagram.This is exemplified by Supplementary Fig. 1, 2 and 3 and theircorresponding grpLvl Tables 1, 2 and 3. The resulting LUTfor the TFA following the blocked approach is shown in TableX.

Algorithm 4 Updating the grpLvl table and ordering thepasses of the LUT.procedure UPDATELUT(gtgt)

1: topLevel = 1# Generate pass number for states in the target group

2: for all states j do3: if j.grpNum == gtgt then4: p+ +5: j.passNum = p6: for all v ∈ tree whose root is j do7: grpLvl[v.level − 1][v.grpNum] + +8: grpLvl[v.level][v.grpNum]−−9: v.level −−

10: end for11: end if12: end for13: grpLvl[topLevel][gtgt] = 014: return

Circuits to Enable the Blocked Approach: We note thatthere is a minimal cost overhead for blocking to delay the writeaction until the end of the block. Our proposed solution is toadd to each row a D flip-flop clocked by the Tag bit. Prior toprocessing a block, write enable signals are discharged. Hence,as we traverse the LUT to process the passes of the block, amatch for a row will have its Tag bit toggle from ‘0’ to ‘1’,setting the write enable signal at the output of the flip-flop to a‘1’. At the end of each block, the rows for which the flip-flopoutputs are ‘1’ are overwritten. This ensures that all rows thathave matches within the block will be overwritten togetherby the same output. The flip-flop is reset after every block.Timewise, the flip-flop’s toggling time cost can be hidden,whereas storage wise, one extra flip-flop per row is needed.

VI. RESULTS AND ANALYSIS

In this section, we study the proposed ternary adder im-plementations (non-blocked and blocked) in terms of energy,delay and area, and we compare them against the binary APadder and other ternary adder implementations. First, we studythe characteristics of the “3T3R” cell. For our experimentalresults, we rely on 45nm predictive technology model [23] forour simulations. The transistor threshold voltage is Vt = 0.4V ,and VDD = 0.8V .

A. Design Space Exploration: QCAM Cell Dynamic Rangeand Energy Analysis

In our ternary AP adder design, a 1-trit addition involvesthe comparison of the key-mask pair with three stored tripletsof memristor states (M1, M2, M3), where each triplet corre-sponds to one of the trits Ai, Bi and Cin. The outcome ofthe comparison can result in a: full match (fm), one mismatch(1mm), two mismatches (2mm) or three mismatches (3mm).

For purposes of the analysis of the “3T3R” cell, we definethe dynamic range (DR) as the maximum voltage differencebetween the fm and the closest mismatch case which is1mm [24], [25], measured after 1ns of evaluation time of the(Sh, Sx, SL) signal triplet as indicated below.

DR = Vfm − V1mm (2)

where, Vfm and V1mm represent the ML voltages for the fmand 1mm states, respectively. Typically, for accurate sensingof the comparison outcome, we aim for a high dynamicrange. However, a high DR comes at the expense of increasedcompare energy consumption. To further assess this, we definefor purposes of the add operation the compare energies Efm,E1mm , E2mm, E3mm corresponding to the fm, 1mm, 2mmand 3mm states, respectively. We rely on HSPICE simulationsto study the dynamic range and compare energies for the“3T3R” cell in the context of the LUT-based ternary adder. Weassess these metrics for the following design space parametercombinations. Without loss of generality, we set the totalnumber of cells per row N = 41 to enable 20-trit addition,where each of the A and B vectors have 20 cells per vector,and we have one extra cell for the Cin trit. We also sweepRL ∈ 20, 30, 50, 100KΩ, and set RH = α ∗ RL whereα ∈ 10, 20, 30, 40, 50. A capacitive load CL = 100fF isused for the comparator to properly latch VML and distinguishbetween the fm and 1mm states due to fast discharge. Fig.6 presents the corresponding dynamic range values for the

10

Fig. 6. Dynamic range for the “3T3R” cell for 20-trit addition as a functionof RL and α.

Fig. 7. Compare energy for the “3T3R” cell for 20-trit addition as a functionof RL and α.

“3T3R” cell for 20-trit addition as a function of RL and α.The maximum, thus, best dynamic range is observed for lowestRL values. For example, DR ≈ 240mV when RL = 20KΩand α = 50. The compare energy for the “3T3R” cell for 20-trit addition as a function of RL and α is plotted in Fig. 7.For the same RL = 20KΩ, the lowest energy is obtainedat the highest α = 50. In fact, for RL = 20KΩ, whenα increases from 10 to 50, Efm drops by 71.61%, E1mm

drops by 22.27%, E2mm drops by 9.45% and E3mm drops by4.37%. As such, for the remaining experiments, we adopt thememristor values (RL, RH) = (20KΩ, 1MΩ) which providesthe best dynamic range with the corresponding lowest compareenergy consumption for this RL value.

B. Evaluation Against Binary SystemAs previously mentioned, the optimal number system is

found to be e which lies in between binary and ternary system.Hence, we evaluate the TAP performance against the BinaryAP. Herein, we compare the ternary LUT-based addition tothe respective binary LUT-based addition in terms of energyand area. For this, we employ the non-blocked approach sincethese metrics are common to both the blocked and non-blockedapproaches. The following section analyzes the delay of thedifferent proposed approaches.

Thus, in our experiments, we study the average energy for p-trit addition in comparison to the equivalent q-bit addition fordifferent p and q values, where p ∈ 5t, 10t, 20t, 32t, 40t, 80tand q ∈ 8b, 16b, 32b, 51b, 64b, 128b, respectively. For exam-ple, we compare p = 20t representing 20-trit addition to theequivalent q = 32b representing 32-bit addition.

We rely on HSPICE to characterize the compare energyfor 1-bit (1-trit) addition in the context of LUT-based bi-

nary (ternary) adder for the 2T2R [19] (3T3R) cell withRL = 20KΩ and RH = 1MΩ. We adopt CL = 100fFto correctly latch VML, and the number of cells per row isequal to 2q + 1 (2p + 1). We set the evaluate time to 1nsfor which we observe a DR approximately equal to 200mVfor the different simulations, allowing for good differentiationbetween the match and mismatch cases. The precharge timeis also set to 1ns.

We developed a functional simulator using MATLAB toobtain the average for the compare energy and write energyfor both the ternary and binary LUT addition, relying ona total of 10,000 p-trit and q-bit additions. The functionalsimulator estimates the number of set/reset operations takinginto consideration whether we are writing only one, two, orall three (A, S, Cout) cells based on the different LUTs andnumber of sets/resets required per cell (see Table V). Weassume the memristor write energy per set or reset operationto be on average around 1nJ as was stated in [26] fordifferent programming and initial memristor conditions. Thefunctional simulator also utilizes the 1-bit and 1-trit compareenergy values obtained using HSPICE to estimate the q-bit (p-trit) compare energy based on the different match/mismatchcombinations. For purposes of area comparison, we rely onthe number of cells per row for the q-bit (p-trit) additionassuming that the “2T2R” cell area is 0.67x the area ofone “3T3R” cell. Results are indicated in Table XI. Overall,compared to the LUT-based binary addition, the LUT-basedternary addition results in about 12.6% reduction in the totalnumber of sets/resets needed, 12.25% reduction in total energyand 6.2% area reduction.

C. Performance Comparison to Other Ternary Adder Designs

In this section, we compare the proposed ternary LUT-adder approaches against other ternary adder implementations.Particularly, we compare the total energy consumed by theproposed ternary AP (TAP) adder implementations againsthybrid CNTFET and memeristor-based implementations ofthe carry-ripple adder (CRA), carry-skip adder (CSA) andcarry-lookahead adder (CLA) [15]. We also conduct a delayanalysis for the TAP blocked and non-blocked approaches incomparison to the LUT-based binary adder and the CLA.

Our comparison is based on extrapolating the authors’ 4-bit adder’s power and delay simulations to reflect energy con-sumption and delay values for 20-trit addition at VDD = 0.8V .For our adder implementation, the consumed energy doesnot differ between the non-blocked and blocked approaches.We thus rely on Table XI to obtain the total energy forour TAP implementation. Fig. 8 presents the energy for thedifferent ternary adder implementations as function of thenumber of rows (#Rows, i.e., number of parallel additions).TAP consumes about 52.64% less energy than the CLA, whichin turn demonstrated lower energy consumption compared tothe CSA and CRA. We note that for all adder implementations,the energy grows linearly with the number of add operations.

We define the delay as the number of clock cycles neededto concurrently compare and write multiple rows within thedata array. While in the non-blocked approach every compareis followed by a write action, the blocked approach delays thewrite action until the end of the sequence of block compares,thus improving the overall delay of the adder. Note that,

11

TABLE XIENERGY AND AREA COMPARISON OF THE TERNARY AP ADDER WITH THE BINARY AP ADDER [6].

8b 5t 16b 10t 32b 20t 51b 32t 64b 40t 128b 80t

Energy

#Set = #Reset 5.99 5.22 11.99 10.53 24.04 21.02 38.24 33.67 47.98 42.17 95.98 84.54Write energy (nJ) 11.99 10.44 23.99 21.06 48.07 42.04 76.48 67.35 95.96 84.33 192.0 169.1Compare energy (pJ) 0.94 3.99 1.91 8.06 3.90 16.4 6.36 26.84 8.11 34.0 17.5 72.58Total energy (nJ) 11.99 10.44 23.99 21.07 48.07 42.06 76.49 67.38 95.97 84.36 192.02 169.17

Normalized Area 16x 15x 32x 30x 64x 60x 102x 96x 128x 120x 256x 240x

Fig. 8. Energy comparison of the TAP versus other ternary adders [15] forset/reset energy of 1nJ.

Fig. 9. Delay comparison for the blocked and non-blocked TAP implemen-tations with the CLA [15] and the binary AP adder [6].

irrespective of whether a match occurs or not, we account forthe write cycle. Fig. 9 shows the delay for the LUT ternaryadder using the non-blocked and blocked approaches, alongwith the CLA and the binary AP adder as a function of thenumber of rows (#Rows). Compared to the CLA, the non-blocked (blocked) TAP demonstrates lower runtime startingwhen the number of p-trit add operations (i.e., #Rows) exceeds64 (32). At 512 rows, the non-blocked and blocked TAPapproaches demonstrate a 6.8x and 9.5x reduction in delaycompared to the CLA, respectively. The blocked approachfurther shows a 1.4x reduction in delay compared to thenon-blocked approach for all #Rows. These results assumea traditional precharge cycle similar to Fig. 2.

In an optimized implementation where the precharge isembedded within the write cycle, the TAP adder is 9x smallerthan the CLA and the blocked TAP approach introducesaround 1.2x improvement compared to the non-blocked TAPapproach. This is due to the need for precharge post evaluatefor the compare cycles that are not followed by a write action.

Finally, it is worth noting that the binary AP adder demon-strates the lowest delay at 2.3x savings compared to the ternary

TAP in lieu of increased area and energy.

VII. CONCLUSION

In this paper, we proposed a novel multi-valued associa-tive processor with illustrative example on ternary-radix. Inaddition, we proposed efficient LUT-based ternary full addermethodology in the context of AP. The AP implementationrelies on a novel quaternary CAM “3T3R” cell. Novel al-gorithms are used to build the ternary adder LUT followingtwo approaches: a first non-blocked approach that formalizesthe intuition behind LUT pass ordering and a second blockedapproach that targets latency reduction in terms of capitalizingon common write action cycles. The efficiency of the proposedapproaches is proven by a formal simulator built using MAT-LAB in which we incorporate HSPICE simulations. Resultsshow that the ternary AP has lower energy and area comparedto the binary AP, albeit higher delay. Moreover, compared toother hybrid CNTFET and memristor implementations of theternary adder, the proposed ternary AP adder has lower energyand delay. Furthermore, the results demonstrate performanceefficiency for the blocked AP approach. In order to improvethe performance of MvAP, multi-valued CAM cell would needto optimized with less number devices and with more efficientwrite techniques.

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Mira Hout (SM 2017) received a B.Eng. degree inComputer and Communications Engineering (withHigh Distinction) from the Maroun Semaan Facultyof Engineering and Architecture, American Uni-versity of Beirut, Lebanon, in 2021. During hersenior year, she worked as a research assistant whereshe focused on topics of associative processors forpurposes of ternary logic ReRAM-based arithmeticcircuits design. She also worked as a teaching assis-tant in the Department of Electrical and ComputerEngineering at AUB for electronics courses. She is

currently a research intern at King Abdullah University of Science and Tech-nology with the Department of Electrical Engineering and Computer Sciencein the scope of an ongoing collaboration between AUB and KAUST. Her workrevolves around studying multi-valued CAM-based associative processorsin the context of in-memory arithmetic and logic compute. Her researchinterests include multi-valued logic, emerging ReRam-based methodologiesfor arithmetic circuit designs and in-memory computing.

Mohammed E. Fouda received a B.Sc. degree(Hons.) in Electronics and Communications Engi-neering and an M.Sc. degree in Engineering Mathe-matics from the Faculty of Engineering, Cairo Uni-versity, Cairo, Egypt, in 2011 and 2014, respectively.Fouda received his Ph.D. degree from the Universityof California, Irvine, USA in 2020. Currently, Heworks as an assistant researcher at University ofCalifornia, Irvine. Fouda has published more than100 peer-reviewed Journal and conference papers,one Springer book, and three book chapters. His H-

index is 21, with more than 1600 citations. His research interests includeanalog AI hardware, neuromorphic circuits and systems, brain-inspired com-puting, memristive circuit theory, fractional circuits, and systems and analogcircuits. He serves as a peer-reviewer for many prestigious journals andconferences. He also serves as a review editor in Frontier of Electronics andthe International Journal of Circuit theory and applications, in addition toserving as a technical program committee member in many conferences. Hewas the recipient of the best paper award in ICM years 2013 and 2020 andthe Broadcom foundation fellowship for 2016–2017.

Rouwaida Kanj received the M.S. and Ph.D. de-grees in electrical engineering from the Universityof Illinois Urbana-Champaign in 2000 and 2004,respectively. She is currently a tenured AssociateProfessor at the American University of Beirut.From 2004-2012 she worked as a research staffmember at IBM Austin Research Labs. Her researchwork focuses on advanced algorithmic research anddevelopment and smart analytics methodologies forDesign for Manufacturability Reliability and Yieldwith emphasis on statistical analysis, optimization

and rare fail event estimation for microprocessor memory designs along withmachine learning applications for Very Large Scale Integration. More recentlyshe is also involved in memristor-based memory design and reliability and thedesign of reliable circuits and systems for healthcare and in-memory compute.This is in addition to her earlier work on noise modeling and characterizationof CMOS designs. Dr. Kanj was a recipient of three IBM Ph.D. Fellowships,is the author of more than 81 technical papers, 36 issued US patents andseveral pending patents. She received an outstanding technical achievementaward and 6 Invention Plateau awards from IBM. She received the prestigiousIEEE/ACM WILLIAM J. MCCALLA ICCAD best paper award in 2009,and two IEEE ISQED best paper awards in 2006 and 2014, and the IEEEICM best paper award in 2020. In 2018 her work on statistical yield analysismethodology was nominated for the ACM/IEEE Richard Newton Award. Sheis currently a senior member of IEEE and serves or chairs on the technicalprogram committees of several prestigious IEEE conferences. She also servesas a peer-reviewer for many prestigious journals.

Ahmed E. Eltawil (S’97–M’03–SM’14) received aDoctorate degree from the University of California,Los Angeles, in 2003 and M.Sc. and B.Sc. degrees(with honors) from Cairo University, Giza, Egypt,in 1999 and 1997, respectively. Since 2019, he hasbeen a Professor at the Computer, Electrical, andMathematical Science and Engineering Division atthe King Abdullah University of Science and Tech-nology, Thuwal, KSA. Since 2005, he has been withthe Electrical Engineering and Computer ScienceDepartment at the University of California, Irvine.

His research interests are in the general area of low-power digital circuitand signal processing architectures, with an emphasis on mobile systems. Dr.Eltawil has been on the technical program committees and steering committeesfor numerous workshops, symposia, and conferences. He has received severalawards, as well as distinguished grants, including the NSF CAREER grantsupporting his research into low-power systems.