Implications of Imperfect Interfaces and Edgesin Ultra-small MOSFET Characteristics

A. Asenov (a), S. Kaya1) (b), and A. R. Brown (a)

(a) Device Modelling Group, Department of Electronics and Electrical Engineering,University of Glasgow, G12 8LT, Scotland, UK

(b) School of Electrical Engineering & Computer Science, Ohio University, Athens,OH 45701, USA

(Received March 15, 2002; accepted May 25, 2002)

PACS: 73.40.Qv; 85.30.De

We use 3D statistical simulations to analyze the influence of imperfect interfaces and edges in sub-100 nm MOSFET characteristics. In particular, we focus on the impact of gates deformed by lineedge roughness, and of oxide thickness variations resulting from a rough Si/SiO2 interface. The 3Dsimulations are based on a very efficient 3D drift-diffusion framework, which can introduce quan-tum mechanical corrections via the density gradient formalism. Random features at the gate edgesand at the Si/SiO2 interface have similar statistical descriptions, but use different parameter sets inaccordance with measurements. In MOSFETs, both line edge roughness and oxide thickness varia-tions result in intrinsic parameter fluctuations, which are comparable in magnitude to random do-pant effects. We simulate the dependence of intrinsic fluctuations on the statistical model param-eters of the roughness. We also consider the scaling of devices with rough gate edges and roughSiO2 interfaces. Our results highlight the importance of including realistic geometry features in thedesign and analysis of MOSFETs below 50 nm regime.

1. Introduction

In spite of all contrary expectations of the previous decade, the silicon CMOS revolu-tion is still continuing firmly and uninterrupted. In fact, it has lately displayed arenewed fervour, which resulted in the acceleration of device scaling [1], currentlydelivering devices having features two generations ahead of the 1997 incarnation of theSIA roadmap [2]. As a result of aggressive miniaturization of traditional CMOS archi-tecture into sub-100 nm dimensions, the importance of ‘atomistic’ considerations inMOSFET design and characterization become even more tangible [3]. In dimensionsonly two orders of magnitude above the atomic size, the earlier macroscopic under-standing of MOSFETs is far away from reality. Differences in the atomistic details ofMOSFETs in a large ensemble lead to mismatch in device performance parameters.Inescapably, an adequate description of MOSFET structures must now incorporate asmuch structural detail as possible [4], so that the degree of mismatch between MOS-FETs may be evaluated.Charge fluctuations associated with (random) distribution of dopants in a semicon-

ductor host, in both numbers and position, is a well-known cause of fluctuations inmeasurable device characteristics [5–7]. However, they are accompanied also by arange of other fluctuations related with imperfections in device geometry [8, 9]. Devicegeometry departs from the ideal picture as a result of interplay between the granular

phys. stat. sol. (b) 233, No. 1, 101–112 (2002)

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1) Corresponding author; e-mail: kaya@ohio.edu

nature of matter and the limitations in the fabrication processes. In this work, we con-centrate on two components of such imperfections: The intra- and inter-device varia-tions of the oxide thickness in MOS structure [9, 10] and line edge roughness (LER)present along the gate of a MOSFET [8, 11]. Since the oxide thickness and the gatedimensions are the two most important elements of technology scaling, having detri-mental roles in device characteristics, their intrinsic fluctuations require immediate andpronounced attention from a practical point of view. Although both effects have beenisolated and investigated experimentally, they were not treated in sufficient detail indevice modelling until recently. The main difficulties were due to computational limitsimposed by the 3D, statistical problem at hand, and to the relatively large dimensionsof earlier generation of MOSFETs. Yet, they constitute clear examples how granularityof underlying atomic structure and finite control available to technology in very smalldimensions may combine to blur device characteristics.In the following, we will first provide basic information on our strategy in dealing

with random interfaces and edges in a 3D simulation environment. This will be fol-lowed by two main sections, in which we demonstrate the impact of oxide thicknessvariations (OTV) and line edge roughness (LER) on MOSFET characteristics and onscaling trends. In the final section, we summarize our conclusions from a collectiveevaluation of the computer experiments included in this work.

2. The Simulation Approach

Results presented in this work have been obtained using an efficient, drift-diffusion(DD) based in-house device simulator, which incorporates a density gradient (DG)module as a means to account for quantum mechanical (QM) effects. All simulationsare carried out in 3D using statistical ensembles of 200 MOSFETs for each data point.It is necessary to have fine discretization near the interfaces and gate edges to accu-rately describe the random features in a 3D simulation domain. Moreover, the require-ment for statistical interpretation transforms the problem into a four dimensional onewhere the fourth dimension is the size of the statistical sample. Thus simulation effi-ciency has had a paramount role during the course of this work and prohibited the useof more complete descriptions for the transport problem.A robust method to introduce DG corrections in the DD system of equations has

been proposed in [12]. In the MOSFET simulations it is often sufficient to solve therelevant subset of equations for the majority carriers in the channel. For n-channeldevices this includes the following equations

r � er ð Þ ¼ �q p� nþNþD �N�

A

� �; ð1Þ

2bnr2 ffiffiffi

npffiffiffin

p ¼ �n � þ kT

qln

n

ni; ð2Þ

r � n�nr�nð Þ ¼ 0 ; ð3Þ

where bn ¼ �h=ð12qmn*Þ and all other symbols have their usual meaning. The electro-static potential , the quasi-Fermi level �n and the root square of the electron concen-tration

ffiffiffin

pin the above formulation are treated as independent variables. We restrict

our simulations in this study to low drain voltages, which allows us to decouple Eqs. (1)and (2) from Eq. (3) by considering a quasi-constant quasi-Fermi level. We have de-

102 A. Asenov et al.: Implications of Imperfect Interfaces and Edges

monstrated in an earlier work that, at low drain voltage, this approach is in excellentagreement with the full self-consistent solution of the DD equations [13]. Before applica-tion to 3D simulations, the DG approach has been carefully calibrated for continuousdoping against rigorous 1D full band Poisson-Schrodinger simulations presented by Jalle-palli et al. [14] in terms of threshold voltage shift and inversion layer charge distribution.

3. Random Interface and Edge Generation

Realistic 2D interfaces and 1D gate edges considered in our 3D simulations have beenreconstructed using a Fourier synthesis approach, which takes advantage of the relation-ship between the measured autocorrelation of a random feature and its Fourier spec-trum. Although using principally the same algorithm, the dimensionality is different inthe edge (1D) and surface (2D) modeling problem. In both cases, the reconstructionstarts from a 1D or 2D autocorrelation function with a given correlation length (L) andRMS height (D) [9, 15]. In the Fourier domain, the magnitude of elements of a 1D or2D complex array representing the height function is determined from the spectral in-formation, while the phase is selected at random. We impose necessary symmetries onthe arrays such that functions generated in the end will be real, without any complexterms. The inverse Fourier transform is then used to obtain a 1D or 2D height functionin real space. In LER modeling, this function is used to describe the gate edge, i.e. theactual delineation of the source/drain edge of the channel in 3D MOSFET simulations.In the case of OTV modeling, the height function is first quantized across one atomiclayer of Si, �3 �A, before it is used to form the Si/SiO2 interface boundary. The use ofrandom phases in the algorithm ensures that a statistically equivalent ensemble can bebuilt easily. We have two options, an exponential or a Gaussian model, for the autocor-relation function used in both versions of the algorithm, which provide additional flex-ibility and are in line with earlier experimental and modelling works published [9, 16].Interested readers may find a detailed description of the 2D algorithm elsewhere [15].

4. Oxide Thickness Variations (OTV)

Owing to its importance in MOSFET performance,a large body of literature on the structural and elec-trical properties of Si/SiO2 interface is available.Structurally, the use of novel microscopy tools withatomic resolution such as HRTEM [16] and AFM[9] has enabled us to investigate the chemical make-up of the random-discrete interface with a higherlevel of accuracy than has been possible before.Consequently, we find that correlation length

phys. stat. sol. (b) 233, No. 1 (2002) 103

Fig. 1 (online colour). Profile of the random Si/SiO2 inter-face in a 30 � 30 nm2 MOSFET (top) followed by an equi-concentration contour (middle) obtained from DG simu-lations and the potential distribution (bottom).LOTV ¼ 2.5 nm and no gate bias is applied

(LOTV) is in the range of 1–2 nm for HRTEM measurements and 10–15 nm for theAFM measurements. While lateral AFM resolution is limited by the scanning tip size toa similar level, HRTEM analysis has a practical limit in the long-wavelengths due tofinite sample size used. Low frequency terms in HRTEM data are often removed withpost-filtering to facilitate the analysis. Thus we consider the two methods complimen-tary, rather than contradictory, and alter LOTV in our simulations between 1–15 nm.The amplitude of OTV is taken to be half the atomic spacing between Si layers in zinc-blende structure, i.e. DOTV � 3 �A, since modern processes succeed in reducing the uni-formity of the interface down to a single Si layer.

4.1 Dependence on correlation length

In order to investigate the dependence of parameter fluctuations on DOTV and LOTV, weconsider a well-scaled generic MOSFET structure with an oxide thickness tox ¼ 1 nm,bulk doping NA ¼ 1018 cm––3, junction depth xj ¼ 7 nm and effective channel dimensionsLeff � Weff ¼ 50 � 50 nm2. These values are typical of the 70 nm technology node andminimize the short channel affects so that they will not create ambiguity in currentcomputer experiments. Mobility is kept constant at 500 cm2/Vs to improve efficiency incurrent simulations, where DG module is used to account for QM corrections.Figure 1 shows an example solution of electrostatic potential for Gaussian interface

autocorrelations with LOTV ¼ 2.5 nm at zero gate bias. It demonstrates the fluctuationsin potential landscape as seen by carriers in the channel below the random interface,which is the origin of deviations in the output current and the device threshold investi-gated throughout this work. Figure 2 shows that the threshold distributions evolve froma normal distribution at LOTV ¼ 5 nm to a binary one at LOTV ¼ 20 nm. The maximum

104 A. Asenov et al.: Implications of Imperfect Interfaces and Edges

Fig. 2. Threshold voltage variation in a 30 � 30 nm MOSFET with average oxide thicknesshtoxi ¼ 10.5 �A for different correlation lengths of the Gaussian power spectrum used to generatethe Si/SiO2 interface

values in the binary distributions are in agreement with the values calculated from twoextreme cases of oxide thickness possible when LOTV is comparable to Leff. The depen-dence of the threshold voltage standard deviation sVT on LOTV obtained from classicaland DG simulations are compared in Fig. 3. The introduction of quantum correctionsresults in an increase in the threshold voltage variation. We believe that this is relatedto the lateral confinement effects, which narrow the current percolation paths and ex-clude the classical charge in these regions. In both cases, the dependence of sVT onLOTV is linear for correlation lengths much smaller than the characteristic MOSFETdimensions and saturates for large LOTV. The saturation in the standard deviation ishence due primarily to inter-device component of OTV, while linear dependence atsmall LOTV may be attributed largely to intra-device component of OTV fluctuations.Note also the shift in calculated threshold distributions between classical and QM cases.The dependence of the kurtosis as a function of in the DG case is shown in the inset ofthe same figure. The increasingly negative values of the kurtosis are indication for theflattening of the distribution with the increase of the correlation length.The shape of the sVT dependence on LOTV can be easily understood qualitatively.

The binary distribution of the threshold voltage at LOTV �Leff, Weff result in sVT sa-turation at a value sVT

max � [VT (tox >¼ 12 �A) VT(tox ¼ 9 �A)]/2. This gives for examplesVT

max ¼ 49 mV in the DG case. In the case when L� Leff, Weff, we assume as a sim-plification that gate area Leff � Weff is divided into LOTV-sided squares, each with thinor thick oxide, respectively. Averaging the contribution of a total of N cells, whereN ¼ 4LeffWeff /LOTV the standard deviation of threshold is reduced by a factor of

ffiffiffiffi

Np

.Therefore,

�VT ¼ �OTVVmaxT

2ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

WeffLeffp : ð4Þ

Thus, for very small values of L the standard deviation should increase linearly.

phys. stat. sol. (b) 233, No. 1 (2002) 105

Fig. 3. Dependence of the thresh-old voltage standard deviation, sVT,on the correlation length, LOTV, forthe 30 � 30 nm2 MOSFETs as inFig. 2. Classical and DG simulationresults are compared

4.2 Oxide thickness dependence

We simulated the dependence of sVT on the average oxide thickness htoxi for a30 � 30 nm2 MOSFET with a rough Si/SiO2 interface. Results are given in Fig. 4, which

106 A. Asenov et al.: Implications of Imperfect Interfaces and Edges

Fig. 4. Dependence of threshold voltage standard deviation, sVT, on the average oxide thicknesshtoxi for a 30 � 30 nm2 MOSFET with random Si/SiO2 interface

Fig. 5. Dependence of the average threshold voltage hVTi on the average oxide thickness htoxi fora 30 � 30 nm2 MOSFET with random Si/SiO2 interface (symbols) and of the threshold voltage VT

on the oxide thickness tox for a similar device with uniform oxide (lines)

shows that fluctuations are virtually independent of htoxi. The independence of oxidethickness is related to the linear dependence between VT and tox, known from the text-book expression for the threshold voltage, which results in a constant variance withrespect to oxide thickness. We also present in Fig. 5 (symbols) the dependence of theaverage threshold voltage hVTi on htoxi calculated classically and quantum mechanically,this time only for LOTV ¼ 10 nm. For comparison, the dependence of the threshold vol-tage of devices with uniform oxide thickness is also plotted in the same figure (lines) asa function of tox. It is clear that the average threshold voltage hVTi of the devices withrandom oxide thickness is very close to the corresponding threshold voltage of uniformoxide MOSFETs with tox ¼ htoxi. The slight lowering of hVTi in the classical case isassociated with increase of the current density at the boundaries between the thinnerand thicker oxide regions due to excess classical charge.

4.3 Device scaling

The dependence of sVT on the effective channel width, Weff, and the effective channellength, Leff, are illustrated in Figs. 6 and 7, respectively. The variation of sVT in respectof Weff follows closely the expected 1=

ffiffiffiffiffiffiffiffiffi

Weffp

dependence from Eq. (4). The variation of�VT in respect of Leff follows the 1=

ffiffiffiffiffiffiffiffi

Leff

pdependence only for LOTV ¼ 2 nm and for

values of Leff larger than 30 nm. For Leff < 30 nm 2D charge sharing effects significantlyreduce the amount of the charge in the channel controlled by the gate and its contribu-tion to the threshold voltage variation, which results in a departure from the 1=

ffiffiffiffiffiffiffiffi

Leff

p

dependence. This effect is more pronounced at correlation length LOTV ¼ 10 nm wherethe departure from the 1=

ffiffiffiffiffiffiffiffi

Leff

pdependence of sVT occurs at effective channel lengths

below 40 nm.

phys. stat. sol. (b) 233, No. 1 (2002) 107

Fig. 6. Dependence of threshold voltage standard deviation, sVT, on effective channel width, Weff,for a 30 � 30 nm2 MOSFET with random Si/SiO2 interface

5. Line Edge Roughness (LER)

Total LER amplitude is traditionally defined to be 3DLER, where the LER rms ampli-tude (DLER) can be statistically obtained by inspection of lines generated by a givenlithography process. Data collected from different processes attest to, at present, a mini-mum total LER limit of 5 to 6 nm (i.e. DLER � 2 nm) [8]. This value, larger than theRoadmap requirements for devices below 100 nm, is alarming since metrology require-ments are often more difficult to meet than actual line-width specifications for a givenprocess. In contrast with rms values, significantly less is known regarding the correlationlength of LER (LLER), which is reported to vary between 10 nm and 50 nm [17]. Ourrecent analysis on actual LER data obtained from EUV and e-beam lithography pro-cesses yielded that typically LLER is approximately 30 nm [8]. It is reasonable to assumethat LLER may be reduced at higher resolution, which can utilise special resists and/or

108 A. Asenov et al.: Implications of Imperfect Interfaces and Edges

Fig. 7. Dependence of threshold voltage standard deviation, sVT, on effective channel length, Leff,for a 30 � 30 nm2 MOSFET with random Si/SiO2 interface

Fig. 8 (online colour). A typical50 � 200 nm2 MOSFETused in 3D simula-tions. LER has parameters LLER ¼ 20 nmand DLER ¼ 3 nm

advanced exposure techniques for better LER performance. The analysis also showedthat Gaussian and exponential models are found to perform equally well as leastsquare fits to the captured autocorrelation data. The presence of LER locally changesthe gate length for a MOSFET and introduces uncertainty in gate dimensions. An ex-ample simulated MOSFET with LER on the gate pattern is shown in Fig. 8. All fea-tures of MOSFETs used in LER simulations are similar to those given in Section 4.1.

5.1 Dependence on LER parameters

Complementary to threshold fluctuations, LER causes fluctuations in drain on-state cur-rent, Ion, as can be seen in Fig. 9. It is interesting to note that current distributionsdisclose a slight skew, which may be attributed to increased short channel effects inshorter elements of the ensemble. We verified that largest (smallest) Ion value in thedistributions correspond to the device with the shortest (longest) effective gate length.For given device dimensions, the standard deviation of threshold voltage fluctuationsdue to LER increases when LLER or DLER is increased. The latter dependence is givenin Fig. 10 for 30 and 50 nm MOSFETs. The inset in this figure plots the average thresh-old voltage lowering (hVTi––VT0), where VT0 is calculated without LER. Thus, LER notonly causes fluctuations but also lowers the threshold and its impact on threshold be-comes larger as gate dimensions are reduced. Moreover, the fluctuations are compar-able in magnitude to those resulting from random dopants in similar 30 � 30 nm2 de-vices studied by Asenov [5].

5.2 Device scaling

In this section, we simulate the geometry scaling of MOSFETs in which LER param-eters are fixed to foreseeable limits as explained earlier. Figures 11 and 12 display thedependence of the standard deviation of drain current on MOSFET gate width, Weff,

phys. stat. sol. (b) 233, No. 1 (2002) 109

20

40

60

2.5 3.0 3.5 4.0

20

40

60

20

40

60 = 2.5 nm

� LER= 10 nm

= 20 nm

� LER

� LER

Frequency

Current [10 A]-4

Fig. 9. Histograms showing drain on-current distribution in 200 (30 � 30 nm2) MOSFETs at threecorrelation lengths, and with DLER ¼ 2 nm. The skew is due to short channel effects

and length, Leff, respectively, for typical LER parameters. Both the on- and off-currentdependencies are given for comparison. Clearly the Weff dependence is an order ofmagnitude weaker than the Leff dependence. Wider devices provide a progressivelybetter average for the properties affected by the LER, thus reducing the uncertainty.The disproportionately large Leff dependence is due to acute short channel effects inregions with drastic reduction in the local channel length introduced by LER. The simu-lated dependence becomes especially severe for devices with a gate length below50 nm. Naturally in all cases off-current dependence is found to be more susceptible tothe presence of LER.The insets of Figs. 11 and 12 plot the ratio of average off-current to on-current.

Since the average on-current remains relatively constant (see Fig. 9), the ratio essen-

110 A. Asenov et al.: Implications of Imperfect Interfaces and Edges

0rms fluctuations [nm]

0

5

10

15

20�

V T[m

V]

0 1 2 3

� LER [nm]

0

2

4

6

8

10

VT

low

erin

g[m

V]

L=50 nm

L=30 nm

1 2 3

Fig. 10. Standard deviation of threshold voltage for two decanano MOSFETs as a function ofLER rms fluctuations at VD ¼ 1.0 V (squares) and VD ¼ 0.1 V (circles). LLER ¼ 20 nm for all cases

50 100 150 200

Channel Width [nm]

1

10

100

σID

[%]

off currenton current

50 100 150 200

<I of

f>/<

I on>

2.2 10-7

2.0 10-7

1.8 10-7

1.6 10-7

Fig. 11. Drain current standard deviation, sID, as a function of effective channel width in decananoMOSFETs. The inset shows ratio of average off- and on-currents. Note that VD ¼ 1.0 V,Leff ¼ 50 nm, LLER ¼ 20 nm and DLER ¼ 2 nm

tially provides a measure for the increased LER induced leakage. As in the case ofstandard deviation, the leakage current appears to be extremely sensitive to LER inMOSFETs with a gate length less than 50 nm. The width dependence of the samefigure of merit is not significant, remaining below 5% overall. Therefore, both LERamplitude and correlation length must be reduced below the current projected minimato prevent excess leakage and fluctuations in MOSFETs with gate dimensions below50 nm.

6. Conclusions

We have presented a 3D statistical simulation study of parameter fluctuations inMOSFETs due to imperfect interfaces and edges. Specifically, we have focused on theimpact of gate line edge roughness and oxide thickness variations. The former studyindicated that intrinsic fluctuations in MOSFETs due to LER become comparable insize to random dopant effects and can seriously inhibit scaling below 50 nm. LER has adetrimental influence on the off-current in sub-50 nm MOSFETs. In a similar manner,OTV can cause significant intrinsic fluctuations, which become especially severe at largecorrelation lengths. We have also observed that quantum mechanical correctionsincluded in the simulations using a density gradient formalism increases the severity ofthe fluctuations due to OTV. Our results highlight the importance of including realisticgeometry features in the design and analysis of MOSFETs below 50 nm regime.

Acknowledgement We would like to thank to J. H. Davies for useful discussions andsuggestions during the course of this work.

References[1] R. Chau et al., IEDM Tech. Dig. 45 (2000).[2] The International Technology Roadmap for Semiconductors, 1999 ed., available at

http://public.itrs.net/Reports.htm

phys. stat. sol. (b) 233, No. 1 (2002) 111

20 40 60 80 100Channel Length [nm]

1

10

100

1000

σID

[%]

off currenton current

20 40 60 80 10010-8

10-7

10-6

10-5

10-4

<I of

f>/<

I on>

Fig. 12. Dependence of drain current standard deviation, sID, on the effective gate length in de-canano MOSFETs. The inset shows ratio of average off- and on-currents. Note that VD ¼ 1.0 V,Weff ¼ 50 nm, LLER ¼ 20 nm and DLER ¼ 2 nm

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112 A. Asenov et al.: Implications of Imperfect Interfaces and Edges