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Implementation Platform for Memory and Logic Integration. Wayne Dai June 9, 2002. Outline. Challenges and opportunities for System-in-a-Package (SiP) SiP implementation platform for memory/logic integration Configurable area-IO memory architecture - PowerPoint PPT Presentation
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Implementation Platform for Memory and Logic IntegrationWayne Dai
June 9, 2002
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OutlineChallenges and opportunities for System-in-a-Package (SiP)SiP implementation platform for memory/logic integrationConfigurable area-IO memory architectureSiP performance analysis and modeling based on GTX frameworkConcluding remarks
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Messages from ITRSPackage cost increases 5% each year.8% - 11% increase in pin count per packaged IC each year, 5% reduction in cost per pin each year.Inter-chip signal integrity issues will be more challenging.In 2002, chip to board clock frequency is 400MHz for cost-performance system, 800MHz for high-performance system.Package size can not shrink due to the fanout problem.Moores law is good for silicon, but not good for board.System-on-a-Chip is not always a good idea.Cost penalty, complexity of design and verification, difficulty of integrating different technologies
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The Y Chart of System DesignSynthesisImplementationARCHITECTURAL DOMAINFUNCTIONAL DOMAINuPDRAMFlashPHYSICAL DOMAINMissingPlatform-based design methodology is the only solution to deliver complex embedded systems in a limited design time.
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System-in-a-Package Implementation PlatformA giant chip rather than a miniaturized circuit board: preserving on-chip electrical environmentChip-on-ChipChip-Laminate-ChipDRAM and graphic chip integration
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Chip-Laminate-Chip Technology Characteristic:Maximum off-chip delay