Implementation of Power Transmission Lines to Field

Programmable Gate Array ICs for Managing Signal

and Power Integrity

Sang Kyu Kim, Satyanarayana Telikepalli, Sung Joo

Park, Madhavan Swaminathan and David Keezer

Department of Electrical and Computer Engineering

Georgia Institute of Technology

266 Ferst Dr. Atlanta, GA 30328

Youkeun Han

DRAM technology, Memory Division

Samsung Electronics Co. Ltd.

Hwasung-city, Gyeonggi-do, Korea 445-701

Abstract—As the operating frequencies of electronic devices

increase, power and signal integrity have become a major issue.

Simultaneous switching noise (SSN) is a major problem that

restricts the performance of high speed digital systems. SSN

leads to voltage fluctuations during data transitions which can

induce excessive noise. SSN is caused by parasitic inductance

components in the power delivery network (PDN) that manifest

themselves through via transitions, apertures on reference plane,

split planes and even solid planes. A new method has been

proposed to address this problem, which employs power

transmission lines (PTL) that supply power to integrated circuits

instead of using the conventional power/ground plane pairs.

This along with current balancing can be used to manage return

path discontinuities and power supply noise. Many of the

published work in this area have proved that the PTL concept is

able to reduce SSN and enhance power and signal integrity.

Pseudo-balanced power transmission line (PB-PTL) concept has

been shown to improve performance and reduce power

consumption. However, this has only been applied to relatively

simple test vehicles. In this paper, the PB-PTL scheme has been

extended for driving multiple I/O drivers in field programmable

gate array (FPGA) ICs. This paper discusses the theory,

simulation and measurement results for this implementation.

I. INTRODUCTION

In high speed digital systems with multiple I/O drivers, simultaneous switching noise (SSN) is a major factor that restricts system performance. SSN in the package and boards occurs wherein there is an interruption in the return current paths. This return path discontinuity (RPD) excites the cavity resonance between power and ground plane, which degenerates signal integrity. Via transitions, split planes and apertures on the reference plane are reasons for generating excessive SSN. Furthermore, SSN can be caused by solid voltage plane during data transitions as well [1].

Many of the methodologies prevent SSN using decoupling capacitors, stitching vias at RPD locations and differential signaling scheme [2]-[4]. Recently a new method for

eliminating the RPDs has been proposed. This replaces the power plane with transmission lines when connecting the voltage regulator module (VRM) to the integrated circuits (ICs). The transmission line, which serves as the power delivery network (PDN), is referred to as power transmission line (PTL) in this paper [5].

There are several issues to be addressed for using PTL namely, 1) dc drop through the source termination resistor during data transitions, 2) impedance mismatch due to manufacturing variations, and 3) layout congestion due to increasing the number of PCB traces. The first two problems can be solved using the constant current power transmission line scheme (CC-PTL). The CC-PTL adds a data pattern detector, switching networks and dummy paths to the PTL so that it maintains constant amount of current flowing through the PTL at all time [6]. This scheme, however, doubles power consumption compared to the conventional PDN. To reduce power overhead, pseudo-balanced signaling scheme has been employed to PTL and called PB-PTL. This concept uses a balanced coding scheme, but some of the encoded bits are discarded when the bit sequences are transmitted to the receiver. The PB-PTL concept not only eliminates RPD, but also reduces inductive noise because it controls the number of high states of data patterns. The PB-PTL improves jitter characteristics, eye patterns and decreases power consumption compared to CC-PTL as well [7].

In the past a simple I/O driver with few output buffers has been used to demonstrate the PTL concept [6], [7]. In this paper we extend the PB-PTL concept to a more realistic application. In [8], we briefly explained the implementation of PTL in a Field Programmable Gate Arrays (FPGA) IC. In this paper, we provide details on the layout and measurements.

This work was sponsored by Samsung under award number 2106CHU

II. LAYOUT DESIGN

A. Description of FPGA Board

The Xilinx Spartan-6 LX45 FG(G) 484 has 338 I/O drivers. Collection I/O drivers is called a bank and the Xilinx chip consists of 4 banks (bank 0 ~ bank 3), which is shown in Fig. 1 [9]. In order to power to bank 3, a power transmission line (PTL) is inserted instead of the conventional power/ground pairs. Bank 3 has 88 I/O drivers and in this paper 30 of them are used for single-ended signaling.

Figure 1. Diagram of I/O banks in Xilinx Spartan 6 IC

Layout designs for two test vehicles are shown in Fig. 2. Fig. 2(a) and (b) represents the layout for the test vehicle using PTL while Fig. 2(c) and (d) shows the design using conventional power/ground pairs. A strip line in Fig. 2(a) is the PTL and the characteristic impedance of this line is designed to be 10Ω. In Fig. 2(b), the PTL is magnified to show how its connection to power supply pins of FPGA IC. It is important to note that the impedance is much higher than the conventional PDN structure. The shaded region in Fig. 2(c) represents the power plane. Similarly, the same region for the conventional design is enlarged in Fig. 2(d). The characteristic impedance of signal transmission lines for output drivers is 50Ω.

B. Stack-up layer of FPGA Board

Stack-up layer designs for both test vehicles are shown in Fig 3. The board using the PTL has 5 layers (Fig. 3(a)), which are signal(Top)-ground(GND1)-signal(Inner1)-power(PWR1)-signal(Bottom). The ICs including the FPGA, power supply, user interfaces, inputs and 18 of 30 output signal transmission lines are on the Top layer. The others such as 12 output signal transmission lines and some passive components are placed on the Bottom layer. Note that the PTL is inserted into Inner1 layer and this was intentionally done to demonstrate the concept in this paper. It is important to note that with PTL, the layers typically decrease and not increase since the PTL can be placed on the same layer as the signal transmission lines [5]. For the test vehicle using power/ground planes which we call as the conventional design, here it has 4 layers, which are signal(Top)-ground(GND1)-power(PWR1)-signal(Bottom).

In conventional designs signal integrity is invariably affected by RPDs [1]. However, for the stack-up in Fig. 3(b) there are no RPDs. Hence, in this paper, the effect on signal integrity comes purely from power supply noise and other discontinuities. The components for the conventional design on each layer are the same as the PTL board, except for no

Inner1 layer in the board. The focus of the two test vehicles is to compare and contrast the two designs in terms of eye diagrams.

The total thickness of the PTL board is 46.75 mil while the conventional board is 44.9 mil. The difference in thickness is due to the additional layer of the PTL and the fabrication process. Copper (thickness 1.35 mil.) and FR-4 (εr = 4.5) are used for both boards. Once again, it is important to note that in actual implementation, the PTL board would be thinner since it will contains fewer layers.

(a)

(b)

(c)

(d)

Figure 2. Layout design (a) power transmission line (b) power transmission

line (enlarged) (c) conventional design (d) conventional design (enlarged)

Power

Plane

PTL

(a)

(b)

Figure 3. Stack-up layer (a) power transmission line (b) conventional

design

Figure 4. Fabricated board

Figure 5. Cross section of power transmission line

C. Fabrication of FPGA Board

The fabricated boards are shown in Fig. 4 with some important functionality are briefly described in this section. Both test vehicles have 6 outputs connected to SMA connectors and the others are terminated (50Ω) to ground. In addition to 80 pin input connectors, there are 4 input SMA connectors on the board. Figure 5 shows a cross section in which the PTL is connected from the power supply connector (Top layer) to the FPGA IC (Inner1 layer).

III. CIRCUIT MODELING

The circuit model of the PB-PTL is shown in Fig. 6. The

output drivers of FPGA ICs are represented as transistors.

The directions of current show pull-up states (right

direction) and pull-down states (left direction) respectively.

Note that there is a source termination resistor between the

PTL and VDD for series-parallel termination scheme. With

pseudo-balanced signaling, however, impedance mismatch

effect can be minimized regardless of the termination

resistors. When 4-to-6 pseudo-balanced signaling is used,

3 transistors are always turned-on out of 6 drivers.

Therefore, the amount of current flowing through the PTL

is constant at any time and this eliminates impedance

mismatch. Moreover, the pseudo-balanced signaling can be

uniquely decoded at receiver. In Fig. 6, the 6th

bit is used

as the balancing bit and it is not transmitted to the receiver.

Figure 6. Circuit model of pesudo-balanced signaling scheme in the power

transmission line

A. Power Transmission Line Simulation

The schematic of the PTL was simulated using Agilent ADS.

Figure 7. Simulated eye diagram for PTL case

The eye diagram from simulation is shown in Fig. 7. The

eye height is 1.0258V and the eye width is 2.51ns. The peak-

to-peak jitter is 155.2ps [8].

B. Conventional PDN Simulation

The conventional design simulated in SONNET is shown in Fig. 8.

Figure 8. Simulated power and ground plane for conventinal board

In the simulation, ports were placed in 12 locations, 1 port at the power supply voltage location, and the other 11 ports at the VCCO pins of the FPGA IC. The resulting S-parameters were then simulated with the Spartan-6 IBIS models provided by Xilinx.

Figure 9. Simulated eye diagram for conventional power plane case

The resulting eye diagram is shown in Figure 9. The eye

height is 0.926V, which is an 11% decrease from the PTL

scheme. In addition, the eye width is 2.47ns and the peak-to-

peak jitter is 221.73ps. The peak-to-peak jitter is a 52%

increase compared with the PTL circuit [8].

IV. PROGRAMMING

The pseudo-balanced coding scheme is illustrated in Fig. 10. In 4-to-6 coding, 3 output drivers are always turned on, thereby keeping the current through the power distribution network constant. With 20-to-30 coding in Fig. 10, 15 output drivers are always turned on at any time. The total current was 500mA when using 20-to-30 coding.

The input signal consists of a clock signal and a reset signal. The clock signal is connected to the pseudo-random bit sequence generator, which uses a linear feedback shift register (LFSR) and two registers for synchronizing each output stage, as shown in Fig. 10. The reset signal is connected to the pseudo random bit sequence (PRBS) block.

Figure 10. Block diagram of programming

Figure 11. Block diagram of testing setup

Figure 12. Testing setup

V. MEASUREMENT RESULTS

Fig. 11 is the block diagram of the testing configuration and Fig. 12 is the measurement setup. Three power supplies (E3610A) were used. The voltage of one power supply was set to 1.2V, which was connected to the supply voltage for the FPGA core. The other two power supplies were of voltage 2.5V, where one was connected to the auxiliary supply voltage and the other to supply voltages for bank 0-bank 3. For the PTL board, however, an additional power supply was used to provide voltage for bank 3. A signal generator (81133A) and an oscilloscope (DCA-X86100D) were connected to the board for providing the input source and measuring the output waveform.

Since each output driver requires 1.55V and 31mA, it consumes a large amount of power. Therefore, the pseudo-balanced coding scheme was reduced to 8-to-12 and 12-to-18 instead of 20-to-30. For the test vehicle using PTL, pseudo-balanced coding scheme was employed and the output was measured with (Fig. 6) and without the series source termination resistors. For the conventional board consisting of power and ground planes, the PRBS was used as the input signal. In other words, when using 12-to-18 coding scheme, the number of I/O drivers for the PTL board was 18 as compared to the conventional board, which was 12.

To maintain 2.5V at the power supply pin of the FPGA, the power supply voltage for the PTL with source termination resistors was adjusted. This is shown in Table I for 12-to-18 coding and in Table II for 8-to-12 scheme. As frequency increases, the FPGA draws more current which results in an increase in the supply voltage. For 12-to-18 coding, the total amount of constant current was 300mA and for 8-to-12 coding, 200mA.

Table III shows the measured peak-to-peak jitter of both test vehicles when using 12-to-18 coding scheme. Table IV shows when 8-to-12 coding scheme is used. In the tables, the PTL (W/ Rs) stands for the PTL’s test vehicle when the series source termination resistors were used while the PTL (W/O

Rs) corresponds to the PTL board without source resistors (uses same voltage as the conventional board). Similarly, the conventional design using PRBS is shown as Conventional (W/O Coding) while Conventional (W/ Coding) employed pseudo-balanced signaling. The objective for removing the source resistor is to check if there are changes in the signal integrity of the waveform. The conventional board refers to the board using power and ground planes with PRBS and pseudo-balanced signaling as the input signal. Figure 13 and 14 shows the waveform comparison between the PTL board without source resistors and the conventional board without using the pseudo-balanced coding for 600MHz frequency. The eye diagrams of the PTL without termination resistors and the conventional board using PRBS are similar to Fig. 13, so they are not included.

TABLE I. ADJUSTED VOLTAGE FOR THE PTL WITH THE TERMINATION

RESISTORS AND 12-TO-18 CODING SCHEME

Clock Frequency [MHz] Adjusted Voltage [V]

100 5.67

200 5.67

300 5.72

400 5.97

500 6.15

600 5.84

TABLE II. ADJUSTED VOLTAGE FOR THE PTL WITH THE TERMINATION

RESISTORS AND 8-TO-12 CODING SCHEME

Clock Frequency [MHz] Adjusted Voltage [V]

100 4.60

200 4.60

300 4.62

400 4.80

500 4.87

600 4.80

TABLE III. PEAK-TO-PEAK JITTER (12-TO-18 CODING SCHEME)

Clock

Freq.

[MHz]

Peak-to-Peak jitter [ps]

PB-PTL

(W/O Rs)

PB-PTL

(W/ Rs)

Conventional

(W/ Coding)

Conventional

(W/O Coding)

100 106.6 106.6 80.0 773.4

200 80.0 80.0 80.0 600.0

300 86.7 80.0 86.7 400.0

400 180.0 166.7 213.4 333.4

500 160.0 180.0 240.0 246.7

600 100.0 100.0 93.4 266.7

TABLE IV. PEAK-TO-PEAK JITTER (8-TO-12 CODING SCHEME)

Clock

Freq.

[MHz]

Peak-to-Peak jitter [ps]

PB-PTL

(W/O Rs)

PB-PTL

(W/ Rs)

Conventional

(W/ Coding)

Conventional

(W/O Coding)

100 53.4 80.0 53.4 480.0

200 66.7 66.7 80.0 333.3

300 73.4 66.7 73.4 273.4

400 126.7 120.0 206.7 206.7

500 86.7 80.0 93.4 166.7

600 93.4 93.4 80.0 160.0

Figure 13. Output eye diagram of PB-PTL without source termination

resistors for 12-to-18 coding scheme

Figure 14. Output eye diagram of conventional design without pesudo-

balanced signaling for 12-to-18 coding scheme

The improvement in Peak to Peak jitter between PB-PTL without source resistor and conventional board using PRBS is 50% - 84% for 12-to-18 coding and 40% - 89% for 8-to-12 coding, over a frequency range of 100–600MHz. This improvement in jitter is caused due to a reduction in power supply noise which impacts deterministic jitter. Although the measurement data of root-mean-square (RMS) jitter, eye height and eye width are not provided in this paper, the PB-PTL provided broader eye diagram and reduced RMS jitter. For instance, the improvement in RMS jitter between PB-PTL without source resistor and conventional board is 52% – 87% for 12-to-18 coding and 50% - 84% for 8-to12 coding, over a frequency range of 100–600MHz. The jitter characteristics and eye patterns between the PTL with and without source resistors are similar to each other. This is because pseudo-balanced coding scheme decreases inductive noise by restricting the number of high states during data transitions. Moreover, the impedance mismatch effect is minimized since the PTL is kept charged all the time. Comparing PB-PTL board and conventional board with coding, the PB-PTL scheme provided better signal integrity with reduced jitter at most frequencies.

VI. CONCLUSIONS

Pseudo-balanced signaling using PTL (PB-PTL) was implemented and compared to a conventional board for FPGA ICs. The PTL board was measured both with and without source termination resistors. For conventional board, Pseudo-balanced signaling was applied to the conventional board design as well. Since the RPD is not present in the conventional board, the reason for the deterioration in the eye diagram is due to power supply noise. The PB-PTL provided wider eye diagram with pseudo-balanced signaling than the conventional board. This result indicates that the PTL can be used to replace the voltage plane and can be used to service several drivers. With the introduction of RPDs in the board, PB-PTL will provide better performance as compared to conventional design using voltage plane, even if the source coding is used for both, as shown in [6], [7]. In addition, there was no appreciable difference in signal integrity in the PTL board with and without the source termination resistor since the far end of the transmission lines were terminated. Hence, the source termination resistor has a small role to play in improving the waveforms and therefore can be removed. This results in power savings.

REFERENCES

[1] M. Swaminathan, D. Chung, S. Grivet-Talocia, K. Bharath, V. Laddha, and J. Xie, “Designing and Modeling for Power Integrity,” IEEE Transactions on Electromagnetic Compatibility, vol. 52, no. 2, pp. 288–310, May 2010.

[2] M. M. Pajovic, J. Yu, Z. Potocnik, and A. Bhobe, “Gigahertz-Range Analysis of Impedance Profile and Cavity Resonances in Multilayered PCBs,” IEEE Transactions on Electromagnetic Compatibility, vol. 52, no. 1, pp. 179–188, Feb. 2010.

[3] I. Ndip, F. Ohnimus, K. Löbbicke, M. Bierwirth, C. Tschoban, S. Guttowski, H. Reichl, K.-D. Lang, and H. Henke, “Modeling, Quantification, and Reduction of the Impact of Uncontrolled Return Currents of Vias Transiting Multilayered Packages and Boards,” IEEE Transactions on Electromagnetic Compatibility, vol. 52, no. 2, pp. 421–435, May 2010.

[4] X. Wang and D. Su, “The Influence of Power/Ground Resonance to Via’s SSN Noise Coupling in Multilayer Package and Three Mitigating Ways,” in 2006 International Conference on Electronic Materials and Packaging, 2006, pp. 1–5.

[5] A. Ege Engin and M. Swaminathan, “Power transmission lines: A new interconnect design to eliminate simultaneous switching noise,” in 2008 58th Electronic Components and Technology Conference, 2008, pp. 1139–1143.

[6] S. L. Huh, M. Swaminathan, and D. Keezer, “Constant Current Power Transmission Line-Based Power Delivery Network for Single-Ended Signaling,” IEEE Transactions On Electromagnetic Compatibility, vol. 53, no. 4, pp. 1050–1064, 2011.

[7] S. Huh, M. Swaminathan, and D. Keezer, “Design of power delivery networks using power transmission lines and pseudo-balanced signaling for multiple I/Os,” in 2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, 2011, pp. 287–290.

[8] Satyanarayana Telikepalli, Sang Kyu Kim, Sung Joo Park, Madhavan Swaminathan and and Youkeun Han, “Managing signal and power integrity using power transmission lines and alternative signaling schemes”, IEEE Latin American Symposium on Circuts and Systems, March 2013.

[9] “XA Spartan-6 FPGA Family” Internet: http://www.xilinx.com/products/silicon-devices/fpga/xa-spartan-6/index.htm

Eye height

1.37V

Peak-to-peak jitter

100.0 ps

Eye height

1.34V

Peak-to-peak jitter

266.7 ps