Impact of interfacial layer on low-frequency noise of HfSiON dielectric MOSFETs

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 6, JUNE 2006 1459

Impact of Interfacial Layer on Low-FrequencyNoise of HfSiON Dielectric MOSFETs

Bigang Min, Siva Prasad Devireddy, Student Member, IEEE, Zeynep Çelik-Butler, Senior Member, IEEE,Ajit Shanware, Member, IEEE, Luigi Colombo, Member, IEEE, Keith Green, Member, IEEE,

J. J. Chambers, M. R. Visokay, and Antonio Luis Pacheco Rotondaro, Member, IEEE

Abstract—Low-frequency noise measurements and analysiswere performed on n-channel MOSFETs with HfSiON as thegate-dielectric material. The role of SiON interfacial-layer thick-ness was investigated. It was observed that these fluctuations canbe described by the unified flicker-noise model that attributes noiseto correlated carrier-number/mobility fluctuations due to trappingstates in the gate dielectric. The model was modified to includethe effect of different gate stack layers on the observed noise.The carrier-number fluctuations were found to dominate over thecorrelated mobility fluctuations in the measured bias range andmore so at the lower gate overdrives. The noise magnitude showeda decrease with increasing SiON interfacial-layer thickness. Fur-thermore, an inverse-proportionality relationship was revealedbetween the effective oxide trap density and SiON thickness.

Index Terms—HfSiON, high-k dielectric, interfacial layer (IL),low-frequency (LF) noise, oxide trap density, MOSFET, 1/fnoise.

NOMENCLATURE

CEOT Equivalent oxide capacitance ofMOSFET (F · cm−2).

Ec Conduction-band energy level (eV).Ev Valence-band energy level (eV).f Frequency (Hz).ft Trap occupancy function.gd Conductance (A · V−1).gm Transconductance (A · V−1).Id Drain current (A).k Boltzmann’s constant (eV · K−1).L Channel length of the MOSFET (µm).Nit Number of occupied traps per unit area

(cm−2).Ninv Inversion carrier density (cm−2).Nt Effective oxide trap density (cm−3·eV−1).

Manuscript received January 9, 2006; revised March 21, 2006. This workwas supported in part by the Semiconductor Research Corporation underContract 2004-VJ-1193 and by the Texas Higher Education Board, ATP, underGrant 003656-0001-2001. The review of this paper was arranged by EditorM. J. Deen.

B. Min, S. P. Devireddy, and Z. Çelik-Butler are with the Department ofElectrical Engineering, University of Texas at Arlington, Arlington, TX 76019USA (e-mail: [email protected]).

A. Shanware, L. Colombo, K. Green, J. J. Chambers, M. R. Visokay, andA. L. P. Rotondaro are with Texas Instruments Incorporated, Dallas, TX 75243USA.

Digital Object Identifier 10.1109/TED.2006.874759

NtHK(Efn) Oxide trap density at the quasi-Fermi levelin the high-k layer (cm−3 · eV−1).

NtIL(Efn) Oxide trap density at the quasi-Fermi levelin the interfacial layer (IL) (cm−3 · eV−1).

NtSiO2(Efn) Oxide trap density at the quasi-Fermi levelin SiO2 (cm−3 · eV−1).

NtHK(E, x, y, z) Oxide-trap-density distribution in thehigh-k layer over space and energy(cm−3 · eV−1).

NtIL(E, x, y, z) Oxide-trap-density distribution in the ILover space and energy (cm−3 · eV−1).

NtSiO2(E, x, y, z) Oxide-trap-density distribution in SiO2

over space and energy (cm−3 · eV−1).q Electronic charge (C).SId

Drain-current noise power spectral density(PSD) (A2 · Hz−1).

S∆Id(x, f) PSD of the local current fluctuations

(A2 · Hz−1).S∆Nit(x, f) PSD for mean-square fluctuations of the

trapped charge carriers over the areaW∆x(Hz−1).

T Temperature (K).Tox Oxide thickness (nm).TIL Interfacial-layer thickness (nm).THK High-k dielectric thickness (nm).Vd Drain-to-source voltage (V).Vg Gate-to-source voltage (V).Vt Threshold voltage (V).W Channel width of the MOSFET (µm).αsc Coulomb scattering coefficient (V · s).αH Hooge’s coefficient.γHK Attenuation coefficient of the electron

wave function in the high-k (cm−1).γIL Attenuation coefficient of the electron

wave function in the IL (cm−1).γSiO2 Attenuation coefficient of the electron

wave function in SiO2 (cm−1).δ Flicker-noise coefficient.µeff Carrier effective mobility (cm2·V−1·s−1).µc0 Mobility fluctuations fitting parameter

(cm · V−1 · s−1).τ0 Trapping time constant at the interface (s).τHK(E, x, y, z) Trapping time constant for high-k

dielectric (s).τIL(E, x, y, z) Trapping time constant for the IL (s).τSiO2(E, x, y, z) Trapping time constant for SiO2 (s).

0018-9383/$20.00 © 2006 IEEE

1460 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 6, JUNE 2006

ω Angular frequency (radians/s).∆N Number of inversion carrier over the area

W∆x.∆Nit Number of occupied traps over the area

W∆x.∆V Infinitesimal volume in the gate dielectric

(cm3).∆x Infinitesimal length in the gate dielectric

(cm).∆y Infinitesimal width in the gate dielectric

(cm).∆z Infinitesimal thickness in the gate dielec-

tric (cm).

I. INTRODUCTION

H fSiON has been studied as a possible MOSFET dielectricmaterial for the past several years [1]–[9]. It has been

demonstrated that the use of HfSiON results in the reductionof gate leakage currents and improved device reliability [2], asit remains amorphous after high-temperature annealing, offersexcellent blocking against Boron penetration, and has goodthermal stability when in contact with a silicon substrate andpolysilicon gate material [3]–[6]. Compared to other high-kgate dielectrics, the flatband shift and mobility degradation arealso less pronounced in HfSiON transistors [7]–[9].

An investigation of low-frequency (LF) noise exhibited byhigh-k gate-dielectric MOSFETs is necessary not only to pin-point the origin of these fluctuations and minimize the noise,but also to use these noise measurements as a diagnostic toolin evaluating the dielectric quality and its interface with silicon[10]. Although reports of such studies on HfSiON devices arestill very limited, it is know that the 1/f noise magnitude andeffective oxide trap density in the high-k dielectric transistorsare one to two orders of magnitude higher than those in SiO2

and SiON devices [11]–[13]. It has been shown that the majorcontributor to 1/f noise is the trapping and detrapping ofcarriers by the traps inside the high-k layer, and the thicknessof the IL has a key role in the observed noise levels [13]–[15].In this paper, the unified flicker-noise model (UFNM) ismodified to take into account the effect of various layersof high-k gate-dielectric stack. We report on the LF-noisebehavior for HfSiON devices with different interfacial-layerthicknesses when biased in the linear strong inversion region.The physical mechanisms causing the LF noise are exploredand a relationship between oxide trap density and the thicknessof the IL is derived.

II. MODIFIED UFNM

According to the UFNM, the current fluctuations in thechannel are caused by both carrier-number fluctuations andcorrelated mobility fluctuations due to remote Coulomb scat-tering by the trapped charge in the dielectric. This can beexpressed as [16]

δIdId

= −(

1∆N

δ∆Nδ∆Nit

± 1µeff

δµeff

δ∆Nit

)δ∆Nit (1)

where Id is drain current, µeff is channel effective mobility,∆N = NinvW∆x, and ∆Nit = NitW∆x. Ninv is the numberof channel carriers per unit area, and Nit is the number ofoccupied traps per unit area. ∆x is the incremental lengthof an infinitesimal volume (∆V ) in the dielectric. The ratioof (δ∆N)/(δ∆Nit) can be considered as unity in strong in-version [17]. It should be noted that the assumption (δ∆N)/(δ∆Nt) ≈ 1 made in this simplification is not valid at relativelylow effective gate voltages |Vg–Vt|. The sign preceding the sec-ond term is determined by whether the active traps are repulsive(+ sign) or attractive (− sign). For the case of acceptor trapsin an n-channel MOSFET, as is the case here, the mobilityfluctuations term would be additive.

The PSD of local current fluctuations is given as

S∆Id(x, f) =

[Id

∆N(1 ± αscµeffNinv)

]2

S∆Nit(x, f) (2)

where αsc is the screened scattering coefficient, andS∆Nit(x, f) is the PSD for mean-square fluctuations of thetrapped charge carriers over theW∆x area, and is expressed as

S∆Nit(x, f) =

Ec∫Ev

W∫0

Tox∫0

4NtSiO2(E, x, y, z)∆xft(1 − ft)

× τSiO2(E, x, y, z)1 + ω2τ2

SiO2(E, x, y, z)

dzdydE. (3)

Here, ft is the trap occupancy function, τSiO2(E, x, y, z) is thetrapping time constant, ω = 2πf is the angular frequency, Ec

and Ev are the conduction-band and valance-band edges, re-spectively,W is the device gate width,NtSiO2(E, x, y, z) is theoxide trap density over space and energy, and z is the electrontunneling distance from 0 (interface) to Tox (the oxide thick-ness). Assuming equal-energy direct tunneling of the channelcarriers over a rectangular barrier, we take τ = τ0 exp(γz),where γ is the tunneling coefficient that can be expressedas γ = (4π/h)

√2m∗Φ, according to the Wentzel–Kramers–

Brillouin (WKB) approximation. Here, m∗ is the electroneffective mass in the dielectric, h is the Planck’s constant, and Φis the barrier height (band offset between Si and the dielectric).Then, for a uniform trap distribution in the gate oxide, (3) canbe integrated to obtain

S∆Nit(x, f) =NtSiO2 (Efn

)WkT∆xγSiO2f

2π

×[tan−1 (ωτ0 exp(γSiO2Tox))−tan−1(ωτ0)

]

=NtSiO2 (Efn

)WkT∆xγSiO2f

(4)

where kT is the thermal energy, f is the frequency, andNtSiO2(Efn

) is the oxide trap density at the quasi-Fermi level,as the approximationNtSiO2(E, x, y, z) = NtSiO2(Efn

), holdswell for the uniform-trap-distribution case [16].

The nature of the (expression tan−1 term) is shown in Fig. 1.Here, ω = 2πf , τ0 is taken as 10−10 s, and the tunneling coeffi-cient (γSiO2 or γSiON) for SiO2 or SiON is taken as 108 cm−1.

MIN et al.: IMPACT OF INTERFACIAL LAYER ON LOW-FREQUENCY NOISE OF HfSiON DIELECTRIC MOSFETs 1461

Fig. 1. Calculation of tan−1(ωτ0 exp(γTox)) for interfacial (SiO2 or SiON)and high-k dielectric (HfSiON) layers as a function of oxide thickness.f = 1−100 Hz and τ0 = 10−10 s.

For Tox > ∼ 2.5 nm, the first term in the bracket convergesto π/2 and the second term will be close to zero in the1–100 Hz range.

In a multilayered gate stack of an IL and a high-k dielectric(see Fig. 2), since traps may reside in either layer, the tunnelingdistance, trapping time constant, and trap density should bedifferent. In theory, the trap occupancy in the dielectric shoulddepend on the occupancy of the traps in the IL, since the trappedcharge in the IL might screen the effect of the trapped chargefurther in the dielectric, or, if the traps are not independent, theoccupancy of one trap might affect the energy level of the other.However, for simplicity, we will assume these fluctuations to beindependent. The PSD S∆Nit(x, f) is then written as [18]

S∆Nit(x, f) =

Ec∫Ev

W∫0

TIL∫0

4NtIL(E, x, y, z)∆xft(1 − ft)

× τIL(E, x, y, z)1 + ω2τ2

IL(E, x, y, z)dzdydE

+

Ec∫Ev

W∫0

THK+TIL∫TIL

4NtHK(E, x, y, z)∆xft(1−ft)

× τHK(E, x, y, z)1+ ω2τ2

HK(E, x, y, z)dzdydE

=NtIL (Efn

)WkT∆xγILf

2π

×[tan−1 (ωτ0 exp(γILTIL)) − tan−1(ωτ0)

]

+NtHK (Efn

)WkT∆xγHKf

2π

×[tan−1 (ωτ0 exp (γHK(THK + TIL)))

− tan−1 (ωτ0 exp(γHKTIL))]

(5)

where NtIL(E, x, y, z) and NtHK(E, x, y, z) are the corre-sponding oxide trap densities in the IL and the high-k dielectric,respectively, τIL(E, x, y, z) and τHK(E, x, y, z) are the corre-sponding trapping time constants, and γIL and γHK are the

Fig. 2. Cross section of a high-k dielectric MOSFET with the coordinatesystem.

tunneling coefficients. The tan−1 term is shown in Fig. 1 fordifferent layers in the stack at f = 1−100 Hz. It is clear thatif IL is thick, say TIL > ∼ 4−4.5 nm, the second term (high-kpart) of the above expression will be negligible and the equationreduces to the conventional expression for the unified model

S∆Nit(x, f) =NtIL (Efn

)WkT∆xγILf

(6)

and

SId=

kTI2dγILfWL

(1Ninv

+ αscµeff

)2

NtIL (Efn) . (7)

In the event that the IL is thin, say TIL < 1 nm, the first term (ILpart) in (5) will be negligible and the equation can be written as

S∆Nit(x, f) =NtHK (Efn

)WkT∆xγHKf

(8)

and

SId=

kTI2dγHKfWL

(1Ninv

+ αscµeff

)2

NtHK (Efn) . (9)

For all other cases where the IL thickness lies between 1 and4 nm, all the terms in (5) remain significant to yield

S∆Nit(x, f) =WkT∆x

f

[NtIL (Efn

)γIL

A+NtHK (Efn

)γHK

B

]

(10)

and the unified model for high-k MOSFETs can be given by

SId=kTI2dfWL

(1Ninv

+ αscµeff

)2

×[NtIL (Efn

)γIL

A+NtHK (Efn

)γHK

B

](11)

where NtIL(Efn) and NtHK(Efn

) are trap densitiesat the quasi-Fermi level in the IL and high-k layers,respectively. In (11), A = (2/π) tan−1(ωτ0 exp(γILTIL))and B = (2/π)[tan−1(ωτ0 exp(γHK(THK + TIL)))−tan−1(ωτ0 exp(γHKTIL))]. Since NtHK(Efn

) is at least oneorder of magnitude higher than NtIL(Efn

) [12], [13], [15], andγIL is higher than γHK, the IL term cannot dominate until the


Fig. 3. Typical 1/f noise spectra of the HfSiON dielectric MOSFET forIL = 1.8 nm, and L × W = 0.14 × 10 µm2. The device is biased atVd = 50 mV, Vg–Vt = 0.3−0.5 V. The peaks are 60-Hz harmonic pickup.

interfacial-layer thickness is about 2.5 nm (see Fig. 1). Thismeans that whenever the IL thickness is greater than 2.5 nm,the contribution to LF noise from the high-k stack will benegligible.

III. NOISE MEASUREMENTS ON

HfSiON-DIELECTRIC MOSFETS

Noise measurements were performed on four lot splits cor-responding to different SiON IL thicknesses of 0.8, 1.0, 1.5,and 1.8 nm. The HfSiON film thickness was ∼ 3 nm for alldevices. The equivalent oxide thickness (EOT) was 1.24, 1.33,1.46, and 1.66 nm. The gate electrode is polysilicon. Details ofthe fabrication process can be found elsewhere [5].

All devices reported here have W = 10 µm with L =0.13−1 µm. Prior to the noise measurement, dc characteri-zation was done to obtain the threshold voltage Vt, channelconductance gd = ∂Id/∂Vd, transconductance gm = ∂Id/∂Vg ,etc. The electron effective mobility µeff was obtained from stan-dard split capacitance–voltage (C–V ) measurements performedon 10 × 10 µm2 devices.

A typical LF-noise measurement system, consisting of alow-noise battery-operated preamplifier and a dynamic signalanalyzer, was used. To minimize the system noise, a custom-designed battery-powered biasing circuitry and a shielded low-noise probe station were utilized. Drain-voltage noise datawere recorded for a constant Vd = 0.1 V while sweeping thegate overdrive (Vg–Vt) from 0 to 0.9 V. Background noisewas measured by setting Vd = 0 V at a certain Vg and wassubtracted from the total measured noise at the same Vg andVd = 0.1 V to obtain the net device noise. For meaningfuldata, we made sure that the background noise was at least twoorders of magnitude less than the device noise for all measuredfrequencies [19]. The noise coefficient δ and the drain-voltagenoise spectral density at 1 Hz (SVd

(f) = SVd(1 Hz)/fδ) were

extracted from the spectrum obtained at each bias condition.The drain-current noise spectral density was then calculatedusing SId

(1 Hz) = g2d · SVd(1 Hz).

Fig. 4. Current noise PSD varies as L−3, at the same bias condition [Vd =0.1 V, (Vg–Vt) = 0.3 V].

Fig. 5. SId/I2

d was found to follow (gm/Id)2, as predicted by the unifiedmodel.

It was observed that, for all measurements, the frequencyexponent δ ranged from 0.8 to 1.1. When δ < 1, the con-tribution of traps closer to the Si–dielectric interface is pre-dominant in noise. It has been shown that the SiO2 (andpresumably SiON also) trap density has a U-shaped distributionfrom the Si valence-band edge to the conduction-band edge.Therefore, even if the trap concentration is uniform spatiallyinto the dielectric, an artificial nonuniformity is encounteredby the tunneling electron due to the band-bending effect causedby the gate bias. Since the trap density is higher at the bandedges, the higher gate bias would lead to more contribution tofluctuations from the traps further into the dielectric, and henceδ > 1 [20]. If the same is true for HfSiON traps, a similar effectshould be observed. In addition, the trap-density differencebetween the high-k dielectric and IL would cause “humps” inthe spectral form, as observed by Simoen et al. [21]. None ofthese, however, were apparent in our data.

IV. RESULTS AND DISCUSSIONS

Fig. 3 gives a typical voltage noise PSD for a 0.14 × 10 µm2

HfSiON dielectric nMOSFET in the 1–100-kHz range. Thedevice is biased at Vd = 50 mV with Vg–Vt varying from


Fig. 6. Normalized noise as a function of gate overdrive voltage for deviceswith different SiON thicknesses. The thinner the IL thickness, the higher thenoise, suggesting the dominant contribution from traps lying in HfSiON.

Fig. 7. Comparison of the contribution from carrier-number-fluctuation andcorrelated mobility-fluctuation terms. 1/Ninv is higher than αscµeff in thewhole bias range, especially in the low-gate-bias region.

0.3 to 0.5 V. Fig. 4 shows current noise PSD (SId(1 Hz))

plotted as a function of effective gate length for the same biasconditions (Vg–Vt = 0.3 V, Vd = 0.1 V) and was found to beproportional to 1/L3 as expected [22]. For further verification,SId/I2d and (gm/Id)2 are plotted against the drain current to

verify that they follow the same trend (Fig. 5). The 1/Id de-pendence is also shown on the figure to check against Hooge’sformulation of bulk mobility fluctuations due to lattice scatter-ing [23]. Based on the results depicted in Fig. 5 and repeatedon all tested devices, the unified noise model was adopted toextract the oxide trap density. Similar results can be found in theprevious report [12].

Fig. 8. Extraction of the Nt and µc0 fitting parameters, shown for thedevices with IL thickness of 0.8 nm and variable channel length. (Vg–Vt) =0.15−0.9 V, Vd = 0.1 V, and f = 1 Hz.

Fig. 9. Effective oxide-trap-density range and average values plotted as afunction of IL thickness. Nt was found to be inversely proportional to the ILthickness.

TABLE ITERM B FOR DIFFERENT INTERFACIAL-LAYER THICKNESSES

AT DIFFERENT FREQUENCIES

For appropriate comparison of noise in devices with differentphysical dimensions, normalization was done with respect toEOT, effective gate length, and drain current, following theunified model. Fig. 6 shows the normalized device noise asa function of gate overdrive for devices with different ILthicknesses and gate lengths. In Fig. 6, the highest noise wasexhibited by the devices with the thinnest IL and the normalizednoise magnitude decreased for thicker ILs. This would suggest


TABLE IIEFFECTIVE TRAP DENSITY Nt WITH THE CORRECTION (Nt(WC)), Nt WITHOUT CORRECTION (Nt(W/OC)), AND THE FITTING PARAMETERS µc0

that the majority of the noise causing traps reside in the high-kfilm or at the HfSiON/SiON interface for these devices.

It is known that the screened scattering coefficient is afunction of inversion charge density [24], [25]. Based on this,Vandamme and Vandamme derived [26]

SId=kTI2dγfWL

(1Ninv

+µeff

µc0

√Ninv

)2

Nt (12)

where µc0 is a fitting parameter. µeff and Ninv are the channeleffective mobility and inversion charge density, respectively.We extracted µeff and Ninv from standard split C–V measure-ments [27]. Wherever appropriate, correction for gate leakagecurrents was performed following [28]. γ is the tunnelingcoefficient whose value is acquired from an earlier report [12],and Nt is the total effective oxide trap density representingthe combined defect density from the interfacial and high-klayers. In (11), we know that the IL term will dominate whenTIL > 2.5 nm. Since 0.8 ≤ TIL ≤ 1.8 nm in these devices

NtIL (Efn)

γILA� NtHK (Efn

)γHK

B (13)

the first term in brackets in (11) can be neglected. Therefore, asingle value for γ (of HfSiON) is used.

The unified-noise-model expression involves two terms:the carrier-number-fluctuation (1/Ninv) and the correlatedmobility-fluctuation (µeff/µc0

√Ninv) terms. Fig. 7 compares

these two terms with respect to (Vg–Vt) in the strong inversion.In all cases, the carrier-number-fluctuation term is higher thanthe correlated mobility-fluctuation term and more so for lowgate overdrives. Thus, the unified model can be approximatedas a pure number-fluctuation model in the weak inversion [29].SId

(1 Hz) is plotted as a function of gate overdrive in Fig. 8,along with the fitted curves obtained by choosing appropriatefitting parameters µc0 and Nt. Fig. 9 shows the range foreffective oxide trap density (Nt) versus the interfacial-layerthickness. As depicted by the solid line, an inverse proportion-ality exists between Nt and IL thickness.

It should be noted that (12) was derived assuming term B in(11) to be unity. The extracted noise parameters in Fig. 9 are

Fig. 10. Effective oxide trap density Nt extracted with and without correctionterm B.

based on this assumption. However, this may not be valid forultrathin high-k films. Table I lists calculated values of termB for different IL thicknesses and frequencies (THK = 3 nm).Table II gives the fitting parameter µc0 and the effective trapdensity Nt values before and after the correction, using (11)and (12). It is clear that whenever TIL ≥ 4 nm, B ≈ 0 and thetraps in high-k dielectric no longer contribute to LF noise. Onthe other hand, the term B assumes less-than-unity values forTIL < 4 nm. Taking this into account, the average effective trapdensity Nt is recalculated and plotted in Fig. 10. The modifiedmodel predicts a steeper increase in effective trap density withdecreasing interfacial-layer thickness.

V. CONCLUSION

The UFNM was modified to include the effect of traps frommultiple gate-dielectric stacks. The effective trap density thusextracted was found to be higher than the trap density extractedusing the single dielectric model, which implies that the latterunderestimates the defect density. LF-noise characterization ofHfSiON dielectric MOSFETs with different interfacial-layer(SiON) thicknesses was done. The IL thickness was foundto have a profound effect on the noise magnitude. Of thetwo fluctuation mechanisms that make up the unified model,the carrier-number fluctuations dominated over the correlatedmobility fluctuations in these devices.


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Bigang Min received the B.S. degree in electricalengineering from the University of Electronic Sci-ence and Technology of China, Chengdu, in 1990,the M.S. degree from Alfred University, Alfred, NY,in 2002 and the Ph.D. degree from the University ofTexas at Arlington, in 2005.

From 1990 to 1996, he was with Chengdu Seam-less Steel Tube Company as an Electrical DesignEngineer, responsible for steel tube test equipmentsystem design. From 1996 to 2000, he was an Elec-tronic Engineer at Marconi Medical working on CT

and X-ray biomedical instrumentation. In 2002, he joined the Electrical Engi-neering Department, University of Texas at Arlington. His current research areais investigation of noise on high-k dielectric MOSFETs, SPICE modeling, andanalog circuit design.

Siva Prasad Devireddy (S’01) received the Bach-elor’s degree in electrical engineering from Chai-tanya Bharathi Institute of Technology (CBIT),Hyderabad, India, in 2000, and the Master’s degreein electrical engineering from University of Texas atArlington, in 2002. Currently, he is working towardthe Ph.D. degree with the Noise and ReliabilityGroup, University of Texas at Arlington, investigat-ing flicker noise in MOSFETs with high-k dielectricmaterials and metal gates.


Zeynep Çelik-Butler (S’84–M’87–SM’98) receivedthe dual B.S. degrees in electrical engineering andphysics from Bogaziçi University, Istanbul, Turkey,in 1982, and the M.S. and Ph.D. degrees in elec-trical engineering from the University of Rochester,Rochester, NY, in 1984 and 1987, respectively.

She was an IBM Predoctoral Fellow from 1983to 1984, and an Eastman Kodak Predoctoral Fellowfrom 1985 to 1987. She joined the Department ofElectrical Engineering, Southern Methodist Univer-sity (SMU) in 1987 as an Assistant Professor, and

was tenured and promoted to Associate Professor in 1993. She was the holderof the J. Lindsay Embrey Trustee Assistant Professorship from 1990 to 1993.She served as the Assistant Dean of Graduate Studies and Research at SMUfrom 1996 to 1999 and was a Professor of electrical engineering from 1999to 2002. Currently, she is a Professor of electrical engineering and Directorof Nanotechnology Research and Teaching Facility at the University of Texasat Arlington. Her research interests include noise in electronic and photonicdevices, microelectromechanical systems, infrared, and pressure sensors. Sheis the holder of four patents, four book chapters, and over 140 journal andconference publications in these fields.

Dr. Çelik-Butler served in various technical committees including the1988–1989 IEEE-IEDM’s and Annual Symposia on Electronic Materials,Processing and Characterization (1989–1992) and International Conference onNoise in Physical Systems and 1/f Fluctuations (ICNF) (1993, 1999, and2001). She was the General Chair of TEXMEMS II Workshop. She was one ofthe Founding Editors of Fluctuation and Noise Letters and served in this capac-ity until 2005. Currently, she serves in the executive committee for TEXMEMSworkshops and is a member of the International Advisory Committee for ICNF.She is a Distinguished Lecturer for the IEEE Electron Devices Society. She hasreceived several awards including the IEEE Dallas Section Electron DevicesSociety Outstanding Service Awards (1995 and 1997), IEEE Electron DevicesSociety Service Recognition Award (1995 and 2003), Outstanding ElectricalEngineering Graduate Faculty Awards (1996, 1997, and 2001), and SouthernMethodist University Sigma Xi Research Award (1997). She is a member ofEta Kappa Nu and the American Physical Society.

Ajit Shanware (S’99–A’00–M’03) received the M. Tech. degree from theIndian Institute of Technology, Mumbai, India, in 1994, and the Ph.D. degreefrom Duke University, Durham, NC, in 1999, both in electrical engineering.

He joined Texas Instruments Incorporated, Dallas, TX in 1999 and iscurrently working in the Silicon Technology Development organization on thereliability of the gate dielectrics and electrode materials.

Luigi Colombo (M’99) is a Texas Instruments (TI) Fellow at TI, Dallas,responsible for the high-k and metal gate activities. He has over 25 years ofexperience with multicomponent material systems including II–VI compounds,high-k dielectric capacitor materials, high-k gate-dielectric materials, andmetal gates for CMOS devices.

Keith Green (S’88–M’93) received the B.S. degree in electrical engineeringfrom the University of Delaware, Newark, in 1998, and the M.S. and Ph.D.degrees in electrical engineering from the University of Florida, Gainesville, in1990 and 1993, respectively.

He joined Texas Instruments (TI) Incorporated, Dallas, TX in 1993. Hecurrently works in TI’s SPICE Modeling Laboratory where he oversees andparticipates in SPICE model production and development projects that rangeover a wide variety of semiconductor component types.

J. J. Chambers, photograph and biography not available at the time ofpublication.

M. R. Visokay, photograph and biography not available at the time ofpublication.

Antonio Luis Pacheco Rotondaro (M’01) was bornin Sao Paulo, Brazil, in 1965. He received the B.S.and M.Sc. degrees in electrical engineering from theEscola Politecnica of the Universidade de Sao Paulo,Sao Paulo, in 1987 and 1990, respectively, the M.Sc.and Ph.D. degrees in electrical engineering from theKatholieke Universiteit Leuven, Leuven, Belgium, in1992 and 1996, respectively.

From 1988 to 1991, he was an Assistant Pro-fessor in the Electrical Engineering Department,Universidade de Sao Paulo where he researched

sputtering deposition of titanium and cobalt for silicide formation. From1991 to 1992, he worked on the characterization and modeling of silicon-on-insulator (SOI) devices operating at low temperatures at the InteruniversitairMicroelektronica Centrum (IMEC), Leuven. From 1992 to 1996, he workedon contamination control in submicrometer CMOS technologies at IMEC.In 1996, he joined Texas Instruments Incorporated, Dallas, where he hasbeen working on front-end-of-the-line advanced process development andprocess integration for the 0.25-µm, 130-nm, 90-nm, and 65-nm technolo-gies. He is also an Adjunct Professor at the Southern Methodist University(SMU), Dallas. His research interests are on strained silicon, high-k gatedielectrics, metal gates, and high-performance CMOS technologies. He isthe holder of 29 U.S. patents and has authored and coauthored more than80 technical papers related to the above fields.

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Impact of interfacial layer on low-frequency noise of HfSiON dielectric MOSFETs