Impact of I O Buffer Configuration

8/8/2019 Impact of I O Buffer Configuration

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Impact of I/O buffer configurationon the ESD performance of a 0.5pm CMOS process

T.Nikolaidis, C.Papadas, M.Varrot, P.M ortini and G.Pan anakakis2

1 SGS-THOMSON Microelectronics,850, rue Jean Monnet - B.P. 16 - 3892 1 Crolles cedex - FranceFax:+ 33 76 92 64 44 Phone:+ 33 7 6 92 64 00

2L.P.C.S. -E.N.S.E.R.G23,rue des m artyrs - B.P. 257 - 38016 Grenoble cedex 1 - FranceFax:+ 33 76 85 60 70 Phone:+ 33 76 85 60 39

Abstract:The purpose of this paper is to

comment on the ESD performance of variousI/O buffer configurations implemented with ageneral purpose, triple-metal, silicideddiffusion, 0.5pm LD D CMOS process. Morespecifically, several U 0 configurations arestudied and, in addition to that, the influenceof specific process steps (i.e. over-dopedp-well) to the ESD performance are alsoaddressed. Finally, it is demonstrated that theconfiguration which guarantees an ESDperformance over 8kV consists of a clampformed on an over-doped p-well between padand Vss, a diode in-between pad and Vdd anda similar clamp between the power andground supplies.

1. IntroductionThe Electro-Static Discharge (ESD),

widely recognized as one of the majorreliability threats of the microelectronicsindustry, becomes more and more severe asthe devices scale down [1,2]. Moreespecially, in the case of the advancedsubmicron CMOS processes, the ESD hasbecome a critical reliability concern, mainlydue to the smaller geometrical parameters(oxide thickness, junction depth) as well as tothe impact of some advanced technologicaloptions (graded junctions, silicided difi sio ns )[3,4]. Since an ESD pulse applied to an ICleads to irreversible damage, robust clampdevices have been developed, in order toincrease the ESD performance [5,6,7]. Thesedevices play the role of protection

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components by evacuating the dischargecurrent to ground and limiting the overstressvoltage t o safe values.

The purpose of this paper is to studythe impact of standard clamp devices,fabricated with classical or specific processsteps (over-doped p-well) and implemented indifferent 1/0 uffer configuration schemes, o nthe ESD performance of a 0.5pm CMOSprocess. Section 2 deals with the descriptionof the clamp devices and the different I/Obuffer configurations used in theseexperiments as well as with the presentationof the experimental set-up. The results and adiscussion on the ESD behavior of thestressed buffers are reported in the section 3followed by the conclusion (section 4).

2. Test structures and e xperimental set-up.The test structures used throughout

this study have been fabricated with a generalpurpose, triple-metal, silicided diffusion,0.5pm LDD CMOS process. Two clampdevices have been considered. The first one isa thin oxide, n-channel, LDD-free, MOSFET(hereinafter refered as CLI), with a 0.5pmchannel length (L), 155pm width (W), adistance between the silicide edge and thediffusion edge in the drain (DS) of 8pm andwith the gate and the source connected toground [SI, while the second one is a

field-oxide gateless n-channel MOSFET(hereinafter refered a s C L2), w ith L = l pm,W=15!5pm and DS=8pm. In order to studythe influence of the substrate dopingconcerktration on the ES D performance, bo thCL1 and CL2 have been fabricated: i) in aClassical P-Well (CPW), with a dopingconceritration of about 2* l O ~ m - ~nd ii) inan Over-Doped P-Well (ODPW), with adoping concentration of about 108 ~m -3.

The above described CL1 and CL2structures, implemented either in CPW orODPW, constitute the main ESD protectioncomponentsof the examined input and outputbuffers. For noise considerations, the Vddpower supply has been split to external(Vdd e) and internal (Vddi) as well as the Vssground rail (Vsse: external ground, Vssi:internal ground). The location of CL1 andCL2 between the I/O pad and the power andgroun d rails, in combination with the locationof prlotection diodes, led to different 1/0buffer configurations. In the case of inputbuffers (see Fig. l), the first configuration(11) consists of the com ponen ts 1, 2 and 3,which are the main clamp, a 400Qnon-silicided resistor and a P+/N-well dioderespectively. A second configuration (12)consists of the I1 with the addition of tw oP+/N-well diodes between the pad and thepow er supplies (Vdd e and Vddi), com ponen ts1, 2, 3, 4 and 5 in Fig.1. A third inputconfiguration (13) is similar to the second one

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has a main clamp (component 4,Fig. 2 ) inparallel with the draidsubstrate diode of theNMOS pull-down transistor. A fourthconfiguration (04) consists of two identicalclamps located between pad and Vssi(component4,Fig. 2) and between Vdde andVssi (component 5, Fig. 2). Finally, the lastconfiguration (05 ) is similar to the 0 4 withan additional diode (component 3, Fig. 2) inparallel with the PMOS. Unless otherwisespecified, the NMOS output transistorparameters are L=lpm, W=8*30pm andDS=8pm. The above I/O configurations aresummarized in the Table 1.

I1I2I3

Input Compone nt Output Component1 config. 1 (see Fig.1) 1 config. 1 (see Fig. 2) 11 , 29 3 0 1 1, 2

1 , 2 , 3 , 4 , 5 0 2 1, 2, 31, 2, 3 , 4 , 5,6 0 3 L 2 , 4

0 4 1, 2 ,4 , 50 5 1 , 2 , 3 , 4 , 5

step-stressed with HB M pulses up to failurewhich is defined as an excess leakage currentof lOnA at 3.3V. This failure criterioncorresponds to the first significant change inthe I(V) characteristic of the stressed buffer.The incremental step for successive stresses is1kV. Each stress consists of three HBMpulses generated by a comm ercial HBM testerwhich conforms to the specifications of the

norm lum STD 883C 3015.7. Differentstress conditions have been applied on the YOpads with respect to the ground (Vsse andVssi) or to the power supplies (Vdde andVddi). The evaluation of the ESDperformance of every I/O configuration isbased on the monitoring of the leakagecurrent.

3. Results and discussion3a. Input buffers

Table 2 summarizes the ESD failurelevel of the three input configurations fordifferent stress conditions: i) positive pulseswith respect to Vsse (+/Vsse), ii) positivepulses with respect to Vssi (+/Vssi) and iii)negative pulses with respect to Vdde(-/Vdcle). It results that for the configuration11,WE: obtain the poorest performance, sincethe oinly available current path during thedischarge is through the clamp 1, whichconstitutes the energy absorbing component.ThereFore, this clamp determines the ES Dperformance of the input buffer, whenpositive pulses are applied on the pad withrespect to the ground rails, while for -/Vddestresses, this clamp is forward biased and thedischarge current goes to ground through theline capacitance. For this stress condition theESD performance depends on the robustnessof the output buffers connected between the

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power and ground rails. In the high currentregime both CL1 and CL2 work as lateralNPN Bipolar Junction Transistors @JT) inthe snap-back mode [9]. The static I(V)snap-back characteristics of these clamps(Figs. 3 and 4) have been traced using the4 45 Semiconductor Parameter Analyzer andthe main snap-back parameters (avalanchevoltage Va, triggering voltage Vtr andcurrent Itr, snap-back voltage Vsb andcurrent Isb) have been extracted. Table 3reads the extracted snap-back parameters aswell as the ESD performance of the stressedclamp, which corresponds t o positive stresseswith respect to Vssi. As it is clearly shown inFigs. 3 and 4 as well as in Table 3, ODPWclamps exhibit a significant decrease of theavalanche and triggering voltages, incomparison with clamps implemented inCPW. Therefore, the ODPW process optionresults in a faster activation of the standardprotection devices. On the o ther hand, despitethe fact that the lateral BJT gain in ODPW islower than in CPW [lo], resulting in adifference Vtr-Vsb smaller in ODPW than inCPW, the snap-back voltage Vsb is lower forclamps implemented in ODPW for the chos endoping levels. As a consequence, under stressconditions, the dissipated heat will be lowerin ODPW clamps. Furthermore, since thefailures observed in both CL1 and CL2 can beattributed to local thermal breakdown [1 13,

80.0

60.0

the ODPW clamps will fail at a higher criticaltemperature due to the increased substratedoping [12]. Consequently, the ESDperformance of the ODPW clamps will behigher in comparison with CPW clamps, as itis clearly shown in the Table 3 . All of theabove reasons demonstrate that the OD PW isan efficient technological option suitable forprotecting thin gate oxides and small coretransistors, while offering a high ESDperformance.

-

0

ODPW

Fig. 3 Snap-back c haracteristic of CL 1

Ev40.0

20.0

0.0

I -1

--

Fig. 4 Snap-back characteristic of CL2

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I I Va I Itr I Vtr I Isb I Vsb I Failure)'CL l ODPW 7.1 35 8.2 36 6.1 6lCL2 ODPW 7 37 8 .3 38 6.2 5CLl CPW 11.6 16 12.4 17 6.6 4

(CL21 CPW ( 1 1 . 5 ) 15 ) 1 2 . 5 ) 16 1 6 . 8 I 3 1Table 3 Main clamp snap-back parameters

Returning back to Table 2, it isobserved that the ESD performance of theconfiguration I2 is higher than the

throu,gh the forw ard biased diode makes thetwo clamp devices (components 1 and 6, Fig.1) to be effectively in parallel, thus doublingth e ESD performance (configurations I1 andI3 in Table 2). I t is worth noticing, thataccording to the experimental results (Table2), ithe ODPW structures guarantee aperformance higher than 8kV.

corresponding performance of the inputbuffers with the I1 configuration, in the case 3b. Ohtp ut buffersof +/V sse as well as +/Vssi stress conditions. Table 4 shows the ESD performanceThis is due t o th e fact that the additional of the examined outp ut buffer configurationsdiode between pad and Vdde, in series with for different stress conditions. In the case ofthe large line capacitance between Vdde and self-protected output buffers (01 and 0 2Vsse, create s a second path for the discharge configurations), the highest performa nce iscurrent. Since the failure location is still th e observed when applying positive pulses withclamp device (component 1 , Fig. l ) , the fact respect to the external ground (+Ns se). As itthat there is a discharge current component has been mention ed previously, for noisethrou gh t he line capacitance leads t o an consilderations, the sourc es of all the NMOSincrease o f the ESD failure level. Obviously, pub1-clown transistors ar e co nnected to afor -/Vdde stresses, the diode 4 (Fig. 1) is separate bus Vsse, while the sources of theblocked leading to the same ESD interrial buffers as well as th e substrate of th eperformance with the I1 configuration. NMOS pull-down transistor are connected to

Adding a se cond clamp in-between an internal "clean" bus Vssi. Fo r the abovethe power (Vdde) and ground (Vssi) rails stress conditions, the substrate of the NMOS(configuration I3), th e ESD performa nce pull-dow n transistor is floating andfbrther increases for all the examined stress const:quently during the transient phase,conditions. Mor e precisely, when positive capacitive coupling [131 between the drainpulses are applied on the pad with respect to and the subs trate leads to a uniform turn onthe ground rails, during the transient phase, of most of the NMOS fingers , hus justiQingcapacitive coupling between pad and Vd de a high performance. Furthermore, comparing



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0 2 with 0 1 for L=lpm, the addition of adiode (component 3, Fig. 2) in parallel withthe PMOS transistor hrther increases theperformance, since the series resistance of thediode 3 is significantly lower than the seriesresistance of the inherent PMOS diode(formed by the PHdrain and the N-wellcontact) [14]. In addition, the configuration0 2 with a L=0.7pm channel length NMOSpull-down transistor exhibits a higher ESDperformance, which could be attributed to abetter capacitive coupling between the drainand the substrate of this transistor, induced bythe channel length L reduction.

For the configurations 0 1 and 02, theworst stress condition is when applyingpositive pulses with 'respect to Vssi. In thiscase the draidsubstrate diode of the NMOStransistor is unprotected. Consequently,putting a clamp between pad and Vssi(component 4, Fig. 2), the ESD performancesignificantly increases, since this clampsnaps-back and dissipates the major part ofthe ESD current. The results presented in theTable 4 (configuration 0 3 ) clearly veri@ thisissue.

A higher ESD performance isobtained, when adding a second clamp(component 5, Fig. 2) between Vdde andVssi (configuration 0 4 ) . As it has beenpreviously mentioned in the case of input

during the transient phase both clamps areeffectively in parallel. The addition of thediode 3 (Fig. 2), parallel with the PMOS(configuration 0 5 ) fhrther improves theresults. Besides, the addition of the supplyclamp 5 (configurations 0 4 and 0 5 ),significantly improves the ESD performancein the case of -N dd e stresses.

Based on the results of the Table 4, itis observed that the ODPW structures give ahigher performance in com parison withclamps implemented in CPW, for the sameoutput buffer configuration. Since this resultconcerns also the input buffers, clampsfabricated in ODPW are suitable for anoverall ESD reliability.

4. ConclusionThe impact of different I/O buffer

configurations as well as the effect of thespecific process steps, i.e. over-d oped p-well,on the ESD performance of a 0.5pm CMOSprocess has been analyzed. It is demon stratedthat the ODPW is a very eficienttechnological option for overall ESDreliability and that the configuration thatguarantees a performance over 8kV consistsof a clamp formed on an over-d oped p-well, adiode in between pad and Vdd and a similarclamp between the power and ground

buffers, the performance increases, because supplies.

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References1.C.Duvvury and A.Amerasekera, "ESD: apervasive reliability concern for IC technologies",Procceedings of the IEEE, vol. 81, pp690-702,may, 19932.L.R.Ave1-y~"IC technology: where it is goingand what it means for the ESD industry",EO SESD symposium proceedings, vol. 7, ppl-5,19853.C.DuvvuryY R.N. Rountree, H.J.Stiegler,T.Polgreen and D.Corum, "ESD phenomena ingraded junction devices", IRPS, pp7 1-76, 19894.K.Cher1, G.Giles and D.Scott, "Electrostaticdischarge protection for one micron CMOSdevices and circuits", IEDM, pp484-487, 19865 .C.Duvvury, R.N.Rountree and L.S.White, "A

10.Y Fong and C.Hu, "High-current snapbackcharacteristics of MOSFET's", IEEE T-ED, vol.37, pp2101-2103, September, 199011 A.Amerasekera, L.van Roozendal,J.Abderhalden, J.Bruines and LSevat, "Ananalysis of low voltage ESD damage in advancedCMOS processes", EOSESD symposiumproceedings, vol. 12, pp143-150, 199012.A.Amerasekera, L.van Roozendal J .Bruinesand F Kuper, "Characterization and modeling ofsecond breakdown in NMOST's for the extractionof ESD-related process and design parameters",IEEE T-ED, vol. 38, pp2161-2168, September,199113 T.Polgreen and A.Chaterjee, "Improving theESD failure threshold of silicided NMOS output

summary of most effective electrostatic discharge transistors by ensuring uniform current flow",protection circuits for MOS memories and their EOSESD symposium proceedings, vol. 11observed failure modes", EOS/ESD symposiumproceedings, vol. 5 , pp181-184, 1983 14.C .Duw ury7 R.N.Rountree, Y.Fong andG.L.R.Avery, "Using SCR's as transient R.A.Mc:Phee, "ESD phenomena and protection

pp 167-174,1989

protection structures in integrated Circuits'I, issues in CMOS output buffers", IRPS,EOSESD symposium proceedings, vol. 5 , pp174- 180, 1987pp177-180, 19837.C.Duwu1-y and C.Diaz, "Dynamic gatecoupling of NMOS for eficient output ESDprotection", IRPS, pp141-150, 19928.F.Kuper7 .Bruines and J.Luchies, "Suppressionof soft failures in a submicron CMOS process",EOSESD symposium proceedings, vol. 15,~ ~ 1 1 7 - 1 2 2 ,9939.N.Khurana, T.Maloney and W.Yeh, "ESD onCHMOS devices - equivalent circuits, physicalmodels and failure mechanisms", IRPS,~ ~ 2 1 2 - 2 2 3 ,985



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- Configuration Technological(see Table 1) parametersCL1

CPW CL2

ODPW CL2CPW CL2

CL 11

CL1

CL1CL2CLl

CPW c12CL1

ODPW c12

I2 4ODPW

I3

Configuration(see Table 1)

ES D failure level (kV)+ N s s e + Nss i -1Vdde

4 4 87 5 > 8

>8 >8 > 8>8 >8 > 8

0 10 2

ODPWCPW

ODPW

0 3

0 4

0 5

CL1 7 7 >8CL2 6 7 > 8CL1 8 >8 >8CL2 > 8 >8 >8

1.5.9EOS/ESD SYMPOSIUM95-42

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Impact of I O Buffer Configuration