III-V/Si heterojunctions for steep

subthreshold slope transistors

Katsuhiro Tomioka1,2, Takashi Fukui1

1. Graduate School of Information Science and Technology, and Research Center

for Integrated Quantum Electronics (RCIQE), Hokkaido University, JAPAN

2. Japan Science and Technology Agency (JST) - PRESTO

Contents 1. Background 2. Formation of III-V nanowire-channel on Si –

Selective Area Growth 3. Steep-slope transistor using III-V NW/Si

heterojunction 4. Summary

Third Berkeley Symposium on Energy Efficient Electronic Systems,

Berkeley, 29th. Oct. 2013

CMOS technologies

Slide 2

Gate

Materials

Transport

2016 2021 2026

Fin (Tri-gate)

Si/SiGe

Diffusion

2011

Future transistor => Low power & High speed

0.8 - 0.5 V

0.5 – 0.3 V

Sub 0.3 V

VDD

III-Vs/Ge

GAA (or SGT)

Tunnel (steep SS)

Beyond CMOS

Year

III-V MOSFETs: High-speed and low power switching

Slide 3

[Supply voltage] : A x [ON-state voltage] Operation power [Supply voltage]2

[ON-state voltage] = [Subthreshold swing (SS)] х

Digits of [ON-state current – leakage current]

Decreasing in leakage current of CMOS FinFET, Surrounding-gate (or GAA) structure*

Boosting up ON-state current with low voltage

III-V materials with high electron mobiloity

InGaAs FinFET

M. Radosavljevic et al.,

IEDM Tech. Dig.

(2011) pp.765

InGaAs GAA

K. Tomioka et al.,

Nature 488

(2012) pp.189

InGaAs vertical FET

J. J. Gu et al.,

IEDM Tech. Dig.

(2012) pp.529

Carrier transport limits subthreshold slope (SS). Power scaling

SS = 2.3kBT/q ~ 60 mV/dec

I DS

(A

/mm

)

Gate voltage, VG (V) 0 0.5 1.0

10-8

10-6

100

10-2

10-4

SS

=60 mV/dec

Steep-slope

< 60 mV/dec

OFF

ON

FET with SS = 60 mV/dec,

ON-state voltage = [60 x 4] mV= 0.24 V

Supply voltage = 4 x [ON-state voltage]

= 4 x 0.24 = 0.96 V

FET with SS = 30 mV/dec,

ON-state voltage = 0.12 V

Supply voltage = 4 x 0.12 = 0.48 V

Sub-30 mV/dec is required for a

0.5 V-operation & Si-CMOS

compatibility

Toward high-speed and low power switching

Steep-slope transistors

5

(I) Tunnel FET (TFET)

(II) Impact ionization FET

exp( )eff

BI AV

Based on BTBT or Zener tunneling

qVeff

Ec

Ev

Efp Efn

Ec

Ev

3 *1/ 2

sec2 2 1/ 2

2

4cross tion

g

q mA A

E

*1/ 2 3/ 24

3

gm EB

q

1 1

2

1 1ln10( ) ln10( ) ln10

eff eff

eff

eff gs gs eff gs

dV dVB dS V

V dV dV V dV

The tunneling current : ( : Electrical field)

M. T. Björk et al., APL 90, 142110 (2007)

Based on impact ionization

(III) Mechanical switch

V. Pottet al., IEEE Proc. 98, 2076 (2010)

CMOS-compatibility Low ON-current

Steeper SS High Voltage/E

Based on MEMS/NEMS

Steepest SS ~ 0 mV/dec.

High Voltage &

Large Size

6

JST-PRESTO project: 1

2009.10 – 2013.3

7

SiO2 sputter

EB lithography and wet chemical etching

MOVPE growth

Growth condition

Precoursors: TMGa, TMAl, TMIn, TBP, AsH3

Growth temp.(Tg): 750 ºC (for GaAs nanowires),

850 ºC (for GaAs/AlGaAs nanowires)

625 ºC (for InP nanowires)

540 ºC (for InAs nanowires)

Substrates: GaAs(111)B, InAs (111)B, InP (111)A and Si (111)

Design of mask-

openings

Growth time: 20 min. (GaAs nanowires),

10 min. (GaAs/AlGaAs core-shell nanowires)

Formation of nanowire-channel Selective-area MOVPE

diameter : 100 nm

SEM image

(1) AsH3 treatment at 400C

(2) Low temperature growth at 400C

with FME (In -> H2 -> As -> H2 ,,,)

(1) (2)

(I) InAs NWs on Si

K. Tomioka et al.,

Nano Lett., 8 (2008) 3475

Growth sequence

(1) AsH3 treatment at 400C

(2) Low temperature growth at 400C

SEM image

Diameter : 75 nm, length : ~ 3 µm

Growth sequence

(1) (2)

(II) GaAs NWs on Si

K. Tomioka et al.,

Nanotechnology 20 (2009)145302

(1) (2)

(III) InGaAs NWs on Si

1 mm

Diameter : 100 nm, length : ~ 1 µm

K. Tomioka et al.,

IEEE JSTQE 17 (2011) 1112

Nature 488 (2012) 189

SEM image

1 mm

III-V nanowires on Si(111)

K. Tomioka et al. paper submitting

Misfit dislocation in III-V NW/Si interfaces

III-V NWs on Si: No defects such as threading dslocation/APD

Misfit dislocation can be suppressed by decreasing NW-diameter

Steep-slope transistor using

III-V NW/Si heterojunctions

InAs nanowire

Silicon

Slide 11

Band discontinuity automatically formed without precise in-situ doping.

Band diagram I-V curve

n+-Si

Si-doped

InAs NW

Sb-doped n+-Si(111)

: 2 x 1019 cm-3

n-InAs n+-Si

EF

0.81 eV

0.06 eV

EC

EV

Unique phenomenon in III-V/Si junction

Ohmic: Ti/Au

p+-Si

Si-doped

InAs NW

B-doped p+-Si(111)

: 4 x 1019 cm-3

p+-Si n-InAs

EF

0.4 eV

0.1 eV

Veff

EC

EV

Staggered Type-II

Tunnel transport across III-V/Si junction

Nanowire: 250

Diameter : 80 nm

InGaAs nanowire/Si InAs nanowire/Si

K. Tomioka et al. paper submitting

・ p++-Si => Esaki tunnel (BTBT)

・ p-Si => Large Zener tunnel

Tunneling transport can be induced by

controlling the Fermi-level in Si

Slide 13

Device concepts of TFET using III-V/Si

Si

III-V

n+-III-V

(I)

(II)

(i) Si(111) substrate

Surrounding-gate structure

III-V NW => channel region Tunnel : Si => III-V

(III)

(IV)

(ii) Si(100) substrate

Fit to conventional CMOS platform

III-V NW => source region Tunnel : III-V => Si

Slide 14

Improved Device procedures

NW growth high-k dielectric (ALD)

Gate-metal (sputter)

RIE – Gate defining

RIE etch-back

(oxide/metal/polymer)

Polymer resin

Spin-coating

Polymer coating

-> RIE etch-back

Drain/Source metal

Evaporation

RIE- Drain defining

n+-Si(111) n+-Si(111) n+-Si(111)

n+-Si(111) n+-Si(111) n+-Si(111)

n+-InAs

Undoped InAs

SiO2 BCB

BCB BCB

Ti/Pd/Au

Ni/Au

LG

Tungsten

Hf0.8Al0.2O

InGaAs NW Vertical FET (Surrounding-gate FET)

Drain current was moderately modulated by VG with very thin EOT.

On/Off ratio, Ion/Ioff : ~ 105

Threshold voltage, VT : 0.30 V

Subthreshold slope : 68 mV/dec

Drain current, ID : 0.07 mA/μm @ VDS of 0.5 V

DIBL : 33 mV/V

Transconductance: 215 μS/μm @ VDS of 0.5 V

K.Tomioka & T. Fukui, DRC Conf. Dig. pp.15 (2013)

Scaling of the NW-HEMT structure

K. Tomioka et al.,

IEDM Tech. Dig. (2011) pp.

773

K. Tomioka et al.,

Nature 488 (2012) pp. 189

100 nm K. Tomioka & T. Fukui

DRC Conf. Dig. pp.15 (2013)

EOT dependency of SS/DIBL

EOT = 0.70 nm => minimum SS with large DIBL

Interface state density, Dit : 1.8 – 3.8 × 1012 cm-2eV-1

Average SS = 68 mV/dec, DIBL : 33 mV/V

LG = 150 nm

LGD = 50 nm

Origin of steep-SS and low Dit Crystal structure relates to the steep SS

Surface roughness : 5 MLs

Stacking fault (Twin plane) is formed 3ML-period

Channel transport: {-110} plane

along <111> direction

Monolayer (ML)

Perc

enta

ge (

%)

(111)A

(111)B

(-110)

(111)B

(111)A

Macroscopic: (-110) => Microscopic: (111)A/(111)B

(111)A: stable surface – less Ga-oxide => low Dit

(111)B: As termination during NW-growth

etched-off by alkaline solution

(-110) surface of the NW: almost (111)A surface

Origin of steep-SS and low Dit

20

Transfer characteristics

Switching behavior was observed at reverse bias condition.

Vth : -0.25 V, SS : 116 mV/dec, On-state current : 1 nA @ 0.5 V On/off ratio : 7 x 104

Output characteristic

Reverse region

Vgs = 0.50 V

SS

= 116 mV/dec

First demonstration of InAs/Si TEFT K.Tomioka et al.,

APL 98 (2011) 083114

Passivation effect of InAs/Si TEFT SA-MOVPE of InAlAs/InAs core-shell NW

K.Tomioka et al.,

ECS Trans. 41 (2011) 61

Source (S) :

p+-Si => Ground

(n ~ 1x1019 cm-3)

Gate (G):

undoped InAs region

(n ~ 1016 cm-3)

Drain (D):

n+-InAs region (n ~ 1018 cm-3)

Nanowire : 80 nm in diameter

1.4 µm in height

On/off ratio : ~ 105

SS : 120 mV/dec,

On-state current : 2.3 μA/μm @ 0.5 V

ON-state current was enhanced

to 40 times than that of bare InAs

NW channel.

=>

Enlargement of capture area &

passivation effect

22

To realize steep-slope ( < 60 mV/dec)

transistor, gate (VG) and drain-source

(VDS) voltage should be biased only

Gate-region and heterointerface.

RG-D

RInAs(Gate)

RSi/InAs

Series resistances of the TFET

RG-D should be lowered.

RInAs(Gate)& RSi/InAs should be higher. LG-D

exp( )eff

BI AV

Based on BTBT or Zener tunneling

( : Electrical field) 3 *1/ 2

sec2 2 1/ 2

2

4cross tion

g

q mA A

E

*1/ 2 3/ 24

3

gm EB

q

1

G

2

GD

G

dV

dB

dV

dV

V

110ln

logId

VdSS

ξ

ξ

ξDS

DS

Lower RG-D Higher R(Gate)& RSi/InAs

Smaller NW-diameter reduces

Number of misfit dislocation.

Enlargement of drain metal

coverage.

Device optimization

300 nm

Si-doped

InAs NW

Undoped

InAs NW

Si-doped

InAs NW

Undoped

InAs NW

I DS

(A

/μm

)

10-13

10-12

10-9

10-10

10-11

10-8

Gate voltage, VG (V) 0 0.5 1.0 -0.5

TFET

APL 98 (2011) 083114

SS

= 104 mV/dec

10-7

10-6

Improved TFET

Diameter: 30 nm

21 mV/dec

VDS = 1.00 V

Steep turn-on behavior

was obtained by the

optimizations.

SS: 21 mV/dec (~ 4 dec.)

ION/IOFF: ~ 106

ION: 0.9 μA/μm @ VDS = 1.0 V

Tunneling: Pure tunneling w/o defect state & with defects

First demonstration of steep-SS K.Tomioka et al.,

VLSI Symp. Tech. Dig. (2012) 47

Nanowire SGT: SS ~ 60 – 70 mV/dec.

InAs NW/Si junction transistor: SS ~ 21 mV/dec,

point slope 12 mV/dec.

steep-SS K.Tomioka et al.,

VLSI Symp. Tech. Dig. (2012) 47

Slide 25

Designs for steep-slope behavior 2

[II] R2 : NW-resistance/ undoped region

Higher R2 => Increasing in effective VG

=> Tunneling occurs under lower VDS & VG.

MOVPE of InAs: unintentional (carbon) doping

=> strongly depends on MOVPE system

The carrier concentration : ~ 1016 cm-3

Pulsed doping for compensation in nanostructure

30 nm

1 nm

Zn atom Single Zn atom in InAs NW (d: 30 nm, h: 1 nm)

Net carrier concentration: 4.7 x 1017 cm-3

Conventional doping can not form intrinsic

layer by compensation effect.

Pulsed doping technique

The benefit of the technique:

Formation of intrinsic layer in unintentional doped nanostructures.

2NW

thbiInGaAs0d

2/dq

VVεε4N

SBHφ

biSBH Vφ

Effect of Zn-pulsed doping

Carrier concentration:

Undoped InGaAs NW: 5.2 x 1016 cm-3

Zn-compensated InGaAs NW: 7.8 x 1015 cm-3

Pulsed doping reduced net carrier concentration, close to intrinsic.

K.Tomioka et al.,

Paper submitting

Compensation doping in undoped InAs nanowire-channel

Formation of pseudo-intrinsic layer: Positive VT-shift

VT: -0.42 => 0.60 V maintaining steeper SS

(i) Zn pulse 1 sec.

VT ~ 0.32 V

(ii) Zn pulse 2 sec.

VT ~ 0.70 V

SS ~ 32 mV/dec

On/Off ~ 105

SS ~ 32 mV/dec

On/Off ~ 105

ION ~ 1 nA/μm @ VDS=0.50 V

Vt-shift: channel doping K.Tomioka et al.,

Paper revised

Si/III-V Heterojunction

nm-scale heterojunction naturally forms

band-discontinuities.

N-TFET

P-TFET

K.Tomioka et al.,

VLSI Symp. Tech. Dig. (2012) pp. 47

K.Tomioka and T. Fukui

APL 98 (2011) pp. 083114

SS ~ 21 mV/dec SS ~ 104 mV/dec

InAs nanowire/Si heterojunction

Steep-slope transistors

Demonstration of steep-sloep SS Issues

Poor gate-bias controllability in InAs MOS Formation of pure intrinsic layer in InAs

Flexibility of III-V nanowire channels

Steep-SS transistor using InAs/Si heterojunction

Undoped

200 nm

Zn-doped

(p-type)

n+-Si

P-channel TFET using p-InAs/n-Si junction was successfully demonstrated.

ON current: 0.1 μA/μm (VDS = VG = -1.0 V) SS: 186 mV/dec

p-InAs: 800 nm in height

Undoped: 400 nm

Diameter: 40 nm

Next challenge: Demonstration of steep subthreshold-slope behavor

Optimization of Zn doping technique while suppressing interdiffusion of Zn atoms

P-channel TFET using InAs nanowire/Si junction

K.Tomioka et al., Paper submitting

Slide 31

Source (S) :

p+-Si => Ground

(n ~ 1x1019 cm-3)

Gate (G):

undoped InAs region

(n ~ 1017 cm-3)

Drain (D):

n+-InAs region (n ~ 1018 cm-3)

Nanowire : 70 nm in diameter

1.4 µm in height

Device structure of Vertical steep-SS transistor

K.Tomioka and T. Fukui, paper submitting

n+

p+

Positive VDS

=>

Reverse bias

condition

VDS

VGS

Channel resistance should be high to generate tunnel current

under lower gate-bias.

Non-dope：1 x 1017 cm-3

Zn-doping：1 x 1016 cm-3

Transfer characteristics Output characteristics

SS: 260 mV/dec => 80 mV/dec ON/OFF: ~ 103 => 104

IOFF = 100 fA/ μm @ VD = 0.50 V

Parasitic leakage current is effectively suppressed.

Steep-SS region appeared under low VDS.

InGaAs NW/Si heterojunction

Channel-length scaling effectively suppress parasitic leakage current.

Scaling of channel-length, Lch

The scaling enhanced drain-current (x 100)

Scaling of Zn-compensated InGaAs NW-channel

Steep SS region became wider in case shorter Lch.

Summary

Proposal & demonstration of TFET using

a new III-V/Si heterojunction

Key points for steep turn-on switching

for the vertical TFETs have been shown.

[I]:

[II]:

Integration of III-V NWs on Si

Unique heterojunction

Vertical TFETs using InAs NW/Si

heterojunction have been demonstrated.

Steep-slope (SS < sub-30 mV/dec)

switching

have been demonstrated.