III-V MOS: Planar and Fin Technologies

2014 MRS Spring Meeting, April 23, San Francisco.

M.J.W. Rodwell, UCSB

III-V MOS: S. Lee, C.-Y. Huang, D. Elias, V. Chobpattanna, J. Law, A.C. Gossard, S. Stemmer, UCSB; T. Kent, A. Kummel, UCSD;P. McIntyre, Stanford.

Transport Modeling: P. Long, S. Mehrotra, M. Povolotskyi, G. Klimeck, Purdue

Why III-V MOS ?

III-V vs. Si: Low m*→ higher velocity. Fewer states→ less scattering → higher current. Can then trade for lower voltage or smaller FETs.

Problems: Low m*→ less charge. Low m* → more S/D tunneling.Narrow bandgap→ more band-band tunneling, impact ionization.

1018 1019 1020 1021

N-InAs

10-10

10-9

10-8

10-7

10-6

10-5

Electron Concentration, cm-3

0.2 eV

B=0.3 eV

step-barrier

B=0 eV

0.1 eV

Landauer

Con

tact

Res

istiv

ity,

cm

2

Excellent contacts now.Better contacts feasible.

Why III-V MOS ? → important but less well-known reasons

Y-K. Choi et al, VLSI Tech. Symp., 2001

-6

-5.5

-5

-4.5

-4

-3.5

-3

-2.5

-2

eV fr

om v

acuu

m le

vel

SiInGaAs HfO

2TiO

2

Ec

Ev

r ~20

r ~40

http://nano.boisestate.edu/research-areas/gate-oxide-studies/

nm-precise epitaxy, large heterojunction DEC→ 1nm thick channels

Dielectric-channel interface:Large DEC, no SiO2 at interface→ smaller EOT

(1nm hard for SOI)

III-V MOS: how small can we make Lg ?

Planar UTB FETs might just scale to 10nm Lg:nm epitaxial control of channel thicknesshigh-energy barriers (AlAsSb)possibly thinner high-K than in Si.vertical spacer greatly aids short-channel effectssimulations suggest that, with spacers, even S/D tunneling is OK.

And with ALE techniques, few-nm-Lg III-V finFETs are also feasible.

The Key question:

...can we get high Ion ,

Compared to Silicon MOS,...

..and low Ioff , and low VDD ,

...at a VLSI-relevant (8-10nm) technology node ?

Performance @ e.g. 35nm is not important !

Small S/D pitch, not just small Lg, is essential !

Intel 22nm finFETs Jan, IEDM 2012

-0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.510-6

10-5

10-4

10-3

10-2

10-1

100

101

DIBL = 50 mV/Vat VT = 100 A/m

SSmin

~ 65 mV/dec. (at VDS

= 0.1 V)

SSmin

~ 68 mV/dec. (at VDS

= 0.5 V)

Lg = 55 nmVDS = 0.1 to 0.7 V0.2 V increment

Cur

rent

Den

sity

(mA

/m

)

Gate Bias (V)

Leakage, short-channel effects, performance comparisons

off-state leakage mechanisms:

Band-band tunneling, S/D tunneling, impact ionization

Small S/D contact pitch MOS-HEMT with large contact pitch vs.

Lateral depletion region reduces severity of most short-channel effects (not VLSI-compatible)

Leakage, short-channel effects, performance comparisons

Band-band tunneling, S/D tunneling, impact ionization

Lateral depletion region reduces severity of most short-channel effects (not VLSI-compatible)

Lin, IEDM2012

UCSB

off-state leakage mechanisms:

Small S/D contact pitch MOS-HEMT with large contact pitch

~20 nm gate-drain space

no lateral gate-drain space

Examples from literature: gate-drain lateral spacers Chang et al.: IEDM 2013:

150nm gate-drain spacer Lin et al. : IEDM 2013: 70nm S/G, G/D spacers

T. W. Kim et al., IEDM2012~16 nm S/G, G/D spacers

D. H. Kim et al., IEDM2012~100nm S/G, G/D spacers

We must build devices with small S/D pitch.contact pitch ~ 3 times lithographic half-pitch

(technology node dimension)

Small S/D pitch hard to realize if we require ~20-50nm lateral gate-drain spacers !

Vertical spacers: reduced leakage -- at small feasible S/D pitch

vs.

III-V MOSFET development process flow

While our fast development process flow does not provide a small S/D contact pitch,in manufacturing, the vertical spacer will provide a small S/D contact pitch.

III-V MOSFET development process flow

Simple, 4-day, 16nm process→ learn quickly !

Low-damage: avoids confusing dielectric characterization.

Process otherwise not scaled: large gate overlap, large S/D contact separations.increases gate leakage, increases access resistance.

Process is not now self-aligned, but could be made self-aligned.

Critical dimensions are scaled: Lg, channel thickness, (N+ S/D):G separations.

TEM Cross-Section, Summer 2013

High Transconductance III-V MOSFETS: 2013 VLSI Meeting

8 nm channel (5 nm/3 nm InAs/In0.53Ga0.47As) and ~4 nm HfO2 high-k dielectric At time, record gm over all gate lengths (i.e. 2.45 mS/μm at 0.5 VDS for 40 nm-Lg)

0.01 0.1 10.4

0.8

1.2

1.6

2.0

2.4

2.8

This work

D.-H. Kim2012 IEDM(VDS=1V)

D.-H. Kim2011 IEDM(HEMT)

Y. Yonai2011 IEDM

T.-W. Kim2012 VLSI

Intel2009 IEDM

M. Egard2011 IEDM

J .J . Gu2012 IEDM

D.-H. Kim2012 IEDM

at Vds=0.5V

Gate length (m)

Gm

_max (m

S/m

)

-0.2 0.0 0.2 0.4 0.60.00.20.40.60.81.01.21.41.61.8

Gm

(mS/m

)

Curr

ent D

ensi

ty (m

A/m

)

Gate Bias (V)0.0

0.4

0.8

1.2

1.6

2.0

2.4

2.8 40 nm 70 nm 90 nm

VDS = 0.5 V

Ni

3.6 nm HfO2

5 nm InAs

3 nm In0.53GaAs

In0.52AlAs Lg ~40 nm

60 nm

Lee et al, 2013 VLSI Symposium, May

High Transconductance III-V MOSFETS: 2013 VLSI Meeting

93 mV/dec @ 500 nm-Lg but > 400 mV/dec @ 40 nm-Lg.Extremely Poor Short-Channel Effects

-0.2 0.0 0.2 0.4 0.610-5

10-4

10-3

10-2

10-1

100

101

VDS=0.5 V

40 nm 70 nm 90 nm

VDS=0.05 V

Curr

ent D

ensi

ty (m

A/m

)

Gate Bias (V)

0.1 1

100

200

300

400

500VTh : Linear extrapolation at Gm_max Threshold Voltage (V)

VDS= 0.5 V VDS= 0.05 V

Gate length (m)

Subt

hres

hold

Sw

ing

(mV/

dec)

0.0

0.1

0.2

0.3

0.4

0.5

-0.2 0.0 0.2 0.4 0.610-6

10-5

10-4

10-3

10-2

10-1

100

101

VDS=0.05 VVDS=0.5 V

SS ~ 93 mV/dec at VDS=0.05 V

Curr

ent D

ensi

ty (m

A/m

)

Gate Bias (V)

Lee et al, 2013 VLSI Symposium, May

Reducing Leakage: 3nm vs. 8nm High-Field Spacer

resultReduced off-state leakage, improved short-channel effects, very high gm & Ion.

Reducing Leakage: 9nm vs. 7.5nm Channel Thickness

resultBetter electrostatics, higher bandgap→ Reduced Ioff, improved subthreshold swing, slightly less gm & Ion.

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.70.0

0.4

0.8

1.2

1.6

2.0

Curr

ent D

ensi

ty (m

A/m

)

Drain Bias (V)

Ron = 280 Ohm-m at VGS = 1.0 V

VGS = -0.4 V to 1.0 V 0.2 V increment

Vertical spacers: some details

Minimum S/D contact pitch: depends upon regrowth angle we need to work on this. [010] gate orientation should help

Spacer sidewalls are gated through the high-K.

Capacitance to UID sidewalls is negligible. about 0.2 fF/m << the ~1.0fF/m interelectrode capacitances.

Capacitance to N+ contacts layers is large. easy to eliminate: low-r sidewall spacer.

Deliberate band offset between spacer & channel compensates offset from strong quantization in channel.

Much Better Results to be Reported

To reduce off-state leakage:thinner channels (quantization)→ less band-band tunnelingthinner channels & dielectrics → better electrostatics

To increase on-state current:thinner channels & dielectrics

Much better results to be reported:Lee et al.: EDL (in press)Lee et al.: 2014 VLSI Symposium (June)

Thin Wells: Gate Leakage ?In a thin InGaAs well, does the bound state energy rise

to the point that dielectric leakage becomes high ?

?

-6

-5.5

-5

-4.5

-4

-3.5

-3

-2.5

-2

eV fr

om v

acuu

m le

vel

SiInGaAs HfO

2TiO

2

Ec

Ev

r ~20

r ~40

1.5nm well: (Ebound-Ec)=0.5 eV Brar data agrees well with:1) Boykin, APL, 21 March 1994 (simulations)2) Recent simulations by Povolotskyi (Purdue)3) Recent unpublished UCSB FET data

Thermal Emission from Source over Back Barrier.

InGaAs-InAlAs barrier is 0.5 eV

Fermi level is 0.3~0.5 eV aboveconduction-band in the N+ source.

Barrier is only 0.1~0.25 eV above Fermi level.

Thermionic emission flux:

barrier. eV 0.2for mA/ 5

)/)exp((*)/(2

2/1

kTEENmkTqJ cfcthermionic

Need increased barrier energy.

Again, effect is less evident in MOS-HEMTsdue to larger N+ S/D separation.

10 nm InGaAs channelHigh-K

AlAsSb Back Barrier: Stops Barrier Thermal Leakage

25 nm i-AlAsSb

SI InP sub375 nm i-InAlAs

60 nm N++ MOCVD RG

InGaAs

60 nm N++ MOCVD RG

InGaAs

10 nm InGaAs channelHigh-K

SI InP sub

400 nm i-InAlAs

60 nm N++ MOCVD RG

InGaAs

60 nm N++ MOCVD RG

InGaAs

InAlAs back barrier

AlAsSb back barrier

InAlAs back barrier

AlAsSb back barrier

AlAsSb layer: 0.5 eV increase in barrier.Expect ~108:1 less thermal emission from source.

130227C

120807A

AlAsSb Back Barrier, P-doped layer, better isolation

-0.4 -0.2 0.0 0.2 0.4 0.60.0

0.4

0.8

1.2

1.6

2.0

2.4

Gm

(mS/m

)

Curr

ent D

ensi

ty (m

A/m

)

Gate Bias (V)0.0

0.4

0.8

1.2

1.6

2.0

2.4VDS = 0.1 to 0.7 V0.2 V increment

-0.4 -0.2 0.0 0.2 0.4 0.60.0

0.4

0.8

1.2

1.6

2.0

2.4

Gm

(mS/m

)

Curre

nt D

ensi

ty (m

A/m

)

Gate Bias (V)0.0

0.4

0.8

1.2

1.6

2.0

2.4VDS = 0.1 to 0.7 V0.2 V increment

InAlAs FET: 88 nm Lg, 25 micron drawn Wg, 8 nm InGaAs channel, 60 nm InGaAs Regrowth, 3.2 nm HfO2, 0 deg

resultAlAsSb barrier shows lower off-state current and better SS as compared to P-InAlAs barrier.

AlAsSb FET: 90 nm Lg, 25 micron drawn Wg, 8 nm InGaAs channel, 60 nm InGaAs Regrowth, 3.2 nm HfO2, 0 deg

-0.4 -0.2 0.0 0.2 0.4 0.610-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

SS ~ 115.0 mV at VDS=0.5 VSS ~ 91.8 mV at VDS=0.1 V

VDS = 0.1 to 0.7 V0.2 V increment

Curr

ent D

ensi

ty (m

A/m

)

Gate Bias (V)0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

Curr

ent D

ensi

ty (m

A/m

)Drain Bias (V)

Ron = 388 Ohm-m at VGS = 1.6 V

VGS = -0.2 V to 1.6 V 0.2 V increment

-0.4 -0.2 0.0 0.2 0.4 0.610-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

SS ~ 135.9 mV at VDS=0.5 VSS ~ 99.9 mV at VDS=0.1 V

VDS = 0.1 to 0.7 V0.2 V increment

Curr

ent D

ensi

ty (m

A/m

)Gate Bias (V)

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.70.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

Curr

ent D

ensi

ty (m

A/m

)

Drain Bias (V)

Ron = 344 Ohm-m at VGS = 1.6 V

VGS = -0.2 V to 1.6 V 0.2 V increment

caution: as-draw gate length and gate widths stated. Data not yet corrected for either.

III-V MOS: how small can we make Lg ?Planar UTB FETs might just scale to 10nm Lg:

Unlike Si !nm epitaxial control of channel thicknesshigh-energy barriers (AlAsSb)possibly thinner high-K than in Si.vertical spacer greatly aids short-channel effectssimulations suggest that, with spacers, even S/D tunneling is OK.

And with ALE techniques, few-nm Lg III-V finFETs are also feasible.

Cohen-Elias et al., DRC 2013

FinFETs by Atomic Layer Epitaxy: Why ?

26 / bodybody TT

Electrostatics: body must be thinner than ~Lg /2→ less than 4 nm thick body for 8 nm Lg

Problem: threshold becomes sensitive to body thickness

3bodybodyth TTV

Problem:low mobility unless surfaces are very smooth

Implication: At sub-8-nm gate length, need :extremely smooth interfaces extremely precise control of channel thickness

side benefit: high drive current→ low-voltage, low-power logic

ALE-defined finFET

Fin template: formed by {110}-facet-selective etch→ atomically smoothChannel thickness set by ALE growth→ atomically precise

Cohen-Elias et al., DRC 2013

Images

HfO2

TiN

fin, ~8nm

100

nm fi

n pi

tch

drain

50 n

m fi

n pi

tch

source

channel

10 n

m th

ick

fins,

100

nm

tal

l

Cohen-Elias et al., DRC 2013

Tall Fins for Low-Power, Low-Voltage Logic

Supply reduced from 500mV to 268 mV while maintaining high speed.

3.5:1 power savings ? Circa 2.5:1 when FET capacitances considered.

Low-voltage (near-VT ) operation:low CV2 dissipation, but low current→ long interconnect delays

Increased fin height→ increased current per unit die area→ interconnect charging delays reduced

-0.1 0 0.1 0.2 0.3 0.4 0.510-1

100

101

102

103

104

Vgs

0.1 A/m @ Vgs=0mV

finFET:10:1 height/pitch

I d, A

mps

per

met

er o

f FE

T fo

otpr

int w

idth

1000 A/m @ Vgs=268mV

0 0.1 0.2 0.3 0.4 0.50.1

1

10

100

1000

Vgs

planar FET

0.1A/meter @ V

gs=0mV

1000 A/meter @ V

gs=0mV

I d, A

mps

per

met

er o

f FE

T ch

anne

l wid

th

What is next ?

29

In progress: thinner dielectrics, better contacts, better alignment→ greater Ion

10nm Lg FETs: prove that spacer kills S/D tunneling leakage. ultra-thin InGaAs & InAs channels low off-current

If we can: InAs ALE-finFETs @ 10nm Lg→ high performance 110-oriented PMOS finFET→ performance approaching NMOS

(end)

Backup slides