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Integrierte Hard- und Softwaresysteme
IHS 3: Test of Digital Systems
R.Ubar, A. Jutman, H-D. Wuttke
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
2
Objective of the Course
SpecificationHardware description
languages (VHDL)
ImplementationFull custom, standard
cell, gate arrays
ManufacturingCMOS
VLSI Design Flow
TestingAutomatic test
equipment (ATE), structural scan testing
Built-in Self-Test
VerificationSimulation. Timing analysis,
formal verification
Test
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
3
Introduction: Test Tools
Test
System
Fault dictionary
System model
Test generation
Fault simulation
Test result
Fault diagnosis
Go/No go Located defect
Test experiment
Test tools
(BIST)
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
4
Introduction: Quality Policy
Quality policyYield (Y)
P,n
Defect level (DL)
Pa
Design for testabilityTesting
P - probability of a defectn - number of defectsPa - probability of accepting
a bad product
nPY )1( - probability of producing a good product
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
5
Introduction: the Problem is Money?
Cost oftesting
Quality
Cost
Cost ofthe fault
100%0%
Cost of quality
Optimumtest / quality
How to succeed?Try too hard!
How to fail?Try too hard!
(From American Wisdom)
Conclusion:“The problem of testingcan only be containednot solved”
T.Williams
Test coverage function
Time
100%
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
6
Two Approaches to Testing
Testing of functions:
100% will be reached onlyafter 2n test patterns
100% will be reached when all faults from the fault list are covered
0%
Faulty functions
covered by 1. pattern Faulty
functions covered by 2. pattern
50%
75%3. pattern
4. pat. 87,5%
93,75%
100%
100%
Testing of faults
Testing of functions
Testing of faults:
4. pat.Not tested
faults
Faults covered by 1. pattern
2. pattern
3. patttern
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
7
Self-Test in Digital Systems
SoC
SRAMPeripherial ComponentInterconnect
SRAM
CPU
Wrapper
CoreUnderTest
ROM
MPEG UDLDRAM
Test AccessMechanism
Test AccessMechanism
Sink
SoC
BIST Control Unit
Circuitry Under Test
CUT
Test Pattern Generation
Test Response Analysis
Self-Test (BIST) in a component
Source
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
8
Overview
1. Introduction2. Theory: Boolean differential algebra3. Theory: Decision diagrams4. Fault modelling5. Test generation6. Fault simulation7. Fault diagnosis8. Testability measuring9. Design for testability10. Built in Self-Test
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
9
Faults as Test Objectives
Stuck-at 1 fault
&&
1
X1 = 1
X3 = 0 1
y = 0 1X2 = 1
1 0(x3 = 0 1) (y = 0 1)
Output is depending on input change
Y = F(X) = x1 x2 x3
dx3 dyHow to set up the dependency:
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
10
Boolean Derivatives: Definition
Boolean function:
Y = F(x) = F(x1, x2, … , xn)Boolean partial derivative:
Example:
),...,...(),...,...()(11 nini
i
xxxFxxxFxXF
),...0,...(),...1,...()(11 nini
i
xxxFxxxFxXF
),...,...(),...,...()(3131
3
231nn xxxFxxxF
xxxxF
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
11
Boolean Derivatives: Main Properties
Useful properties of Boolean derivatives:
These properties allow to simplify the Boolean differential equation
to be solved for generating test pattern for a fault at xi
If F(x) is independent of xi
ii xXGXF
xXGXF
)()()()(
ii xXGXF
xXGXF
)()()()(
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
12
Faults as Test Objectives
Stuck-at 1 fault
&&
1
X1 = 1
X3 = 0 1
y = 0 1X2 = 1
1 0(x3 = 0 1) (y = 0 1)
Output is depending on input change
Y = F(X) = x1 x2 x3
dx3 x1 x2 x1 = x2 = 1How to set up the dependency:
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
13
Boolean Derivatives: Calculation
316254142321 )))((( xxxxxxxxxxxxy
5
562414233121
5
625414233121
5
625414233121
5
625414233121
5
625414233121
5
))((
)))(((
)))(((
))))((((
xxxxxxxxxxxxx
xxxxxxxxxxxxx
xxxxxxxxxxxxx
xxxxxxxxxxxxx
xxxxxxxxxxxxx
xy
Transformations of the Boolean derivative:
Given: Wanted: 5x
y
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
14
Basics of Theory for Test and Diagnostics
Two basic tasks:1. Which test patterns are needed to detect a fault (or all faults)2. Which faults are detected by a given test (or by all tests)
ALU
&10
0
&1 0
Gate
Multiplier
System Booleandifferential
algebra
Decisiondiagrams
DD
BDD
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
15
Overview
1. Introduction2. Theory: Boolean differential algebra
3. Theory: Decision diagrams4. Fault modelling5. Test generation6. Fault simulation7. Fault diagnosis8. Testability measuring9. Design for testability10. Built in Self-Test
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
16
Binary Decision Diagrams
7654321 )( xxxxxxxy Simulation:
7654321 xxxxxxx0 1 1 0 1 0 0
1y
Boolean derivative:
15427613
xxxxxxxy
y x1
x2 x3
x4 x5
x6 x7
0
11
0Functional BDD
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
17
Binary Decision Diagrams
Shannon’s Theorem:
01)()(
)(
kk xkxk XFxXFx
XFy
xky1
)(kx
XF
0)(
kxXF
Using the Theoremfor BDD synthesis:
Functional synthesis BDDs:
43124321 ))(( xxxxxxxxy
x1y 2432 )( xxxx x2
x3 x4
43xxx3
x4
43 xx
Example:
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
18
Fault Propagation Problem
&1
Path activation
Fault “Stuck-at-1”
0
Fault activation
Correct signal
Error
1 0
Logic gate
1
Pathactivation
FaultStuck-at-0
Fault activation
Correct signal
Error
1 0
7654321 )( xxxxxxxy
x1x2
x3 = 1x4x5x6x7
y
0
0
0 F (X)
Logic circuit
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
19
Fault Propagation with BDD
FaultStuck-at-0
Fault activation
Correct signal
Error
1 0
7654321 )( xxxxxxxy
x1x2
x3 = 1x4x5x6x7
y
F (X)
1
Pathactivation
0
0
0
x1
x2
y
x3
x4 x5
x6 x7
0
11x1
x2
y
x3
x4 x5
x6 x7
0
11
0
Fault propagation through logic circuit with BDD:
0
0
?1
?
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
20
Binary Decision Diagrams
7654321 )( xxxxxxxy Simulation:
7654321 xxxxxxx0 1 1 0 1 0 0
1y
Boolean derivative:
15427613
xxxxxxxy
y x1
x2 x3
x4 x5
x6 x7
0
11
0Functional BDD
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
21
Overview
1. Introduction2. Theory: Boolean differential algebra
3. Theory: Decision diagrams (Higher Levels)4. Fault modelling5. Test generation6. Fault simulation7. Fault diagnosis8. Testability measuring9. Design for testability10. Built in Self-Test
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
22
Structur =>BDDs for Logic GatesElementary BDDs:
1
x1x2x3
y x1 x2 x3&
x2x3
y x1
x1
x2
x3
1x1x2x3
y x1 x2 x3
+x1x2x3
y
x1
x2
x3
y x2 x3
Adder
NOR
AND
OR
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
23
BDDs for Flip_Flops
DC
q c
q’
D
SC
q
R
0')'(
SRqcRqScq
c
q’
S
R q’
R
U
D Flip-Flop
RS Flip-Flop
JK Flip-FlopSJ
q
R c
q’
S
R q’
CK
K
J
U - unknown value
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
24
Synthesis of SSBDD for a Circuit
&
1
1x1
x2
x3
x21
x22y
a
b
))((& 322211 xxxxbay
Superposition of Boolean functions:
Given circuit:
Compare to
Structurally Synthesized BDDs:a by
a x1
x21
b x22
x3
DD-library:
ay x22
x3
y x22
x3
x1
x21
Superposition of DDs SSBDD
b a
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
25
Representing by SSBDD a Circuit
&
&
&
&
&
&
&
12
345
6
7
71
72
73
a
b
c
d
e
y
Macro
y = cyey = cy ey = x6,c,yx73,c,y deybey
y = x6x73 ( x1 x2 x71) ( x5 x72)
Structurally synthesized BDDfor a subcircuit („Macro“) 6 73
1
2
5
7271
y
0
1
To each node of the SSBDD a signal path in the circuit corresponds
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
26
Fault Collapsing
Further reduction of the complexityFault Collapsing:Two faults are considered equivalent if the faulty functions produced by the two faults are equal. Alternatively, the two faults are equivalent if they can be detected by the same tests.(a/0=z/0) b/0=z/0
a/0 and b/0can be dropped
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
27
Fault Collapsing
Further reduction of the complexityFault Collapsing:A fault f is considered to dominate another fault gwhen every test for g is also a test for f.
z/1 dominatesthe fault a/1
Fault z/1 can bedropped
Test vektors{01,10,11}
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
28
Fault collapsing
Equivalence realtionshipsAND-Gate OR- Gate NOT-Gate
Dominance realtionships
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
29
Fault Collapsing
Which faults can be dropped?
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
30
Fault Collapsing
Which faults can be dropped?
Faults: {s/0, s/1, s3/0, s3/1, a/0, a/1, b/0, b/1, s1/0, s1/1, s2/0, s2/1, c/0, c/1, d/0, d/1, z/0, z/1}Local collapsing: {s/0, s/1, s3/0, s3/1, a/1, b/1, s2/1, c/0, d/0, z/1}The faults s/0, b/1, z/1 dominate s3/1, faults s/1, a/1 dominate s2/1. The fault s3/0 is equivalent to c/0. The global collapsed fault list for the circuit is thus {s2/1, s3/1, c/0, d/0}. Hence, by using global fault collapsing number of faults from 18 to 4. This is in effect a 77.78% reduction from the original fault list.
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
31
Fault collapsing
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
32
Fault collapsing
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
33
BDDs/ SSBDDs for Logic Circuits
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
34
Fault List
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
35
SSBDDs with Multiple Inputs
Further reduction of the complexity by SSMIBDDs:Fault Collapsing
&
&
&
1
1
1
1
1
&
&
&
&
1
1
1
1 2
3 4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
210
0
1
18
9 8
21
6 101613
14 11
7
19
15 1217
3 414 11
17
16 13
20
18
2
5 1 151210
84 faults on 42 lines 36 faults on 18 nodes
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
36
Fault Diagnosis with SSBDDs
&
&
&
1
1
1
1
1
&
&
&
&
1
1
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
0
0
1
1
2
14 11
7
19
1217
3 4
14
11
16 13
20
18
2
5 1
15
1210
17
15
9 8
6 10
16
13
1821
Diagnosis tree:
20
Fault detected
16
5
13
17 15 13Fail Fail Fault
located
Fault located
Two strategies possible
1
2
1
2
Efficient effect-cause fault analysis with SSMIBDDs
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
37
Reducing the Complexity by Optimizing BDDs
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
38
BDDs and DDs
SSBDD
mlm
lm,1
m1
m0mT,1
mT,0
lm,0
Root node DD
m
lmlm,1m1
mT,1
Root node
lm,2m2
mT,2
lm,nmn
mT,n
DD
m
lmlm,1m1
mT,1
Root node
lm,2m2
mT,2
lm,nmn
mT,n
Test generation at logic level (BDD)
Test generation at higher levels (DD)
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
39
High-Level Decision Diagrams
• data path and control path on RT-level
• RT level simulation
• Functional units (F1,..,F4)
• Register
• Multiplexer / Demultiplexer
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
40
Register Level Fault Models
K: (If T,C) RD F(RS1, RS2, … RSm), NRTL statement:
K - labelT - timing conditionC - logical conditionRD - destination registerRS - source registerF - operation (microoperation) - data transfer N - jump to the next statement
Components (variables) of the statement:
RT level faults:K K’ - label faultsT T’ - timing faultsC C’ - logical condition faultsRD RD - register decoding faultsRS RS - data storage faultsF F’ - operation decoding faults - data transfer faults N - control faults(F) (F)’ - data manipulation faults
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
41
Fault modeling on SSBDDs
The nodes represent signal paths through gatesTwo possible faults of a DD-node represent all the stuck-atfaults along the corresponding path
&
&
&
&
&
&
&
12
345
6
7
71
72
73
a
b
c
d
e
y
Macro 6 73
1
2
5
7271
y
0
1
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
42
Fault Modeling on High Level DDsHigh-level DDs (RT-level):
R2M3
e+M1
a
*M2
b
R1
IN
c
d
y1 y2 y3 y4
y4
y3 y1 R1 + R2
IN + R2
R1* R2
IN* R2
y2
R2 0
1
2 0
1
0
1
0
1
0
R2
IN
R12
3
Terminal nodes represent:RTL-statement faults: data storage, data transfer, data manipulation faults
Nonterminal nodesrepresent: RTL-statement faults: label, timing condition, logical condition, register decoding, operation decoding,control faults
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
43
Data Path in Digital Systems
R2M3
e+M1
a
*M2
b
R1
IN
c
d
y1 y2 y3 y4
M1 y1 Function 0 M1 = R1 1 M1 = IN
M2 y2 Function 0 M2 = R1 1 M2 = IN
M3 y3 Function 0 M3 = M1+ R2 1 M3 = IN 2 M3 = R1 3 M3= M2* R2
R2 y4 Operation Function 0 Reset R2 = 0 1 Hold R2 = R’2 2 Load R2 = M3
Data Path
Control Path
y x
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
44
Decision Diagram of the Data PathM1
y1 Function 0 M1 = R1 1 M1 = IN
M2 y2 Function 0 M2 = R1 1 M2 = IN
M3 y3 Function 0 M3 = M1+ R2 1 M3 = IN 2 M3 = R1 3 M3= M2* R2
R2 y4 Operation Function 0 Reset R2 = 0 1 Hold R2 = R’2 2 Load R2 = M3
y4
y3 y1 R1 + R2
IN + R2
R1* R2
IN* R2
y2
R2 0
1
2 0
1
0
1
0
1
0
R2
IN
R12
3
R2
R2 + M3
M1
M2
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
45
High-Level Decision Diagrams
R2M3
e+M1
a
*M2
b
R1
IN
c
d
y1 y2 y3 y4
Superposition of High-Level DDs:A single DD for a subcircuit
Instead of simulating all the components in the circuit, only a single path in the DD should be traced
y4
y3 y1 R1 + R2
IN + R2
R1* R2
IN* R2
y2
R2 0
1
2 0
1
0
1
0
1
0
R2
IN
R12
3
R2
R2 + M3
M1
M2
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
46
High-Level Decision Diagrams Applet
• Design of data path and a micro-program (control path) on the RT-level
• RT level simulation
• Fault simulation and test coverage evaluation
• Test generation
• Design for testability and BIST
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
47
High-Level Decision Diagrams Applet
• Micro operation: MUX, F1,…• Control signal: micro operation• Cost: number of gates that
implement a micro operation• Choose between high speed
and low cost
• Implementing an algorithm• F can be transparent / disabled
– Only F2 Automaton– F1, F2, F2 sequence– F1, F2, F3, F4 parallel
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
48
High-Level Decision Diagrams Applet
• Algorithm: average• (A+B)/2
• a) high speed– Max resources– Max parallel
• b) low cost– Min resources– Sequential
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
49
High-Level Decision Diagrams Applet
• Algorithm: average• (A+B)/2
• a) high speed– 2 operation units (F2, F3)– Add and Div in in 1 clock cycle– 4 steps– Cost: 83
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
50
High-Level Decision Diagrams Applet
• Algorithm: average• (A+B)/2
• b) low cost– Only 1 Unit (F4)– 2 clock cycles for operation– 5 clocks – Cost: 73
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
51
High-Level Decision Diagrams Applet
• Algorithm: average• (A+B)/2
• Test
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
52
High-Level Decision Diagrams Applet
• Algorithm: average• (A+B)/2
• To continue the test
• Follow the example at
• http://www.pld.ttu.ee/applets/rtl/rtl_exercises.html
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
53
Decision Diagrams for Microprocessors
I1: MVI A,D A INI2: MOV R,A R AI3: MOV M,R OUT RI4: MOV M,A OUT AI5: MOV R,M R INI6: MOV A,M A INI7: ADD R A A + RI8: ORA R A A RI9: ANA R A A RI10: CMA A A A
High-Level DDs for a microprocessor (example):
Instruction set:
I R3
A
OUT4
I A2R
IN5
R1,3,4,6-10
I IN1,6
A
A2,3,4,5
A + R7
A R8
A R9
A10
DD-model of themicroprocessor:
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
54
Decision Diagrams for MicroprocessorsHigh-Level DD-based structure of the microprocessor (example):
I R3
A
OUT4
I A2R
IN5
R1,3,4,6-10
I IN1,6
A
A2,3,4,5
A + R7
A R8
A R9
A10
DD-model of themicroprocessor:
OUT
R
A
IN
I
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
55
DD Synthesis from Behavioral DescriptionsBEGIN
Memory state: MProcessor state: PC, AC, AXInternal state: TMPInstruction format: IR = OP. A. F0. F1. F2.Execution process: EXEC:
BEGINDECODE OP (
0: AC AC + M[A]1: M[A] AC, AC 02: M[A] M[A]+ 1,
IF M[A]= 0 THEN PC PC + 13: PC A......................................7: IF F0 THEN AC AC + 1
IF F1 THEN IF AC = 0 THEN PC PC + 1IF F2 THEN (TMP AC, AC AX, AX TMP)
ENDEND
Procedural description of a microprocessor
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
56
DD Synthesis from Behavioral Descriptions
Start
AC = AC + M [A] AC = AC + 1PC = A
M [A] = AC, AC = 0
M [A] = M [A] + 1
PC = PC + 1
1
2
3
4
6
5
AC = AX, AX = AC
7
PC = PC + 1
AC = AX, AX = AC
8
9
AC = AX, AX = AC
10
11
OP=0
OP=1
OP=2
OP=3...
OP=7
M[A]=0M[A]=1
F0=1
F0=0F1=1F1=0
F2=0
F2=1
AC=0AC0
F2=1F2=0 F2=1
F2=0
Symbolic execution tree:
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
57
DD Synthesis from Behavioral Descriptions
No Input assertions Output assertions1 OP = 0 AC = AC+ M A2 OP = 1 M A = AC, AC = 03 OP = 2, M A + 1 = 0 M A = M A +1, PC = PC + 14 OP = 2, M A + 1 0 M A = M A + 15 OP = 3 PC = A6 OP = 7, FO=0, F1=0, F2=0 NO CHANGE7 OP = 7, FO=0, F1=0, F2=1 AC = AX, AX = AC8 OP = 7, FO=0, F1=1, AC=0, F2=1 AC = AX, AX = AC9 OP = 7, FO=0, F1=1, AC=0, F2=0 NO CHANGE
Generation of nonprocedural descriptions via symbolic execution
Terminal contexts
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
58
DD Synthesis from Behavioral Descriptions
Input assertions Output assertionsOP = 0 AC = AC+ M AOP = 1 M A = AC, AC = 0OP = 2,M A + 1 = 0
M A = M A +1,PC = PC + 1
OP = 2,M A + 1 0
M A = M A + 1
OP = 3 PC = AOP = 7,FO=0, F1=0, F2=0
NO CHANGE
OP = 7,FO=0, F1=0, F2=1
AC = AX, AX = AC
OP = 7, AC=0,FO=0, F1=1, F2=1
AC = AX, AX = AC
OP = 7, AC=0,FO=0, F1=1, F2=0
NO CHANGE
OPAC AC+M [A]
#0
F0 F2
AC
AX
F2 AC+1
Decision Diagram for AC
0
1
2,3
7 0 0
0
1 1
1
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
59
Hierarchical Modelling on DDs
M=A.B.C.q
1
1
q
xA
0qA
i B’ + C’
#1
qB
i#2
0qA
i A’ + 1
#4
2
1
xB
qC
i C’#3
0qC
i A’ + B’
#5
3
1
xC
qA
i B’ + C’
#5
0qC
i A’ + B’
#5
41
xC
qC
i C’#5
0
B
Ai A’ + B’+C’xA
0
q#5
B’
qB
i B’#5
x1
x2 x3
x4 x5
x6 x7
0
11
0
C
Component:Binary Decision Diagram
System:High-level decision diagram
A small part is simulated at the higher level: to increase the speed of analysis
A small part is simulated at the lower level
Cause-effect analysis well formalized
B’ + C’
Technical University Tallinn, ESTONIACopyright 2000-2003 by Raimund Ubar
60
Fragen