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Germany

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An Implementation Study on Fault Tolerant LEON-3 Processor System

Z. Stamenković

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Outline

• Radiation and fault tolerance

• System description

• Implementation details

• Test results

• Under way

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Reliability Issues in Radiation Environments

• Single-event upset (SEU)

A change of state caused by a charged particle strike to a sensitive volume in a microelectronic device

Alpha particles (helium-4 nuclei) emitted by radioactive atoms found in packaging materials

Thermal neutrons in certain device materials that are heavily doped with 10B

High-energy terrestrial cosmic rays (play a major role)

• SEU-induced latch-up

A failure mechanism of CMOS integrated circuits characterized by excessive current due to parasitic PNPN paths

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Fault Tolerance of LEON-3 Processor

• SEU tolerance by design (Gaisler Research)

Triple-module-redundancy (TMR) on all flip-flops

Three copies of a flip-flop

Two of three voting on output

Register file error-correction (up to 4 errors per 32-bit word)

Cache RAM error-correction (up to 4 errors per tag or 32-bit word)

Autonomous and software transparent error handling

No timing impact due to error detection or correction

Fault-tolerant memory controller

Provides an Error Detection And Correction Unit (EDAC)

Corrects one and detects two errors

• Not immune to SEU-induced latch-up (in present IHP technology)

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LEON-3 Processor System

LEON_3FT Core

8 Reg. Windows

LEON_3FT Core

8 Reg. Windows

FT Memory Controller

FT Memory Controller

8 x

GP

IO8

x G

PIO

GPIOEJTAG

2 kByteI- Cache

2 kByteI- Cache

2 kByteD- Cache

2 kByteD- Cache

AHB APB

1 x 24bitTimer

1 x 24bitTimer

UART 0UART 0

EDAC SRAM

EDAC SRAM FLASHFLASH

Serial 0

Serial 1 UART 1UART 1

Bri

dg

eB

rid

ge

Scan TestScan TestFT Add-onFT Add-on

FT Add-onFT Add-on

Scan-I/F

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• Installation of the release

• Adaptation of the configuration tool (to include IHP’s library)

• Implementation of data and instruction caches

• Logic synthesis of the design

• Implementation of scan chain

• Generation of the chip layout

• Simulation (functional, post-synthesis and post-layout net-list)

• Scan test vectors generation (ATPG)

• Scan test simulation

• Adaptation of testbenches

• EVCD test vectors generation

• Test specification

• Documentation

Implementation Details

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Chip Features

LEON-3

Area (mm2) 22

Number of signal ports 105

Number of power ports 20

Number of scan ports 1 (3)

Transistors (x106) 0.83

Cache Memory (kB) 6

Scanable Flip-Flops (x103) 15

Power/Frequency (mW/MHz) 6.2

Max Frequency (MHz) 160

Cache Array

Size (KB)

No. of Words

Data Width

Address Width

I/D Data 2.5 512 36 of 40 9

I/D Tag 0.5 128 29 of 32 7

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Test System (Gaisler Research)

• Target hardware consists of a small mezzanine with Fault Tolerant LEON-3 device mounted on a development board (Pender Electronic Design)

• Board communicates with a host system (a laptop PC) over one of the on-chip UARTs

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Test Execution (Gaisler Research)

• Heavy-ion-error injection

Chamber with the vacuum of 10-2 mbar

Californium (Cf-252) source

Flux of 25 particles/s/cm2 at the device surface for 3 hours

• “Paranoia” program makes a large number of calculations and registers any computational error or anomaly

• On-chip monitoring logic reported 281 effective SEU errors, of which 99% were corrected

• Cross-section for a memory RAM bit was measured to 7.2x10-8 cm2

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Under Way

Protection against SEU-induced latch-up