Ignou mca mcs 12 solved assignment 2011

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Text of Ignou mca mcs 12 solved assignment 2011

  • 1. Course Code : MCS-012Course Title : Computer Organisation and Assembly Language ProgrammingAssignment Number : MCA(1)/012/Assign/2011Maximum Marks : 100Weightage : 25%Last Dates for Submission : 15th April, 2011 (For January Session) 15th October, 2011 (For July Session)There are four questions in this assignment, which carries 80 marks. Rest 20 marks are for viva voce. You may use illustrations and diagrams to enhance the explanations. Please go through the guidelines regarding assignments given in the Programme Guide for the format of presentation. Answer to each part of the question should be confined to about 300 words.Question 1:(a) Perform the following arithmetic operations using binary signed 2s complement notation for integers. You may assume that the maximum size of integers is of 10 bits including the sign bit. (Please note that the numbers given here are in decimal notation) (3 Marks)i) Add 498 and 260Ans:ii) Subtract 456 from 56Ans: Page 1
  • 2. iii) Add 256 and 255Ans:(b) Convert the hexadecimal number: FA BB C9 into binary, octal and decimal. (1 Mark)Ans1: (FA BB C9)16 = (0110011001001011000111)2Ans2: (FA BB C9)16 = (77735711)8Ans3: (FA BB C9)16 = (16759753)10(c) Convert the following string into equivalent ASCII code Copyright 2001 - 2011. Include ASCII code of spaces between words in the resultant ASCII. Are these codes same as that used in Unicode? (2 Marks)Ans: 43h6fh70h79h72h69h67h68h74h20h28h43h29h20h32h30h30h30h20h32h30h31h31h Character ASCII UNICODE C 43H 0043 o 6FH 006F p 70H 0070 y 79H 0079 r 72H 0072 i 69H 0069 g 67H 0067 h 68H 0068 t 74H 0074 space 20H 0020 ( 28H 0028 c 43H 0043 ) 29H 0029 space 20H 0020 2 32H 0032 0 30H 0030 0 30H 0030 0 30H 0030 space 20H 0020 Page 2
  • 3. 2 32H 0032 0 30H 0030 1 31H 0031 1 31H 0031 Yes the codes are same in ASCII & UNICODE(d) Design a logic circuit that accepts a four digit binary input and creates an odd parity bit, a sign check bit and a more than two zero value test bit. The odd parity bit is created for the four bit data. The sign bit is set to 1 if the left most bit of the data is 1. Zero value bit is set to 1 if three of the input bits are zero. Draw the truth table and use K-map to design the Boolean expressions for each of the output bits. Draw the resulting circuit diagram using AND OR NOT gates. (5 Marks)Ans: Page 3
  • 4. (e ) A sequential circuit has two D flip flops A and B, two inputs x and y and one output z. Flip flops input equations and the circuit output are as follows: (5 Marks) DA = x B DB = y A + x A z=A+B (i) Draw the circuit diagram for the above. ClockX Y CxB A D A CyA A Z CxA B D B CyA+xA B (ii) Tabulate the state table for the flip flops. Present State Next State x y A B A B 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 Page 4
  • 5. 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1(f) Design a floating point representation of 32 bits closer to IEEE 754 format except that the exponent of the representation should be of 4 bits only. You may assume that the mantissa is in normalised form; the exponent bias of 7; and one bit is used for the sign bit. Represent the number (89.125) 10 using this format . (4 Marks)Ans:Question 2:(a) A RAM has a capacity of 64 K 64. (2 Marks) (i) How many data input and data output lines does this RAM need to have? Ans: 64, since the word size is 64. (ii) How many address lines will be needed for this RAM? Ans: 64K = 64 1024 = 65536 words. Hence, there are 65536 memory addresses. Since 65536 = 16 2 it requires 16 bits address code to specify one of 65536 addresses. Page 5
  • 6. (b) Consider a RAM of 256 words with a word size of 16 bits. Assume that this memory have a cache memory of 8 Blocks with block size of 32 bits. For the given memory and Cache in the statements as above, draw a diagram to show the address mapping of RAM and Cache, if direct memory to cache mapping scheme is used. (4 Marks)Ans: Page 6
  • 7. (c) You want to read a file from a disk. Explain how the I/O will be performed if (4 Marks) (i) Interrupt Driven Input/ Output Scheme is used. Ans: With interrupt driven I/O, when the interface determines that the device is ready for data transfer, it generates an interrupt request to the computer. Upon detecting the external interrupt signal, the processor stops the task it is processing, branches to a service program to process the I/O transfer, and then returns to the task it was originally performing which results in the wai