Active RF Devices, Circuits and Systems Summary

Ku Band LC-active 90nm CMOS VCO

Domenico Zito1,2, Domenico Pepe2

1Dept. of Electrical and Electronic Engineering, University College Cork, College Road, Cork, Ireland 2 Tyndall National Institute, Lee Maltings, Dyke Parade, Cork, Ireland

Abstract. A novel 13-GHz LC-active VCO has been implemented in 90nm CMOS technology by ST-Microelectronics. The VCO consists of two complementary cross-coupled pairs, an active LC tank implemented by means of a differential high-Q low-noise active inductor and two p-MOSFET varicaps, and an output buffer stage. The VCO provides a sinusoidal signal with amplitude of -11.3 dBm at 12.72 GHz. The measured phase noise amounts to -105.25 dBc/Hz at 1-MHz frequency offset. The VCO core and the active inductor have a current consumption of 700 µA and 1.8 mA, respectively, from a 1.2-V power supply.

I. Introduction. With the latest advances in the silicon technology, most of all the submicron CMOS, the interests of the industry have been addressed to emerging applications at higher frequency, up to millimeter-waves [1] (e.g. 60-GHz Wireless Video Area Networks, 77-GHz Short Range Radars, etc.). For many of them, the realization of the overall wireless transceiver depends mainly on the opportunity of implementing low-phase noise oscillators, without any additional steps or technological hybridization (e.g. MEMS) in the fabrication process [2-3].

The reduction of the phase noise (PN) in Voltage Controlled Oscillators (VCOs) is dealt with efforts at different levels: technology, design and topology. As for the topology, most of LC-VCO circuit solutions proposed in the literature are originated by the cross-coupled differential pair (CCDP, see Fig. 1) with or without a current tail [4]. All the solutions suffer, more or less, of three main mechanisms responsible of the phase noise performance degradation: the current tail noise, the transistor pair noise, and the thermal noise of the tank parasitic resistance [4]. As for the transistor pair noise, the injection into the tank occurs when both transistors of the pair are switched on [2]. In short, the CCDP acts as in the single-balanced mixer by multiplying for ±1 the tail current (IT). Thus, the noise current generator of each transistor is alternatively switched off ideally for half of the period. At the zero crossing, both transistors are in on state and the CCDP stage can be considered perfectly balanced. In this condition, the source node common to both transistors is ac grounded (i.e. due to the symmetry) and each noise current splits equally into each transistor of the pair. This means that the other half flows through the tank. When the stage has switched completely, the noise current of the on-state transistor does not reach the tank since it is well degenerated by the tail transistor. Unlike the tail noise, the CCDP noise represents typically the most relevant limit to the PN performance [4].

As for the losses in the LC tank, they are in large part due to the losses in the spiral integrated inductors. Therefore, a significant interest has been addressed to the implementation of high quality factor (Q) active inductors [5]. In spite of active inductors are capable of providing very attractive high Q (up to several hundreds), the benefits of this approach based on LC-active tanks is limited by the inherent noise of the active circuitry. This aspect, which is very often neglected, is highlighted in [6] by means of theoretical evaluations. In particular, in [6] we also investigated by simulations some potential solution of LC-active VCO for 5-6GHz applications, but no experimental evidences have been provided yet.

In this paper we report for the first time the design, implementation and experimental characterization of a CMOS LC-VCO based on a high-Q low-noise active inductor and two complementary cross-coupled pairs. In Section II, the 13-GHz LC-active VCO in 90nm CMOS is presented. In Section III, the experimental results are reported and discussed. Finally, in Section IV, the conclusions are drawn.

II. LC-Active VCO. The schematic of the proposed 13-GHz LC-active VCO is shown in Fig. 2. The VCO exploits a topology based on two complementary cross-coupled pairs [7] and an LC-active tank based on the Differential Boot-Strapped Inductor (D-BSI) [8]. The circuit includes also an output buffer to drive properly the standard 50- input impedance of the test equipment, such as the signal source analyzer (SSA). In detail, the VCO core consists of two complementary CCDPs, which provide a higher total equivalent transconductance gmeq with respect to a single CCDP with the same bias current, or the same gmeq for a lower current. Each transistor of the cross-coupled pairs is tailed with its own current source in

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Active RF Devices, Circuits and Systems Summary

order to allow a reduction of the phase noise contribution due to the current noise sources that from the cross-coupled transistor pairs reach the tank [7]. Unlike the others, this topology avoids that the CCDP noise reaches the tank, not only when the circuit is completely switched (as well as for the other solutions), but over the entire period. In fact, when the stage has switched completely, the on-state transistor is well degenerated by the tail transistor and the noise current does not reach the tank, as in the case of Fig.1. At the zero crossing, both sides are in on state and the stage is perfectly balanced. Then the source nodes of each CCDP are virtually grounded (virtual ground is not a prerogative of the negative feedback and it is known that the positive feedback of the cross-coupled pair realizes a virtual short circuit between its two source nodes [9]), but unlike the previous case there is not any path through which the noise currents can reach the tank (they flow entirely into the own transistor itself). Note that, in this topology, the CCDP noise (i.e. the most relevant), would be rejected totally. In practice, the tail transistors are affected also by parasitic capacitances, which reduce further the Norton equivalent impedance (Cdb) and mutual isolation (Cdg and Cgs) and then the rejection is limited to a significant reduction. However, the limited output resistance characteristic of deep-submicron MOSFETs and the parasitic capacitances contribute positively to set the loop gain. Last, it is worth noting that the LC tank is encapsulated within the two complementary cross-coupled differential pairs, for a better immunity to the noise coming from the supply voltage.

The LC-active tank is realized by means of the D-BSI since it allows the implementation of high-Q active inductors characterized by a low power consumption (PC) and low noise contribution, as reported hereinafter. The capacitance of the tank consists of the equivalent parasitic capacitance at the nodes 1 and 2, and includes also a couple of p-MOSFET varicaps for a fine adjusting of the oscillation frequency (no frequency tuning is required in our application [10]).

It is worth mentioning that, despite the cross-coupled pairs exhibit themselves a negative resistance, this approach proposed herein offers the opportunity of avoiding an increase of the transistor size and current consumption of the differential pair just to improve the PN performance. In other terms, the design of the differential pairs can be carried out in order to achieve a higher oscillation frequency (f0) and lower PC,whereas the design of the D-BSI can be carried out in order to achieve a higher Q with an extremely low noise contribution and low PC.

The LC-active VCO has been designed for direct-conversion receiver for passive radiometry in the ISM band 12.75-13.25 GHz (Ku) [10] and fabricated in 90nm CMOS by ST-Microelectronics. The differential (i.e. symmetric) BSI (D-BSI) has been implemented following the design reported in [8]. The simplified schematic is reported in Fig. 3. The circuit exhibits the behaviour equivalent to high-Q inductor between the nodes 1 and 2. The equivalent inductance (L12) and quality factor (Q) of the D-BSI circuit realized stand-alone are reported in Fig. 4. The post-layout simulations (PLS) show that D-BSI exhibits a noise of about –180 dB/ Hz at 13 GHz and an out-of-band peak of about –160 dB/ Hz at 19 GHz (see Fig. 5).

III. Experimental Results. The equivalent inductance (L12) and quality factor (Q) of the D-BSI circuit realized stand-alone are reported in Fig. 4. The micrograph of the test-chip is shown in Fig. 6a. The area is 0.216mm2 (ESD-protected pads inclusive). The measurement setup is shown in Fig. 6c. The test-chip has been characterized on-chip by means of GSGSG microprobes by Cascade and a rat-race microstrip balun (see Fig. 6b) in order to transit from the differential output of the VCO to the single-ended input of the SSA. The frequency spectrum measured by means of the R&S FSUP 26.5-GHz SSA is shown in Fig. 7. The amplitude amounts to 11.13 dBm (3.25 dB test setup loss inclusive) at f0=12.72 GHz. The PN measured by means of the SSA is shown in Fig. 8. The VCO exhibits a PN of -105.25 dBc/Hz at 1-MHz offset, and about -119 dBc/Hz at 3-MHz offset. A fine frequency tuning in the range from 12.72 to 12.93 GHz is obtained by acting on the varicap voltage (VC), as reported in Fig. 9. Fig. 10 reports the PN and f0 versus the bias current (IDC) of the D-BSI. Note the reduction of the PN (about 12 dB) when the D-BSI is switched on. The current consumption of the VCO core and BSI amount to 0.7 and 1.8 mA, respectively, from a 1.2-V supply voltage. Similar performance have been measured on four test-chips. Table I reports the summary of the performance for a comparison with the state of the art (SoA) for CMOS VCOs operating close to the Ku band.

IV. Conclusions. The experimental results and the comparison with the state of the art for CMOS VCOs operating close to the Ku band show, for the first time, that this approach based on LC-active tank implemented by means of the D-BSI allows us to achieve very competitive performance by saving approximately 37.5% of the best state-of-the-art power consumption. These results demonstrate that such an approach is not only possible, but even advisable for the system-on-chip implementation of next-

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Active RF Devices, Circuits and Systems Summary

generation high-frequency transceivers on standard silicon technologies, potentially up to millimetre-wave frequencies.References: [1] A. Niknejad, “60-GHz siliconization”, IEEE Microwave Magazine, vol.11, no. 1, pp. 78-85, Feb. 2010. [2] C. Ameziane, D. Belot, R. Plana, T. Taris, Y. Deval, J.-B. Begueret, “A 64GHz push-push oscillator in 0.13 BiCMOS technology”, European Microwave Conference, Sept. 2009, pp. 401-404. [3] S. Shahramian, A. Hart, A. Tomkins, A. Chan Carusone, P. Garcia, P. Chevalier, S.P. Voinigescu, “Design of a Dual W- and D-Band PLL”, IEEE JSSC, Vol. 46, Is. 5, May 2011 , pp. 1011-1022. [4] A. Lacaita, S. Levantino, C. Samori, “Integrated Frequency Synthesizer for Wireless Systems”, Cambridge Univ. Press, 2007. [5] R. Mukhopadhyay, et al., “Reconfigurable RFICs in Si-based technologies for a compact intelligent RF front-end,” IEEE T-MTT, vol. 53, no. 1, pp. 81–93, Jan. 2005. [6] D. Zito, D. Pepe, “LC-active VCO for Modern Wireless Transceivers”, Int. J. of Circuit Theory and Applications, Wiley, vol. 38, pp.69–84, Feb. 2010. [7] D. Zito, “On exploiting new circuit topologies for the next-generation wireless transceivers at the - and mm-waves”, IEEE Proc. of the International Circuits and Systems Conference NEWCAS 2008, Montreal, 22-25 June 2008, pp. 380–383, invited paper. [8] D. Zito, A. Fonte, D. Pepe, “Microwave Active Inductors” IEEE MWCL, Vol. 19, Is. 7, July 2009, pp. 461–463. [9] T.H. Lee, The design of CMOS radio-frequency integrated circuits, Cambridge University Press, 1998. [10] F. Alimenti, S. Leone, G. Tasselli, V. Palazzari, L. Roselli, D. Zito, “IF Amplifier Section in 90nm CMOS Technology for SoC Microwave Radiometers”, IEEE MWCL, Vol.19, Is.11, pp. 770–773, Nov 2009. [11] B. Park, S. Lee, S. Choi, S. Hong, “A 12-GHz Fully Integrated Cascode CMOS LC VCO With Q-Enhancement Circuit”, IEEE MWCL, Vol. 18, Is. 2, Feb. 2008, pp. 133–135. [12] C.-L. Yang, Y.-C. Chiang, “Low Phase-Noise and Low-Power CMOS VCO Constructed in Current-Reused Configuration”, IEEE MWCL,Vol. 18, Is. 2, Feb. 2008, pp. 136–138. [13] N.-J. Oh and S.-G. Lee, “11-GHz CMOS differential VCO with back-gate transformer feedback”, IEEE MWCL, Vol. 15, Is. 11, Nov. 2005, pp. 733–735. [14] S. Ko, J.-G. Kim, T. Song, E. Yoon, and S. Hong, “20 GHz integrated CMOS frequency sources with a quadrature VCO using transformers”, IEEE RFIC Symposium, June 2004, pp. 269–272. [15] T.K.K. Tsang, M.N. El-Gamal, “A high figure of merit and area-efficient low-voltage (0.7-1 V) 12 GHz CMOS VCO”, IEEE RFIC Symposium, 8-10 June 2003, pp. 89–92. [16] Y. Han; L.E. Larson, D.Y.C. Lie, “A low-voltage 12GHz VCO in 0.13um CMOS for OFDM applications”, Topical Meeting on SiliconMonolithic Integrated Circuits in RF Systems, Jan. 2006, pp. 1–4.

Figures and Table

C

VDD

L

IT

L C

VB

Fig. 1. Traditional LC-VCO topology and CCDP current noise sources in. IT is the tail current flowing in the tail transistor and VB is the dc bias voltage.

Fig. 2. Schematic of the LC-active VCO. M1–M6 are minimum channel length transistors of width 6, 6, 14, 14, 6 and 14 m, respectively. CVAR

is made by p-MOSFET (L=0.4 m, W=4.5 m). All the transistors are biased in the saturation region. The transistors of output buffer are biased through the dc voltage at the node T of the D-BSI circuit.

Fig. 3. Simplified schematic of the D-BSI. The two inductors LR are realized by means of a symmetric spiral (2LR) and a dc voltage (ac ground) is applied to its common node T (central tap) in order to bias the VCO output buffer.

Fig. 4. Measured equivalent inductance (L12) and quality factor (Q) of the D-BSI for different bias currents.

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Active RF Devices, Circuits and Systems Summary

Fig. 5. Noise (PLS) at the terminals 1 and 2 of the D-BSI. Note that this noise level is largely below the maximum sensitivity of commercial instruments (about -100 dBm/Hz).

Fig. 6. a) Die micrograph of the 13-GHz LC-active VCO test-chip. b) 13-GHz balun on Rogers 4003 substrate. c) Measurement setup.

Fig. 7. Measured output spectrum of the VCO. Fig. 8. Measured PN (f0=12.72GHz).

Fig. 9. Measured fine tuning range and PN versus VC. PN varies in the range from -105.25 to -102.3 dBc/Hz at 1-MHz frequency offset. Fig. 10. PN and oscillation frequency (measured) versus IDC of the D-

BSI.

TABLE I. SUMMARY OF THE PERFORMANCE AND COMPARISON WITH SOA

Ref. fO[GHz]

VDD [V]

Pc[mW]

PN [dBc/Hz]

FOM(*) [dB] Node

[11] 11.55 1.8 8.1 -110.8@1MHz -183 0.18um [12] 16 1.8 8.1 -111@1MHz -186 0.18um [13] 11.22 1.8 6.84 -109.4@1MHz -181.8 0.18um [14] 10 1.8 11.9 -118.7@1MHz -188 0.18um [15] 12 1 7.7 -102@0.6MHz -179.2 0.18um [16] 11.2 0.8 4.8 -106@1MHz -180.2 0.13um Thiswork 12.72 1.2 3 -105.25@1MHz -182.6 90nm

(*) FOM = PN – 20 log(fC/ f) + 10 log(PC/1mW)

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IET Active RF Devices, Circuits and Systems Seminar

Ku Band LC-active 90nm CMOS VCO

Domenico Zito1,2, Domenico Pepe1

1Tyndall National Institute, Lee Maltings, Cork2Dept. of Microelectronic Engineering, University College Cork, Cork

12th Sep.2011, The Institute of Electronics, Communications and Information Technology (ECIT), Queen's University of Belfast, Northern Ireland Science Park, Belfast (UK)

www.tyndall.ie

Outline

• Introduction

• Phase Noise in LC-VCOs: Recalls

• CMOS LC-Active VCO– topology– differential Boot-Strapped Inductor (D-BSI)

• 13-GHz D-BSI in 90nm CMOS– experimental results

• 13-GHz LC-Active VCO in 90nm CMOS– experimental results– summary of performance and comparison with the SoA

• Conclusions

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Introduction

• The interests of the industry have been addressed to emerging applications at higher frequency, up to millimeter-waves

• For many of them, the realization of the overall wireless transceiver depends mainly on the opportunity of implementing low-phase noise oscillators

• L-C Voltage Controlled Oscillator (LC-VCO) are the most common type of oscillator used in RFIC design

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Phase Noise in LC-VCOs: Recalls

• In LC-VCOs the Phase Noise (PN) is mainly due to the following contributions

– Resonator noise

– Tail current noise

– Differential pair noise

• Ways to reduce PN in LC-VCOs – at a topological level– by increasing the quality factor (Q) of the tank

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CMOS LC-Active VCO

• Schematic of the proposed CMOS LC-active VCO – each transistor of the cross-coupled pairs is tailed with its own current source– the LC-active tank is realized by means of the Differential Boot-Strapped

Inductor (D-BSI) circuit

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CMOS LC-Active VCO: topology

• Unlike the traditional cross-coupled differential pair, this topology avoids that the differential pair noise reaches the tank over the entire period of oscillation– Parasitic effects

Traditional cross-coupled differential pair Proposed LC Active VCO

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Differential Boot-Strapped Inductor (D-BSI)

• The D-BSI allows the implementation of high-Q active inductors characterized by a low power consumption and low noise contribution[Ref.]

[Ref.] D. Zito, A. Fonte, D. Pepe, “Microwave Active Inductors”, IEEE MWCL, Vol. 19, Is. 7, July 2009, pp. 461–463.

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13-GHz D-BSI in 90nm CMOS

• A 13-GHz D-BSI stand-alone has been implemented in 90nm CMOS technology by ST-Microelectronics

• Micrograph of the test-chip– 0.21mm2 (ESD-protected pad inclusive)– 0.16mm2 core only

• VDD = 1.1 V, PC = 2 mW

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13-GHz D-BSI in 90nm CMOS: experimental results (1/3)

• Measured equivalent inductance and Q – L=3.2nH, Q up to 400

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13-GHz D-BSI in 90nm CMOS: experimental results (2/3)

• Measured Q vs. input power– Q of 55 up to -7 dBm – IDC = 1.76mA

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13-GHz D-BSI in 90nm CMOS: experimental results (3/3)

• Simulated noise at the terminals 1 and 2 of the D-BSI– input noise approx. 1nV/sqrt(Hz) at 13 GHz– mostly due to the parasitic resistance of the primary spirals of the

transformers

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13-GHz LC-Active VCO in 90nm CMOS

• 13-GHz LC-Active VCO in 90nm CMOS by ST-Microelectronics – D-BSI active microwave inductor in the tank

• Microphotograph of the test-chip– 0.216mm2 (ESD-protected pad inclusive)

• VDD = 1.2 V, PC = 3 mW

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13-GHz LC-Active VCO in 90nm CMOS: experimental results (1/5)

• LC-Active VCO measurement setup– R&S FSUP 26.5-GHz SSA– 13-GHz balun on Rogers 4003 substrate

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13-GHz LC-Active VCO in 90nm CMOS: experimental results (2/5)

• Measured output spectrum– amplitude of 11.13 dBm (3.25 dB test setup loss inclusive) at f0=12.72 GHz

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13-GHz LC-Active VCO in 90nm CMOS: experimental results (3/5)

• Measured PN– −105.25 dBc/Hz at 1-MHz offset at f0=12.72GHz

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13-GHz LC-Active VCO in 90nm CMOS: experimental results (4/5)

• Measured fine tuning range and PN versus VC

– PN varies in the range from -105.25 to -102.3 dBc/Hz at 1-MHz frequency offset

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13-GHz LC-Active VCO in 90nm CMOS: experimental results (5/5)

• Measured PN and oscillation frequency versus IDC of the D-BSI.– PN is reduced of about 12 dB when the D-BSI is switched on

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13-GHz LC-Active VCO in 90nm CMOS: Summary of performance and comparison with the SoA

Ref. fC[GHz]

VDD[V]

Pc[mW]

PN[dBc/Hz]

FOM[dB] Tech.

[Park, 2008] 11.55 1.8 8.1 -110.8@1MHz -183 0.18um

[Yang, 2008] 16 1.8 8.1 -111@1MHz -186 0.18um

[Oh, 2005] 11.22 1.8 6.84 -109.4@1MHz -181.8 0.18um

[Ko, 2004] 10 1.8 11.9 -118.7@1MHz -188 0.18um

[Tsang, 2003] 12 1 7.7 -102@0.6MHz -179.2 0.18um

[Han, 2006] 11.2 0.8 4.8 -106@1MHz -180.2 0.13um

This work 12.72 1.2 3 -106@1MHz -183.3 90nm

)mW/Plog()f/flog(PNFOM CC 11020 +Δ−=

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Conclusions

• A 13-GHz LC-Active VCO has been implemented in 90nm CMOS

• The tank of the VCO has been realized with a D-BSI active inductor– The D-BSI allows the implementation of high-Q active inductors

characterized by a low power consumption and low noise contribution

• A 13-GHz D-BSI stand-alone has been implemented in 90nm CMOS– Experimental results

• L=3.2nH• Q up to 400• Q up to 55 for an input of -7dBm

• The 13-GHz LC-Active VCO has been characterized experimentally– Experimental results

• PN=-106dBc/Hz@1MHz from carrier• PC = 3mW

• Very competitive performance have been achieved by saving approx. 37.5% of the best state-of-the-art power consumption

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Acknowledgments

• The authors are grateful to the following bodies for their financial supports:– Irish Research Council for Science, Engineering and Technology

(IRCSET) – Science Foundation Ireland (SFI)

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Domenico Zito1,2, Domenico Pepe1

email: domenico.zito@tyndall.ie email: domenico.pepe@tyndall.ie

1Tyndall National Institute, Lee Maltings, Cork2Dept. of Microelectronic Engineering, University College Cork, Cork

Contacts

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