IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION …ece.ubc.ca/~xmeng/Files/Meng_TVLSI.pdf · IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 11, NOVEMBER

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 11, NOVEMBER 2008 1581

Layout of Decoupling Capacitors inIP Blocks for 90-nm CMOS

Xiongfei Meng, Student Member, IEEE, Resve Saleh, Fellow, IEEE, and Karim Arabi, Member, IEEE

Abstract—On-chip decoupling capacitors (decaps) in the formof MOS transistors are widely used to reduce power supplynoise. This paper provides guidelines for standard cell layouts ofdecaps for use within Intellectual Property (IP) blocks in applica-tion-specific integrated circuit (ASIC) designs. At 90-nm CMOStechnology and below, a tradeoff exists between high-frequency ef-fects and electrostatic discharge (ESD) reliability when designingthe layout of such decaps. In this paper, the high-frequency effectsare modeled using simple equations. A metric is developed todetermine the optimal number of fingers based on the frequencyresponse. Then, a cross-coupled design is described that has beenrecently introduced by cell library developers to handle ESDproblems. Unfortunately, it suffers from poor response times duethe large resistance inherent in its design. Improved cross-coupleddesigns are presented that properly balance issues of frequencyresponse with ESD performance, while greatly reducing thin-oxidegate leakage.

Index Terms—Electrostatic discharges, integrated circuit layout,leakage currents, MOS capacitors.

I. INTRODUCTION

W ITH increasing clock frequency and decreasing supplyvoltage as CMOS technology scales, maintaining the

quality of the power supply has become a primary issue. Voltagevariations in the power supply arise due to IR drop and Ldi/dt[1]. The IR drop has been increasing over time due to increasedresistances in the power grid as the metal widths continue toshrink with each successive technology generation. The induc-tive Ldi/dt effects are also increasing due to the high current de-mands of application-specific integrated circuit (ASIC) designsin 90-nm CMOS technology. However, the pin and package in-ductance overwhelms the inductance of the on-chip power dis-tribution network, and therefore, the on-chip inductance is usu-ally neglected [1].

There are a variety of different methods that can be used tomanage voltage drops. Among them, the most popular is to useon-chip decoupling capacitors (decaps) to maintain the powersupply within a certain percentage (e.g., 10%) of the nominalsupply voltage [2], [3]. Decaps are typically placed in regionsbetween areas of high current demands and the power pads andinput/output (I/O) pins [4]–[6]. This paper addresses standard-

Manuscript received July 13, 2006; revised May 3, 2007. First publishedOctober 3, 2008; current version published October 22, 2008. This workwas supported in part by the Natural Sciences and Engineering ResearchCouncil of Canada (NSERC) and by PMC-Sierra Inc.

X. Meng and R. Saleh are with the Department of Electrical and ComputerEngineering, University of British Columbia, Vancouver, BC V6T 1Z4, Canada(e-mail: [email protected]; [email protected]).

K. Arabi was with PMC-Sierra, Inc., Burnaby, BC V5A 4X1, Canada.He is now with Qualcomm, San Diego, CA 92121 USA (e-mail:[email protected]).

Digital Object Identifier 10.1109/TVLSI.2008.2001240

cell decap layout [7], [8], [15] at the 90-nm technology node andbelow.

A number of relatively new issues for standard cell decapsmust be addressed that impact the design and layout of thesecells at scaled technology nodes. We address two importantproblems of decap frequency response and electrostatic dis-charge (ESD) protection [11]. Since decaps are required toperform at increasingly higher operating frequencies, we firstinvestigate the frequency response [6], [9], [10] and proposeimprovements to optimize decap layouts. Next, we investigatethe problems of reduced oxide thickness of a transistor, namely,ESD [11] and thin-oxide gate leakage [3], [4], in the contextof decap design. A potential ESD event across a thin gateoxide increases the likelihood that a chip will be permanentlydamaged due to a short circuit in the decap itself. Higher gateleakage increases the total static power consumption of thechip.

A cross-coupled standard-cell design was proposed [12] toaddress the issue of ESD performance. The design providessufficient ESD protection, but does not offer any savings ingate leakage and it may compromise the frequency response.This paper suggests improved layouts of the cross-coupled de-sign that properly tradeoff frequency response and ESD perfor-mance, while greatly reducing gate leakage current.

The rest of this paper is organized as follows. In Section II,layout design based on the frequency response of decaps is ad-dressed. The two new design issues, ESD reliability and gatetunneling leakage, are briefly discussed in Section III, followedby the cross-coupled design and its layout modifications. Con-clusions are provided in Section IV.

II. HIGH-FREQUENCY RESPONSE OF DECOUPLING CAPACITORS

Standard cell layouts of an Intellectual Property (IP) blockconsist of rows of fixed-height cells in the ASIC design flow.After cell placement is completed, there are a number of emptycells that can be filled with decaps of various sizes depending onthe space available. Previous work has addressed the automaticplacement and sizing of decap cells [8]. Our focus is on optimallayout of each decap filler cell. Typically, these standard cellshave both nMOS and pMOS devices as shown in Fig. 1(a), witha corresponding layout in Fig. 1(b). Thin-oxide MOS devicesare generally used for standard-cell decap implementation.

As the frequency of operation increases, a fingering approachis required to implement the layout. That is, a single transistor issplit into a number of parallel transistors with the same width,but smaller channel lengths. The overhead of this approach isadditional spacing for source/drain contacts and an overall re-duction in the low-frequency capacitance. However, the averagecapacitance of the decap over a given frequency range improves

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Fig. 1. (a) Standard cell decap can be implemented as an nMOS in parallel witha pMOS device. The corresponding layout is shown in (b).

Fig. 2. Decap can be implemented as an nMOS device and modeled asa lumped-RC circuit with effective resistance and effective capacitance asfunctions of frequency � .

as we increase the number of fingers. Therefore, we address theproblem of how many fingers to use, given a fixed area of afiller cell and fixed gate-oxide thickness, and develop a usefulmetric to capture the frequency response characteristics in orderto choose the optimal number of fingers.

To derive the needed equations, we begin with an nMOS de-coupling capacitance as shown in Fig. 2. Non-idealities associ-ated with MOS devices are modeled as a lumped-resistance–ca-pacitance (RC) circuit [10] where both the effective resistance

, and effective capacitance , are functions of frequency, as shown in Fig. 2.The dc capacitance and resistance are given by

[7], [10], [13]

(1a)

(1b)

where is the oxide capacitance per unit area, is theoverlap and fringing capacitances per unit width of the device,

is the mobility, is the voltage across the oxide, is thethreshold voltage, and and are the width and length of thetransistor, respectively.

Assuming that a given filler cell has a horizontal dimensionand vertical dimension , the channel length of each device

in a fingered layout is

(2)

where is the number of fingers and is the distancebetween fingers required by contact spacing rules. Modified ex-pressions for and can be derived as a function of

Fig. 3. Circuit setup to extract the effective resistance and the effective capac-itance values from an ac analysis.

the number of fingers. Thus, the effective capacitance at dc isgiven by

(3)

For capacitance, each additional finger adds extra overlap andfringing capacitances but loses area due to the contact spacing.Therefore, the capacitance actually decreases linearly as we in-crease the number of fingers. The corresponding equation for

with fingers in a parallel combination is

(4)

In previous work [10], the resistance was used to select thechannel length and there were no area constraints involved.However, since the resistance drops off as , it is not asimportant in the selection of a suitable . In fact, the goal ofan optimal layout should be to provide the highest capacitancevalue in the given area over a desired operating frequency, 0 to

, while delivering a low resistance. A simple metric is neededto evaluate layouts with differing number of fingers. The logicalchoice for a metric is to use the average capacitance over thisfrequency response up to , as follows:

(5)

where is obtained from (3) and is the effec-tive capacitance with fingers at frequency . A weighted av-erage is also feasible, but we find that the simple average workswell in practice.

The main issue with the metric is that is diffi-cult to compute without the aid of HSPICE or an equivalentsimulation tool. To facilitate the process, we developed simplefrequency-dependent models for both and . We alsowanted the characteristics of both functions to be accurate astechnology scales. First, we performed a number of ac simu-lations in HSPICE for a 90-nm CMOS technology using non-quasi-static (NQS) models, which are essential when simulatingdecaps in the gigahertz frequency range of operation. Two pa-rameters, ACNQSMOD and TRNQSMOD, were set to “1” inBSIM4 [13]. The circuit in Fig. 3 was used to extract the effec-tive resistance and capacitance from HSPICE results as follows:

where , and are the real, imagi-nary, and magnitude components of , respectively.

Both nMOS and pMOS decaps were simulated withW L sizes as follows: 15 m 5 m, 10 m 10 m,


MENG et al.: LAYOUT OF DECOUPLING CAPACITORS IN IP BLOCKS FOR 90-NM CMOS 1583

Fig. 4. Circuit setup to extract the effective resistance and the effective capacitance values from an ac analysis.

and 5 m 15 m. The simulation frequency ranged from 0to 10 GHz. Typical ASIC clock rates today are in the rangeof 500 MHz to 1 GHz, but it is important to study frequencyresponse well beyond the clock frequency. Most of the spectralpower density of digital signals lies within frequencies of upto , where is a signal’s rise time (whichcan be on the order of 50 ps or less), and is the 3-dBcutoff frequency of the spectral power density [14]. We assumeconservatively that 50 ps, and carry out the analysis upto 10 GHz.

The results of the simulations are shown in Fig. 4. As in-creases, there is a noticeable rolloff in the curves due to finitetransit time effects. Devices with large L’s have a more pro-nounced effect. In fact, the curve for 5 m 15 um quicklydecays in value relative to 15 m 5 m. A general observa-tion on nMOS and pMOS decaps can also be made: nMOS issuperior to pMOS in its high-frequency behavior since it has alarger and a smaller at high frequencies, assuming thearea is fixed. Although standard cells employ both nMOS andpMOS devices for decaps, these results show that nMOS decapswould provide better frequency response characteristics.

Based on the frequency responses of and , we pos-tulated functions for modeling purposes of the form

(6a)

(6b)

where [13] and .Shown in Fig. 5 are the results of curve-fitting using (6a)and (6b) against HSPICE for the nMOS device. The resultsare very close. A factor of 1/2 was applied to in order toproduce results shown in Fig. 5. That is, the equation formust be adjusted by a fitting factor of 0.5 in order to obtaingood results. Similar results were obtained for pMOS devices.This demonstrates that the first-order equations for and

are reasonably accurate and, perhaps more importantly,that can be easily computed for the metric withoutrunning HSPICE.

We now have all the necessary information to determine thenumber of fingers based on the frequency response. From (6a),the effective capacitance in (5) at with fingers is

where

To demonstrate the efficacy of the metric, we apply it tothe layout of a standard-cell decap in an available area of2 m 9 m. Using (5), Table I lists the metric valuesfor the nMOS or pMOS devices for different frequency ranges.The optimal number of fingers corresponds to the largest entriesin bold. For example, if the frequency range of interest is 0 to



Fig. 5. Plots of � and � for three nMOS devices (HSPICE versus model).

TABLE IOPTIMAL NUMBER OF FINGERS FOR DIFFERENT FREQUENCY RANGES

10 GHz, then 3 nMOS fingers and 4 pMOS fingers are optimalrelative to our metric. Of course, if the range is 0 to 2 GHz, twofingers are sufficient for both N or P devices. Note that pMOSdevices typically require one more finger than nMOS devicesat higher frequencies of operation.

Table I was shown to illustrate the use of the metric in de-termining the optimal number of fingers. In practice, the designprocess would be as follows. First, the area of a filler cell (inparticular, the -dimension of the cell) and frequency range ofoperation are used as input parameters. Then, the capacitancevalue as a function of is computed using (5). Finally, the valueof producing the highest capacitance is used to implement thelayout.

The results in Table I can be validated by using (3) and(6a) to generate plots for both nMOS and pMOSdevices, as shown in Fig. 6. The results in the plot wereverified with HSPICE to ensure consistency. As an example,consider the cases with 1 finger and 10 GHz. For thenMOS case in Fig. 6190 fF 50 fF 120 fF, whereas for pMOS,

190 fF 10 fF 100 fF.These are the same values that are found in the last row of thetable with . The rest of the table is produced in the samemanner for different values of and frequency range .

By inspection, the plots indicate that three fingers would beoptimal for nMOS decaps and four fingers would be optimalfor pMOS decaps, based on the flatness of the lines and the ini-tial value of the capacitance. This conclusion is consistent withTable I. However, by using the metric, designers can quicklyobtain the optimal number of fingers for a target operating fre-quency, without the need for such plots or SPICE simulations.

Fig. 6. Effective capacitance � �� of nMOS and pMOS decaps in 90 nmfor different numbers of fingers in a fixed area of � � � �m and � � � �m.

Fig. 7 illustrates how standard cell layouts would be imple-mented using the previous results, assuming a 10-GHz operatingrange. These layouts would be automatically created by a decapfiller cell generator. Two possible layouts are shown: (a) usesthe N and P devices and (b) is nMOS only. Fig. 9(a) uses threefingers for the nMOS device and four fingers for the pMOS de-vice. From an average capacitance perspective, the nMOS-onlylayout style of Fig. 9(b) is better, and this is also reflected inTable I. To implement this type of layout in a standard cell, thep-well region must be extended to cover the entire area, whichis not typical of standard cell design. This approach can be used



Fig. 7. Two sample layouts showing (a) N and P decap with four pMOSand three nMOS fingers and (b) nMOS-only with three fingers in a 90-nmtechnology.

Fig. 8. Cross-coupled decap schematic [12].

as long as the design rules at the boundaries of adjacent standardcells are satisfied.

III. CROSS-COUPLED DECOUPLING CAPACITOR DESIGNS

At the 90-nm technology node, there is the possibility ofoxide breakdown during an ESD event. A simple ESD protec-tion scheme for decaps is to insert a relatively large resistance inseries to limit the maximum voltage seen at the gate of the decap[11]. A minimum is needed to ensure ESD reliability fordecap cells. A cross-coupled decap design has been proposedby cell library developers [12] to address the issue of ESD reli-ability. Fig. 8 illustrates the new decap wherein the drain of thepMOS device is connected to the gate of the nMOS, and viceversa [12]. The cross-coupled design provides additional seriesresistance to the inherent decap resistance to increase .

The frequency response characteristics of this new configura-tion can be evaluated to determine if the results obtained in thelast section can be applied directly to the new circuit. We firstcompared a standard 3N-4P decap of Fig. 7(a) to a same-areacross-coupled decap using HSPICE ac analysis in Fig. 9.

The standard 3N-4P decap has a very low resistance (around30 ), which makes it prone to ESD failure. The cross-coupled3N-4P design has a much higher dc (around 3500 ) buta poorer frequency response for . Consequently, the tradeoffbetween ESD reliability and frequency response must be con-sidered in the design process and decap layout. To improve thefrequency response, additional fingers must be used. The target

Fig. 9. � �� and � �� comparison of fixed-area standard decap andcross-coupled decap: same MOS device sizes but different poly connections.

resistance for ESD protection in our case is a min-imum of 500 . We increased the number of fingers to reducethe resistance from 3500 down to that required by ESD. Ac-cording to (4), the scale factor on the 3N-4P design can be foundas follows:

Scaling the 3N-4P by approximately this amount, we produceda cross-coupled 8N-9P decap. Similarly, for an ESD target

, we find that , so we chose6N-7P. The plots for 6N-7P and 8N-9P fingers are also illus-trated in Fig. 9. The results show that the 8N-9P cross-coupledversion is the best configuration to address both frequencyresponse and ESD protection.

From a layout perspective, the cross-coupled decaps can berealized by simply rerouting the poly connections of the stan-dard decaps, while keeping the MOS devices the same. The lay-outs of two cases, 3N-4P and 8N-9P, are shown in Fig. 10.

We addressed one other issue of thin-oxide gate leakagecurrent [16] of the decap, which contributes to the chip’s totalstatic power. Using HSPICE, the standard and cross-coupleddecap circuits were found to have almost identical gate leakage.That is, since the cell area is fixed and only the poly terminalconnections are swapped, the cross-coupled design providesno inherent savings in gate leakage as compared to the stan-dard design. There exists a simple design approach to savegate leakage. Simulations using BSIM4 SPICE models [17]indicated that pMOS gate leakage is roughly 3 times smallerthan nMOS gate leakage for same size transistors [18], [19].



Fig. 10. Sample layouts of cross-coupled decap cells for (a) 3N-4P (b) 8N-9P.

Fig. 11. Sample layouts of improved decap cells for (a) 1N-9P (b) 1N-16P.

Therefore, pMOS devices are preferred from a leakage per-spective. Since pMOS devices have a poor frequency response,more fingers can be used to obtain the desired result. But thismust be carried out in the context of the cross-coupled designto preserve ESD protection.

The basic idea to control leakage is to have the smallestpossible nMOS device cross-coupled with the largest possiblemulti-fingered pMOS device. This way, the advantages ofpMOS leakage and cross-coupling ESD protection are pre-served. The layouts of two configurations are illustrated inFig. 11. A small nMOS device is used in both cases. Notethe n-well regions have been expanded in both layouts toaccommodate the larger pMOS device. Fig. 11(a) uses 9 pMOSfingers while Fig. 11(b) has a total of 16 fingers. The same cellarea as before (2 m 9 m) was used for the two designs.

Table II summarizes the leakage values for the different cases.The standard and cross-coupled 3N-4P decaps have roughly thesame leakage. It is somewhat reduced for the 8N-9P case sincethere is less area for leakage. However, for the two layouts with

TABLE IICOMPARISON OF THE NEW DESIGNS AND THEIR GATE LEAKAGE CURRENT

Fig. 12. Frequency response of various cross-coupled designs.

the small nMOS devices, the leakage is cut in half. In fact, thecase with 1N-16P, the leakage is 62% less than the standarddecap 3N-4P.

The of the cross-coupled design must be setbased on ESD considerations, but that also controls the max-imum number of fingers permitted . Since the nMOSdevice is fixed while the pMOS device is multi-fingered, weuse the following equation to determine the resistance:



where and are the resistance of the decaps without fin-gers. This target sets up the equation for a maximumnumber of fingers, . That is

(7)

As described in Section II, the optimal depends on the fre-quency response (i.e., ), but the number of fingers se-lected should not exceed to satisfy ESD requirements.

Fig. 12 illustrates the frequency response of the various de-signs from 0–10 GHz. All of the configurations provide similar

values but are dramatically different in the frequency re-sponse characteristics. The standard 3N-4P case is the best, fol-lowed by the modified cross-coupled 1N-16P. The are dif-ferent in all cases but only the standard 3N-4P case is unsuitablefor ESD protection. However, it is desirable to select the config-uration with the lowest that satisfies the ESD criteria (500

in this case) for a rapid time-domain response. Overall, thecross-coupled 1N-16P layout is recommended because it pro-vides the required for ESD reliability and saves at least50%–60% on gate leakage.

To summarize, at 90 nm and below, standard-cell decapdesign should follow the layout strategy shown in Fig. 11. Byusing the smallest nMOS device and the largest multi-fingeredpMOS device in the cross-coupled form, the decap has thelowest leakage and is able to satisfy the ESD requirements.

IV. CONCLUSION

This paper investigated the tradeoffs between high-frequencyperformance of decaps and ESD protection and its impact on thelayout of standard cell decaps. We introduced a design metric todetermine the optimal number of fingers to use in the standardcell layout to obtain a desired capacitance level over a targetoperating frequency. Models were developed to capture the fre-quency responses of and for a given technology withonly a few parameters. As a result, the models can be used topredict the same characteristics of future technologies.

For ESD protection, a cross-coupled design was proposed bycell library developers to provide a large series resistance, but itsuffers from reduced frequency response and provides no sav-ings in gate leakage. This paper shows that more fingers areneeded with the cross-coupled standard-cell layouts to providethe target resistance value for ESD protection. We show thatthe layout with the smallest nMOS device and a multi-fingeredpMOS device delivers acceptable frequency response and ESDreliability, while providing the lowest leakage.

ACKNOWLEDGMENT

The authors would like to thank J. Chia for early work in thisarea.

REFERENCES

[1] S. Pant and E. Chiprout, “Power grid physics and implications forCAD,” in Proc. 43rd ACM/IEEE Des. Autom. Conf., Jul. 2006, pp.199–204.

[2] H. H. Chen and S. E. Schuster, “On-chip decoupling capacitor opti-mization for high-performance VLSI design,” in Proc. Int. Symp. VLSITechnol., Syst., Appl., May–Jun. 1995, pp. 99–103.

[3] H. H. Chen, J. S. Neely, M. F. Wang, and G. Co, “On-chip decouplingcapacitor optimization for noise and leakage reduction,” in Proc. Symp.Integr. Circuits Syst. Des., Sep. 2003, pp. 319–326.

[4] M. Popovich, E. G. Friedman, M. Sotman, A. Kolodny, and R. M. Se-careanu, “Maximum effective distance of on-chip decoupling capac-itors in power distribution grids,” in Proc. ACM/IEEE Great LakesSymp. VLSI, 2006, pp. 173–179.

[5] D. A. Hodges, H. G. Jackson, and R. A. Saleh, Analysis and Design ofDigital Integrated Circuits in Deep Submicron Technology, 3rd ed.New York: McGraw-Hill, 2004.

[6] M. Popovich and E. G. Friedman, “Decoupling capacitors for multi-voltage power distribution systems,” IEEE Trans. Very Large Scale In-tegr. (VLSI) Syst., vol. 14, no. 3, pp. 217–228, Mar. 2006.

[7] J. Chia, “Design, layout and placement of on-chip decoupling capac-itors in IP blocks,” M.A.Sc. thesis, Dept. Elect. Comput. Eng., Univ.British Columbia, Vancouver, BC, Canada, 2004.

[8] H. Su, S. S. Sapatnekar, and S. R. Nassif, “Optimal decoupling capac-itor sizing and placement for standard-cell layout designs,” IEEE Trans.Comput.-Aided Des. Integr. Circuits Syst., vol. 22, no. 4, pp. 428–436,Apr. 2003.

[9] J. R. Hauser, “Bias sweep rate effects on quasi-static capacitance ofMOS capacitors,” IEEE Trans. Electron Devices, vol. 44, no. 6, pp.1009–1012, Jun. 1997.

[10] P. Larsson, “Parasitic resistance in an MOS transistor used as on-chipdecoupling capacitance,” IEEE J. Solid-State Circuits, vol. 32, no. 4,pp. 574–576, Apr. 1997.

[11] A. Amerasekera and C. Duvvury, ESD in Silicon Integrated Circuits,2nd ed. Hoboken, NJ: Wiley, 2002.

[12] Artisan Components Inc., Sunnyvale, CA, “TSMC 90 nm CLN90GProcess SAGE-X v3.0 standard cell library databook, release 1.0,”2004.

[13] W. Liu, MOSFET Models for SPICE Simulation Including BSIM3v3and BSIM4. Hoboken, NJ: Wiley, 2001.

[14] H. Johnson and M. Graham, High-Speed Digital Design. UpperSaddle River, NJ: Prentice-Hall, 1993.

[15] X. Meng, K. Arabi, and R. Saleh, “Novel decoupling capacitor designsfor sub-90 nm CMOS technology,” in Proc. Int. Symp. Quality Elec-tron. Des., Mar. 2006, pp. 266–272.

[16] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakagecurrent mechanisms and leakage reduction techniques in deep-submi-crometer CMOS circuits,” Proc. IEEE, vol. 91, no. 2, pp. 305–327, Feb.2003.

[17] K. Cao, W.-C. Lee, W. Liu, X. Jin, P. Su, S. K. H. Fung, J. X. An,B. Yu, and C. Hu, “BSIM4 gate leakage model including source drainpartition,” in Tech. Dig. Int. Electron Devices Meet., Dec. 2000, pp.815–818.

[18] W.-C. Lee and C. Hu, “Modeling gate and substrate currents due to con-duction- and valence-band electron and hole tunneling,” in Dig. Tech.Papers: Symp. VLSI Technol., Jun. 2000, pp. 198–199.

[19] F. Hamzaoglu and M. Stan, “Circuit-level techniques to control gateleakage for sub-100 nm CMOS,” in Proc. Int. Symp. Low Power Elec-tron. Des., 2002, pp. 60–63.

Xiongfei Meng (S’06) received the B.A.Sc. andM.A.Sc. degrees in electrical and computer engi-neering from the University of British Columbia,Vancouver, BC, Canada, in 2004 and 2006, respec-tively, where he is currently pursuing the Ph.D.degree under the supervision of Prof. R. Saleh inelectrical and computer engineering.

He is a Visiting Researcher with PMC-SierraInc., Burnaby, BC, Canada, where he works on IPimprovement and design automation. His researchinterests include analog and mixed-signal VLSI

designs, with an emphasis on power delivery systems and power supply noisecontrol.



Resve Saleh (M’79–SM’03–F’06) received theB.S. degree in electrical engineering from CarletonUniversity in Ottawa, ON, Canada, and the M.S.and Ph.D. degrees in electrical engineering from theUniversity of California, Berkeley.

He is currently a Professor in the fieldof system-on-chip design and test and theNSERC/PMC-Sierra Chairholder with the De-partment of Electrical and Computer Engineering,University of British Columbia, Vancouver, BC,Canada. He has published over 100 journal articles

and conference papers. He was a founder of Simplex Solutions which devel-oped CAD software for deep submicrometer digital design verification. Priorto starting Simplex, he spent nine years as a Professor with the Departmentof Electrical and Computer Engineering, University of Illinois, Urbana. Healso taught for one year at Stanford University, Stanford, CA. He has workedfor Mitel Corporation, Ottawa, ON, Canada, Toshiba Corporation, Japan,Tektronix, Beaverton, OR, and Nortel, Ottawa, ON, Canada. He coauthoreda book entitled Design and Analysis of Digital Integrated Circuit Design: InDeep Submicron Technology (McGraw Hill, 2004).

Prof. Saleh was a recipient of the Presidential Young Investigator Award in1990 from the National Science Foundation in the United States. He is a Profes-sional Engineer of British Columbia. He served as general chair (1995), confer-ence chair (1994), and technical program chair (1993) for the Custom IntegratedCircuits Conference. He held the positions of Technical Program Chair, Confer-ence Chair and Vice-General Chair of the International Symposium on Qualityin Electronic Design (2001), and has served as Associate Editor of the IEEETRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND

SYSTEMS.

Karim Arabi (M’94) received the B.Sc. degreein electrical engineering from Tehran Polytechnic,Tehran, Iran, and the M.Sc. and Ph.D. degrees inelectrical engineering from Ecole Polytechnique deMontreal, Montreal, QC, Canada.

He is Director of Engineering with Qualcommwhere he is involved in design, DFT, and method-ology development. Previously, he was withPMC-Sierra, where he was responsible for R&D ac-tivities in advanced technology development, designmethodology enhancement, and design services. His

research interests include low-power design, power management, DFT, andmixed-signal design and test. He is program committee member of severalIEEE conferences and workshops.


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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION …ece.ubc.ca/~xmeng/Files/Meng_TVLSI.pdf · IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 11, NOVEMBER