IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 10, OCTOBER 2012 4347

A 50-MHz Fully Integrated Low-Swing BuckConverter Using Packaging Inductors

Youngkook Ahn, Hyunseok Nam, and Jeongjin Roh, Senior Member, IEEE

Abstract—Implementation of on-chip passive elements and effi-cient regulation schemes are key aspects of fully integrated dc–dcconverter design. This paper presents a 50-MHz fully integratedbuck converter equipped with packaging inductors. These induc-tors include parasitic inductances of the bonding wires and leadframes in the package. They have significantly better Q factorsthan the best on-chip inductors implemented on silicon. This pa-per also presents full-swing and low-swing gate drivers for efficientregulation of high-frequency switching converters. The low-swingdriver uses the drop voltage of a diode-connected transistor andis applied in a fabricated converter to reduce the gate driving losscaused by the high switching operation. The proposed converteris designed and fabricated using a 0.13-μm 1-poly 6-metal CMOSprocess. The fully integrated buck converter achieves 68.7% and76.8% efficiency for 3.3 V/2.0 V and 2.5 V/1.8 V conversions, re-spectively, while providing a load current of 250 mA.

Index Terms—Bonding wire, fully integrated dc–dc converter,lead frame, low-swing gate driver, packaging inductor.

I. INTRODUCTION

W ITH the development of integrated mixed-signal cir-cuits and system-on-a-chip (SOC) technologies, current

handheld devices require smaller printed circuit board (PCB)area, lower cost, longer battery lifetime, and more coordinatedpower management [1].

Representative power management technologies for hand-held devices include low-dropout (LDO) regulators, switched-capacitor (SC) and switched-inductor dc–dc converters. Al-though the LDO regulator can be integrated on a chip, it hasdisadvantages in that it can conduct only step-down operationsand has very low power efficiency when operating at low outputvoltage because its efficiency is directly determined by a voltageconversion ratio. The SC converter can also be integrated on achip, but it has poor efficiency and many power switches. Theswitched-inductor converter requires a considerable board area

Manuscript received March 31, 2011; revised November 22, 2011, February19, 2012; accepted March 15, 2012. Date of current version May 31, 2012. Thisresearch was supported in part by the Ministry of Knowledge Economy, Korea,under the University ITRC support program supervised by the National IT In-dustry Promotion Agency under NIPA-2012-H0301-12-1007, and in part by theIndustry Strategic Technology Development Program funded by the MinistryKnowledge Economy, Korea under the development of system semiconductortechnology for IT fusion revolution 10039145. Recommended for publicationby Associate Editor S. D. Pekarek.

Youngkook Ahn and Jeongjin Roh are with the Department of Elec-trical Engineering, Hanyang University, Ansan 426-791, Korea (e-mail:jroh@hanyang.ac.kr).

Hyunseok Nam is with the Samsung Electronics Corporation, Giheung 499-711, Korea (email: namstein@naver.com).

Digital Object Identifier 10.1109/TPEL.2012.2192136

due to large external passive elements, including the inductorand the capacitor. However, it has been widely used becauseof its advantage of very high efficiency. Therefore, the full in-tegration of the switched-inductor converter, including passiveelements, is very important for modern hand-held electronic de-vices that require a small and thin PCB area as well as highefficiency.

Previous studies pertaining to integrated power convert-ers have focused on integrating passive elements on sil-icon/nonsilicon substrates and on efficient power regula-tion schemes. In [2], standard complementary metal–oxide–semiconductor (CMOS) processes are used to build the induc-tors required for milliwatt power converters. The inductors haveplanar, spiral layouts. In [3], an optimization strategy is pre-sented to reduce the size of planar, spiral inductors for the givenspecifications of a converter. In [4], a silicon-molding micro-machining technique is used to implement a power inductor insilicon. In [5], a concept of coupled multiturn bond-wire induc-tors with ferrite epoxy glob cores is presented to offer a cost-effective way for SOC or system-in-package. PCB-integratedinductors are introduced in [6]. In [7], plastic deformation mag-netic assembly technology is used to build high-quality IC-levelinductors with a small footprint. In [8], off-chip air-core induc-tors, which are installed on a package, are introduced. In [9]and [10], a 3-D interleaving structure and on-chip poly-nwellcapacitors are used to obtain sufficient capacitance and to re-duce the fabrication cost in SC converters, respectively. In [11]and [12], interleaved techniques are presented to reduce the out-put voltage ripple. In [13] and [14], low-swing gate drive tech-niques are reported to enhance the efficiency characteristics ofhigh-frequency switching converters. In [15], a 200-MHz buckconverter with a resonant gate driver is presented to improve ef-ficiency under light to medium load conditions. In [16], a fullyintegrated four-phase converter with a semiconstant on/off timecontrol system is introduced to maximize the power density. Afully integrated dc–dc converter having a wide power range fordynamic voltage-scaling-based applications is reported in [17].

The present study focuses on a power management IC designfeaturing packaging inductors that have higher Q factors thanon-chip inductors and gate driver designs to improve the powerefficiency of the buck converter by properly driving the powertransistors during high switching transitions. The gate drivers arecomposed of full-swing and low-swing schemes. The fabricatedbuck converter uses the low-swing gate driver to reduce thegate driving loss caused by a high switching frequency, whichis the key design parameter for the full integration of dc–dcconverters. In Section II, the design of the inductor for thefully integrated dc–dc converter is explained. In Section III, the

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4348 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 10, OCTOBER 2012

circuit implementation of the proposed converter is presented.In Section IV, the measurement results and a comparison withprevious works are discussed. Finally, the conclusion is givenin Section V.

II. INDUCTOR DESIGN FOR FULLY INTEGRATED

DC–DC CONVERTERS

The full integration of dc–dc converters offers several advan-tages, such as a smaller chip area and a less expensive and moreflexible design. However, the size of passive filter componentsshould be significantly decreased for the full integration of dc–dc converters. The equations for the inductor and capacitor aregiven in [11] and [13] as

L =(VIN − VOUT)D

2fswIo,

C =(1 − D)

8(ΔVOUT/VOUT)f 2swL

(1)

where D is the duty cycle, fsw is the switching frequency,ΔVOUT is the output voltage ripple, and Io is the nominaloutput current. The sizes of required components can be de-termined by optimizing the parameters of the above equations.In particular, the switching frequency can be used as a key pa-rameter for optimizing the value of an inductor or a capacitor.For example, once the inductance is determined, the capacitanceand switching frequency can be varied to achieve the requiredspecification, such as output voltage ripple.

On-chip metal-insulator-metal (MIM) capacitors with a Qfactor of 95 have been reported [18]. However, on-chip induc-tors, which can be implemented using the top metal layer ofthe CMOS process and have been investigated extensively inRF circuits, suffer from a low Q factor (<10) [19]. The poorQ factor of an on-chip inductor is due to high trace resistance,substrate and inter-layer capacitive coupling, and eddy currentloss [20]. Despite these factors, monolithic inductors have beenconstructed using Q-enhancement techniques [19]. This imple-mentation occupies a significant area and suffers from poor noisefigure and high nonlinearity. Moreover, since the inductance re-quired in power converters is much larger than that required inRF circuits, high Q inductors still pose serious challenges whenimplemented in fully integrated dc–dc converters. Hence, thereis a need to investigate alternatives to high Q inductors that canbe easily integrated and that occupy a small die area.

A. Bonding-Wire Inductor

One alternative is parasitic inductances of bonding wires thatare mainly studied in the RF field. Compared to on-chip in-ductors, bonding wires have high Q factors, and their varia-tion can be less than 5% using modern precision-automatedbonding machines [21]. The electric characteristics of bond-ing wires are determined by their physical dimensions. Fig. 1shows a configuration to calculate the inductances in a standardbond-wire model of EIA/JEDEC [22]. As can be seen in [22],self-inductance (Lbond ) and mutual inductance (Mbond ) can be

Fig. 1. Configuration for inductance calculations.

written as

Lbond = 2 × l × [ln(2l

r) − 0.75] nH,

Mbond = 2 × l × [ln(2l

d) − 1 +

d

l] nH (2)

where l is the length of a wire, r is the radius of a wire, and dis the distance between two wires. The total loop inductance ofthe two parallel wires is as follows:

Ltotal.bond = 2 × (Lbond − Mbond). (3)

The dc resistance can be approximated if the total diameter ofthe wires is known, which is given by

Rdc =L

σA(4)

where L is the total length of the wire, σ is the conductivity ofthe wire, and A is the cross-sectional area of the wire. In [23],the bonding wire is used to obtain a large inductance of 18 nH,and the spiral-shaped inductor on the silicon is configured toreduce the occupied area using an additional bonding process.

B. Packaging Inductor

As an alternative to fully integrated dc–dc converters, wepresent a parasitic packaging inductor composed of a packagelead and a bonding wire. Packaging inductors have significantlyhigher Q factors than the best on-chip inductors implementedon silicon due to their low parasitic component. Major errors aredetermined by the variation of the bond-wire length connectedto the package cavity [24].

Popular IC package types used in the semiconductor industryare QFP, SOP, DIP, BGA, etc. Table I shows example RLC val-ues for different packages [25]. Bonding wire parasitic elementsare not included in Table I. As shown in Table I, packages havedifferent RLC values due to different characteristics, includingsize, layout, and lead counts. Therefore, once a package type ischosen for applications using the packaging inductor, the valueof packaging inductance can be controlled by compromisingbetween pin counts used for implementing the packaging in-ductor and the switching frequency of a dc–dc converter. Thiswork uses an MQFP package to show the feasibility of the fullyintegrated dc–dc converter using packaging inductors. Differentpackage types are also available for obtaining the packaginginductance.

AHN et al.: 50-MHZ FULLY INTEGRATED LOW-SWING BUCK CONVERTER USING PACKAGING INDUCTORS 4349

TABLE IEXAMPLE RLC VALUES FOR DIFFERENT PACKAGES

Fig. 2. SOC architecture using a fully integrated converter with packaging inductors.

Fig. 2 shows SOC architecture configured using a fully inte-grated dc–dc converter with a packaging inductor in an MQFPpackage, and it also shows a cross section of a package and thebasic structure of the lead frame. As shown in Fig. 2, the pack-aging inductor is composed of the bonding wire and the leadframe, which can be implemented by soldering two leads on thePCB or using an additional lead molding process to combinetwo leads. Through this power delivery approach, the distancesbetween a dc–dc converter and the load circuits can be consid-erably shortened on the same silicon substrate. As a result, thepower supply interconnection delays and the response time dur-ing load transients can be reduced significantly compared withmultichip architectures.

The packaging inductor includes both bonding wire induc-tance and lead inductance, as shown in Fig. 2. The analyticaltechniques help establish the design guideline through the handcalculation of packaging inductance. In reality, the more accu-rate model parameter of the package requires a full 3-D electricalsimulation, which can provide the best prediction of electricalbehavior for the specific packaging inductor design [26].

Fig. 3 shows the equivalent circuit model, including packageleads and bonding wires, and its electrical data [27]. Fig. 3(b)shows the corresponding electrical data when the MQFP pack-age is used to implement the packaging inductor. These dataare generated by the 3-D electrical simulator (Ansoft Q3D pa-rameter extractor [26]). These electrical data also show that thepackaging inductor has sufficient inductance and low parasiticresistance for use in dc–dc converters. Leads are modeled usingT-equivalent circuits [25]. Each lead has two terminals: one isconnected to the PCB, and the other is connected to the bond-ing wire. In a T-equivalent circuit, the self-inductance and theself-resistance are separated into two parts and placed on ei-ther side of the self-capacitance. Bonding wires use the lumpedRLC model [28] and mutual capacitance of the bonding wire isomitted from the model for the sake of simplicity. The leads arelabeled lead1 , lead2 , and lead2+n; a current flows from lead1 tolead2+n .

Mutual inductance between neighboring pins arises due tothe magnetic coupling effect, which affects the performanceof the filter inductor. It is unusual that the mutual inductance

4350 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 10, OCTOBER 2012

Fig. 3. (a) Equivalent circuit model of package leads and bonding wires. (b) Electrical data.

includes both positive and negative terms due to the differentcurrent direction in the metal strip. Positive mutual inductanceincreases the real inductance of packaging inductors, whereasnegative mutual inductance decreases it. Therefore, the effectof mutual inductance should be taken into account in detailedsimulations of dc–dc converters.

Two package leads and bonding wires are used to imple-ment the inductor for a fully integrated dc–dc converter, whichhave negative mutual inductance due to opposite current direc-tion, as shown in Fig. 3. In the case of a packaging inductorconsisting of lead1 and lead2 , total inductance can be signifi-cantly reduced by a strong negative coupling effect, which alsodegrades the performance of a dc–dc converter. Therefore, anoptimum distance between two neighboring pins should be de-termined to minimize the effect of negative mutual inductance.The self-inductance, mutual inductance, and total packaginginductance used in this paper are 22.6, 2.67, and 19.9 nH,respectively. The total series resistance is approximately200 mΩ.

C. Geometric Reconfiguration of Packaging Inductors

As discussed in the previous section, the packaging inductor,which consists of two packaging pins in parallel, suffers from thenegative coupling effect. Fig. 4 shows a possible configurationof a spiral-shaped inductor using package lead and bondingwire in a package. The spiral-shaped structure of the packaginginductor can suppress the negative coupling effect as well asincrease the total packaging inductance due to positive mutualinductance. The total inductance of the spiral-shaped packaginginductor can be written as follows [20]:

Ltotal = ΣLS + ΣMpositive − ΣMnegative (5)

where LS , Mpositive , and Mnegative are self-inductance, pos-itive mutual inductance, and negative mutual inductance,respectively.

AHN et al.: 50-MHZ FULLY INTEGRATED LOW-SWING BUCK CONVERTER USING PACKAGING INDUCTORS 4351

Fig. 4. Spiral-shaped packaging inductor.

Fig. 5. Block diagram of the fully integrated buck converter.

III. CIRCUIT IMPLEMENTATION

A. Fully Integrated Buck Converter

Fig. 5 shows a block diagram of a fully integrated buck con-verter. This paper focuses on the feasibility study of a dc–dcconverter with a packaging inductor. The designed buck con-verter is composed of a monolithic controller, an integratedoutput filter, and an input decoupling capacitor used to suppresspower supply noises generated by parasitic inductance. RF 1 andRF 2 are configured as off-chip devices for easy modification ofthe output voltage during the test. The designed chip employsvoltage-mode control to generate the pulse-width modulationsignal and uses the package lead and bonding wire inductanceexisting in a package to implement a high Q inductor. The circuitsimulation of the dc–dc converter with the packaging inductor isaccurately verified with the help of the reliable electrical data, asshown in Fig 3. Moreover, the buck converter has been designed

and simulated in inductance changes of ±30% to achieve hightolerance for variations in packaging inductance during practicalmeasurement.

B. Gate Driver Circuit

In fully integrated power converters, a key design parameteris a high switching frequency that enables the size of the passiveelements to be reduced. However, operation at a high frequencyincreases power dissipation in the power transistors and theirgate drivers. Overall, these power losses are a significant partof the total losses of dc–dc converters. In switching converters,zero-voltage switching is a useful technique to reduce dynamicpower loss in the power transistors [29], but gate driver lossremains significant. The adaptive power transistor driving tech-nique, which uses optimized and separated driving voltages, isalso useful to reduce the switching loss of the converter [30].In [13] and [14], low-swing techniques are presented to reducethe switching losses of the gate driver chain.

This paper proposes full-swing and low-swing gate driversthat generate dead-time delays, which are required to avoid theshootthrough current from PMOS and NMOS power transis-tors, and enhance the efficiency of a high-frequency switchingconverter. The low-swing driver is simply modified from thefull-swing driver to reduce the gate driving loss. To achieveshort dead-time delays and reduce extra power dissipation inseparated buffer stages that are used to drive each of the powertransistors in the buck converter, unified buffer circuits are pro-posed, which are shown in Fig. 6.

In case I, dead-time delays are controlled by lengths of M2and M3, when the VP rises from 0 to VIN and VN rises from 0 toVIN due to the positive feedback loop consisting of M3 and NMafter the dead-time delay. When VN falls from VIN to 0, thenVP falls after the dead-time delay. Therefore, there is no periodwhen both PM and NM are turned ON simultaneously. Whenboth power transistors are turned OFF, the body diode Dbody2 ,which is a parasitic component in the CMOS process, is used toflow the current until PM turns on again [31].

Case II is similar to case I, but it uses the diode-connect M3so that NM operates with low-voltage swing. Once the chargeoperation has begun, VN rises sharply. When VN becomes largerthan VIN–|VTH3 |, M3 will enter the weak inversion region andthe ID3.weak flowing at this time is as follows [32]:

ID3.weak =W

LID0exp(

qVSG3

nkT) (6)

where n is the subthreshold slope factor, ID0 is the process-dependent parameter, k is the Boltzmann’s constant, T is theabsolute temperature, and q is the magnitude of the electroniccharge. From (6), when VN increases, VSG3 decreases and ac-cordingly ID3.weak also decreases. As shown in the waveformof Fig. 6 (b), VN has a lower voltage level than VIN ; the voltagechange during this time can be expressed as follows:

dVN

dt=

ID3.weak

CP 2, when VN > VIN − |VTH3 |. (7)

From (7), the voltage swing level is determined by ID3.weak andcan be adjusted by the length of M3.

4352 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 10, OCTOBER 2012

Fig. 6. Proposed gate drivers: (a) case I and (b) case II.

Fig. 7. Simulated waveforms of gate drivers.

The simulated waveform of the gate drivers is shown in Fig. 7when VIN = 2.5 V, Fsw = 50 MHz, D = 0.5, and IL = 300 mA.Here, IPM and INM are currents flowing through PM and NMpower transistors, respectively. It can be seen that the gate driv-ing signals VP and VN with dead-time delays are generated,so the PM and NM transistors do not turn ON simultaneously,avoiding a large shootthrough current compared to a conven-tional CMOS tapered buffer [33].

To generate the low gate voltage, case II uses the drop volt-age of a diode-connected transistor, which is unlike the re-quired extra passive elements and secondary supply voltagesin [13], [14], [34], and [35]. Gate driving losses in case II canbe expressed as [34]

Pgate.PM = CP 1 × V 2IN × FSW

Pgate.NM = CP 2 × VIN × (VIN − ΔV ) × FSW (8)

where ΔV is the amount of change in VN when M3 is in theweak inversion region, and FSW is the switching frequency.

From (8), the driving loss can be reduced by VIN–ΔV . However,the on-resistance of NM should be evaluated at the gate voltagewithin the range of analysis, since the conduction loss of NMis gate voltage dependent. The on-resistance of a MOSFET canbe generalized as [36]

Ron(VGS) = Rch(VGS) + Rext(VGS) (9)

where Rch is the effective channel resistance and Rext is allthe resistance outside the channel, which includes part of thesource and drain, wiring, and the rest of the parameters. Notethat in the aforementioned equation, both Rch and Rext arefunctions of the gate voltage. Furthermore, Ron is dependent onprocess variations, such as doping profiles, source/drain junctiondimensions, and materials [37].

The optimum on-resistance of NM was determined by theHSPICE simulation. As VN decreases, Ron.NM increases, sinceaccumulation carrier density decreases in a nearly exponentialmanner [37], as shown in Fig. 8. Ron.NM of case II is increasedby 8.2–18.3% compared with that of case I at the input voltagerange of 2.5–3.3 V and can increase the conduction loss. WhenNM is conducting, the conduction loss can be approximated as

Pcond.NM = I2L × (1 − D) × Ron.NM (10)

where D is the duty ratio of the gate signal and IL is the averageinductor current.

To analyze the effect of Ron.NM , conduction losses and gate-driving losses of full-swing and low-swing converters are simu-lated and normalized to the input power at D = 0.5, IL = 200 mA,and FSW = 50 MHz, which is shown in Fig. 9. The low-swingconverter in case II can obtain higher efficiency than the full-swing converter in case I, since the reduction of the gate drivingloss takes precedence over increased conduction loss, as shownin Fig. 9. In addition, the low-swing technique in case II canyield a greater advantage at light loads since the conduction lossstrongly depends on the load current [34], [35]. The gate drivingloss of the converter in case II is reduced by 13.5%, improvingefficiency by 2.6% at a 3.2 V/1.6 V conversion, compared withthat in case I. In this paper, case II is applied in order to obtain

AHN et al.: 50-MHZ FULLY INTEGRATED LOW-SWING BUCK CONVERTER USING PACKAGING INDUCTORS 4353

Fig. 8. Simulated on-resistance of the NM transistor (VDS = 0.1 V, W =4000 μm, and L = 0.35 μm).

Fig. 9. Simulation results of power losses normalized by the input power(D = 0.5, IL = 200 mA, and FSW = 50 MHz).

the advantage of the low-swing technique in a high-frequencyswitching buck converter.

IV. MEASUREMENT RESULTS

The fully integrated dc–dc buck converter is designed in a0.13-μm 1-poly 6-metal CMOS process and fabricated usingthe multiproject wafer. Packaging inductors, a high switchingfrequency of 50 MHz, and a low-swing gate driver are appliedin the buck converter to achieve the full integration of passiveelements and efficient regulation. Fig. 10 shows the micrographof a buck converter, which uses the package leads and the bond-ing wires in the MQFP package to obtain the large inductance;it also shows the emphasized micrograph of a buck converter.

Table II shows the breakdown of the total area by compo-nents. As shown, most of the area is occupied by the capacitors(86.7%), with output capacitors taking up 45.5% and input de-coupling capacitors taking up 41.2% of the total area. All capac-itors used in this paper are MIM capacitors, and the capacitanceis 1 fF/μm2 .

The test setup in Fig. 11 is designed to verify the load andline transient performance of a fabricated chip. In the load regu-lation test, the load current varies between 40 and 120 mA, withVIN=3.3 V, VOUT=2.0 V, and FSW =50 MHz. Fig. 12 displaysthe measured output voltage waveform of the buck converteraccording to the variation in the load current. The transient time

Fig. 10. Micrograph of the proposed buck converter.

TABLE IIAREA BREAKDOWN OF A CHIP

Fig. 11. Load and line transient test setup.

of this paper is approximately 200 ns, and the output ripplevoltage is approximately 300 mV. As shown in Fig. 11, the linetransient test setup simply uses two dc power supplies that arealternately connected to the VIN of a fabricated chip, which issimilar to [38]. In the line transient test, the input voltage variesbetween 2.8 and 3.3 V, with VOUT = 2.1 V, Io = 50 mA, andFSW = 50 MHz. Fig. 13 indicates the measured output voltagewaveform of the buck converter according to the variation in theinput voltage. When the input voltage varies, the output voltagereacts to changes of input voltage, but quickly returns to theoriginal value.

Table III is a summary of the performance of the fabricatedchip. The input voltage range is 2.5–3.3 V, the switching fre-quency is 50 MHz, and the maximum load current is 300 mA.The consumed total silicon area is approximately 10 mm2 .Fig. 14 shows the efficiencies for 3.3 V/2.0 V and 2.5 V/1.8 V

4354 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 10, OCTOBER 2012

Fig. 12. Measured load regulation waveform.

Fig. 13. Measured line regulation waveform.

conversions. The peak efficiencies are measured as 68.7% and76.8%, respectively. In this paper, the measured output voltageripple is about 300 mV, which is reduced by about 14.2%. Thismeans that packaging inductance was increased by about 20%due to the use of a test socket on the PCB for testability, asshown in Fig. 11. The measurements show the line regulationof 7.14%/V at a variation of 0.5 V and the load regulation of0.046%/mA at load changes of 100–300 mA.

Table IV shows a comparison between the proposed con-verter and previously reported works. Most of them use highswitching frequencies in order to reduce the volume of thepassive elements. In the case of the inductor realization, theoff-chip air-core inductor soldered to the package, the on-chipspiral inductor, and the spiral-shaped bonding wire inductor areused in [8], [11]–[13], [16], [17] and [23], respectively. Ourwork was implemented in a standard 0.13-μm CMOS process.The packaging inductor, which already exists in the package,and the low-swing technique are applied to improve the per-formance of the fully integrated dc–dc converter. At conver-sion rates of 0.6–0.72, the efficiencies are measured at 68.7%and 76.8%, respectively. This represents relatively high conver-sion efficiencies compared with [11]–[13], [17] using on-chip

Fig. 14. Measured efficiencies of the fabricated chip.

TABLE IIIPERFORMANCE OF THE FABRICATED DC–DC BUCK CONVERTER

inductors implemented on the silicon, since the packaging in-ductors have low parasitic components.

Table IV also shows the power density, which indicates theamount of power per unit area. This paper shows a power den-sity of 60 mW/mm2 and the maximum output power is 600 mW,which is the second highest value for fully integrated convert-ers. This paper focuses on the feasibility of the fully integratedconverter using packaging inductors. All the capacitors are im-plemented using MIM capacitance of 1 fF/μm2 , which wasonly available at the time of fabrication. Optionally, the highestcapacitance or MOS capacitance can be used to reduce the sili-con area, which would significantly improve the power density.This study can be expanded to supply higher output power usinglarger power transistors. However, inductor power loss causedby parasitic resistance in the packaging inductor would increasewith increasing current and limit the output power to less thanseveral watts.

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TABLE IVPERFORMANCE COMPARISON OF THIS DESIGN WITH PREVIOUSLY REPORTED WORKS

V. CONCLUSION

A 50-MHz fully integrated buck converter was demonstratedin a 0.13-μm 1-poly 6-metal CMOS process. The packaging in-ductors, including both parasitic inductances of bonding wiresand lead frames, were used to implement high Q inductors.These parasitic components are usually considered undesirable,but this work incorporates these parasitic components into thepower stage to enhance the performance of the fully integrateddc–dc converter. This approach can be a very attractive tech-nique for mobile electronic devices, which require very smalland thin PCB solutions. In addition, a low-swing circuit is pro-posed to reduce the gate driving loss of a high-frequency switch-ing buck converter. The low-swing driver uses the drop voltageof a diode-connected transistor without using additional voltagegenerators. The proposed buck converter is verified throughmeasurement results, without requiring any off-chip passiveelements.

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Youngkook Ahn received the B.S. degree in elec-tronic and electrical engineering science from Kyeon-sang National University, Jinjoo, Korea, in 2006. Hereceived the M.S degrees in electrical engineering andcomputer science from Hanyang University, Ansan,Korea, in 2009, where he is currently working towardthe Ph.D. degree in the same department.

His research interests include power managementcircuits and mixed-signal integrated circuits.

Hyunseok Nam received the B.S. degree in elec-tronic and electrical engineering science from Hal-lym University, Chuncheon, Korea, in 2005, and theM.S and Ph.D. degrees in electrical engineering andcomputer science from Hanyang University, Ansan,Korea, in 2007 and 2012, respectively.

He joined Samsung Electronics Corporation, Gi-heung, Korea, in 2012, where he works in the SystemLSI Division.

Jeongjin Roh (SM’2010) received the B.S degreein electrical engineering from Hanyang University,Seoul, Korea, in 1990, the M.S. degree in electricalengineering from The Pennsylvania State Universityin 1998, and the Ph.D. degree in computer engineer-ing from the University of Texas at Austin, Austin,TX, in 2001.

From 1990 to 1996, he was with the SamsungElectronics, Giheung, Korea, as a Senior Circuit De-signer for mixed-signal products. From 2000 to 2001,he was with the Intel Corporation, Austin, TX, as a

Senior Analog Designer for delta-sigma data converters. Since 2001, he hasbeen with the Faculty of the Hanyang University, Ansan, Korea. His researchinterests include oversampled delta-sigma converters and power managementcircuits.