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Gallium Nitride Hybrid Microwave Circuits for Low-Noise Applications Tyler Ross Faculté d’ingénierie Université de Moncton 57, avenue Antonine-Maillet Moncton (N.–B.) E1A 3E9 Canada Email: [email protected] Gabriel Cormier Faculté d’ingénierie Université de Moncton 57, avenue Antonine-Maillet Moncton (N.–B.) E1A 3E9 Canada Email: [email protected] Khelifa Hettak Communications Research Centre Canada 3701 Carling Avenue P.O. Box 11490, Station H Ottawa, ON K2H 8S2 Canada Email: [email protected] Abstract—This paper presents recent work in the area of gallium nitride (GaN) low-noise microwave integrated circuits. Gallium nitride has attracted interest principally due to its power handling ability. However, its noise performance has received relatively little attention. We discuss the noise performance of several discrete devices, and how they perform in hybrid integrated circuits. The predictive and descriptive models used in our work are discussed and are compared with laboratory measurements. I. I NTRODUCTION In recent years, gallium nitride has become increasingly attractive to microwave and millimetre-wave circuit designers. Gallium nitride has many characteristics which make it highly suitable for RF and microwave power amplifiers, such as its very high power handling ability (high power density), high breakdown voltage and an ability to operate at high temperatures (see, e.g., [1], [2]). Gallium nitride also has characteristics that would be useful in systems that are not heat- or power-intensive. For example, gallium nitride is known to be quite resistant to radiation, moreso than gallium arsenide [3], which is advantageous for space or other high ionizing radiation applications. There is therefore reason to consider using gallium nitride for the complete transceiver circuit, particularly when a high level of integration (e.g., system-on-chip) is required. It is therefore necessary to understand and characterize the noise characteristics of gallium nitride transistors. Several authors have reported on the noise generated by gallium nitride devices (see, e.g., [4], [5]). However, much of the work done to date has involved measurement of either discrete devices or monolithic circuits. The former allows the de-embedding of connector parasitics, contact pads and often the extrinsic parasitics of the transistor, while the latter tends to be costly, as the entire circuit, including the transistor and other circuitry, must be fabricated all at the same time, on a single substrate. While this can be quite advantageous in terms of reduced parasitics and loss, it can be quite expensive, especially since relatively small wafers are normally used in gallium nitride fabrication processes. The case of hybrid integrated circuits has not received much attention, however. Hybrid circuits are useful when reduced manufacturing cost is desired, as it allows a cheaper fabrication process to be used for the biasing and matching circuitry, for the example of a low-noise amplifier, which generally occupies many times more area than the active device. Finally, there is a need to examine noise models for discrete gallium nitride devices because commercially available discrete devices are usually intended for power amplifiers and consequently, noise models are not available. Modelling techniques must be investigated if these types of devices are to be used in low-noise applications. This paper is organized as follows: Section II discusses the noise models used, Section III presents the circuits used and Section IV presents and discusses the simulation and measurement results. II. NOISE MODELLING Noise models of varying degrees of sophistication have been known and studied for field-effect transistors in general, and MESFETs and HEMTs more specifically, for quite some time. Over the past few years, models describing the noise of gallium nitride HEMTs specifically have been demonstrated [5], [6]. Many previous models neglected noise sources (such as noise due to the high gate leakage currents present in many gallium nitride devices [7]), or did not provide a way to calculate all the noise parameters of a device (R n , Γ opt and F min ) required to properly design a low-noise amplifier. These shortcomings were addressed by Sanabria et al., who reported on a noise model capable of accurately predicting the noise parameters of gallium nitride HEMTs [8]. This predictive model requires typical small-signal FET model parameters, such as g m , R s , R g , C gs , etc., as well as the gate leakage current in order to calculate the noise parameters. No noise measurements are required. III. CIRCUITS Two different types of circuits were modelled and measured. First, a discrete chip transistor was packaged in a test fixture,

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Page 1: [IEEE the American Electromagnetics Conference (AMEREM) - Ottawa, ON, Canada (2010.07.5-2010.07.8)] 2010 14th International Symposium on Antenna Technology and Applied Electromagnetics

Gallium Nitride Hybrid Microwave Circuits forLow-Noise Applications

Tyler RossFaculté d’ingénierie

Université de Moncton57, avenue Antonine-MailletMoncton (N.–B.) E1A 3E9

CanadaEmail: [email protected]

Gabriel CormierFaculté d’ingénierie

Université de Moncton57, avenue Antonine-MailletMoncton (N.–B.) E1A 3E9

CanadaEmail: [email protected]

Khelifa HettakCommunications Research Centre Canada

3701 Carling AvenueP.O. Box 11490, Station H

Ottawa, ON K2H 8S2Canada

Email: [email protected]

Abstract—This paper presents recent work in the area ofgallium nitride (GaN) low-noise microwave integrated circuits.Gallium nitride has attracted interest principally due to its powerhandling ability. However, its noise performance has receivedrelatively little attention. We discuss the noise performanceof several discrete devices, and how they perform in hybridintegrated circuits. The predictive and descriptive models usedin our work are discussed and are compared with laboratorymeasurements.

I. INTRODUCTION

In recent years, gallium nitride has become increasinglyattractive to microwave and millimetre-wave circuit designers.Gallium nitride has many characteristics which make it highlysuitable for RF and microwave power amplifiers, such asits very high power handling ability (high power density),high breakdown voltage and an ability to operate at hightemperatures (see, e.g., [1], [2]).

Gallium nitride also has characteristics that would be usefulin systems that are not heat- or power-intensive. For example,gallium nitride is known to be quite resistant to radiation,moreso than gallium arsenide [3], which is advantageous forspace or other high ionizing radiation applications. There istherefore reason to consider using gallium nitride for thecomplete transceiver circuit, particularly when a high levelof integration (e.g., system-on-chip) is required.

It is therefore necessary to understand and characterizethe noise characteristics of gallium nitride transistors. Severalauthors have reported on the noise generated by gallium nitridedevices (see, e.g., [4], [5]). However, much of the work doneto date has involved measurement of either discrete devicesor monolithic circuits. The former allows the de-embeddingof connector parasitics, contact pads and often the extrinsicparasitics of the transistor, while the latter tends to be costly,as the entire circuit, including the transistor and other circuitry,must be fabricated all at the same time, on a single substrate.While this can be quite advantageous in terms of reducedparasitics and loss, it can be quite expensive, especially sincerelatively small wafers are normally used in gallium nitridefabrication processes.

The case of hybrid integrated circuits has not received much

attention, however. Hybrid circuits are useful when reducedmanufacturing cost is desired, as it allows a cheaper fabricationprocess to be used for the biasing and matching circuitry, forthe example of a low-noise amplifier, which generally occupiesmany times more area than the active device.

Finally, there is a need to examine noise models fordiscrete gallium nitride devices because commercially availablediscrete devices are usually intended for power amplifiersand consequently, noise models are not available. Modellingtechniques must be investigated if these types of devices areto be used in low-noise applications.

This paper is organized as follows: Section II discussesthe noise models used, Section III presents the circuits usedand Section IV presents and discusses the simulation andmeasurement results.

II. NOISE MODELLING

Noise models of varying degrees of sophistication have beenknown and studied for field-effect transistors in general, andMESFETs and HEMTs more specifically, for quite some time.Over the past few years, models describing the noise of galliumnitride HEMTs specifically have been demonstrated [5], [6].Many previous models neglected noise sources (such as noisedue to the high gate leakage currents present in many galliumnitride devices [7]), or did not provide a way to calculate allthe noise parameters of a device (Rn, Γopt and Fmin) requiredto properly design a low-noise amplifier.

These shortcomings were addressed by Sanabria et al., whoreported on a noise model capable of accurately predicting thenoise parameters of gallium nitride HEMTs [8]. This predictivemodel requires typical small-signal FET model parameters,such as gm, Rs, Rg, Cgs, etc., as well as the gate leakagecurrent in order to calculate the noise parameters. No noisemeasurements are required.

III. CIRCUITS

Two different types of circuits were modelled and measured.First, a discrete chip transistor was packaged in a test fixture,

Page 2: [IEEE the American Electromagnetics Conference (AMEREM) - Ottawa, ON, Canada (2010.07.5-2010.07.8)] 2010 14th International Symposium on Antenna Technology and Applied Electromagnetics

RF in

λ

4

Vg

λ

4

Vd

RF out

Fig. 1. Schematic of the common-source test circuit

complete with biasing circuitry, in a common-source configura-tion. Second, the same type of discrete device was mounted ina common-gate configuration, with biasing circuitry integrated.

In order to perform measurements on the discrete chiptransistors, it was necessary to package them. Otherwise, theprobing would have been complicated and rather delicate, asthe transistor’s pads are on opposite sides of the die and areof different sizes.

For this reason, a test fixture was designed includingall necessary circuitry, except matching. This offers severaladvantages. First, while electromagnetic simulation can providegood results and the different elements (bond wires, connectors,etc.) can be simulated with relatively good accuracy, actualmeasurements allow for even better results. Second, it allowsone to identify inaccuracies in any models used, such as thesmall-signal transistor model, if one is available.

Fig. 1 shows a simplified schematic of the common-sourcetest fixture. The model available from the manufacturer beforefabrication was limited, but it did show that the transistor wasonly conditionally stable. The addition of a shunt resistor onthe drain, as shown on the schematic, was sufficient to stabilizethe transistor. Quarter-wavelength radial stubs were used toachieve broadband RF short-circuits. The stub attached to thestabilizing resistor was sized larger to suppress instability ata lower frequency. Fig. 2 shows a microphotograph of thefabricated test fixture.

Fig. 3 shows a schematic of the common-gate configuration.A series resistor was placed at the drain to prevent the transistorfrom oscillating. However, the amount of resistance requiredreduces the potential gain of the circuit considerably, as thecommon-gate amplifier is well-known for its inherent instability.Quarter-wavelength stubs (both radial and straight stubs) areused for biasing purposes, as shown in the schematic. Thestraight stub was required due to space constraints. Fig. 4shows a microphotograph of the fabricated test fixture.

Both hybrid circuits were manufactured using the Commu-nications Research Centre Canada’s in-house MHMIC process.

Fig. 2. Microphotograph of common-source test fixture. The circuit hasdimensions of 9.8 mm × 7.1 mm.

RF in

λ

4

Vs

Vg

λ

4

λ

4

Vd

RF out

Fig. 3. Schematic of the common-gate test circuit

Fig. 4. Microphotograph of common-gate test fixture. The circuit hasdimensions of 9.9 mm × 8.3 mm.

Page 3: [IEEE the American Electromagnetics Conference (AMEREM) - Ottawa, ON, Canada (2010.07.5-2010.07.8)] 2010 14th International Symposium on Antenna Technology and Applied Electromagnetics

A 10-mil alumina substrate (εr = 9.9) was used, with 1-µmthick gold used for conductive traces. The resistors are TiWthin-film resistors while the blocking capacitors were 5.1pFdiscrete chip capacitors.

Measurements were performed using an Agilent Technolo-gies N5242A precision network analyzer which includes anoise figure option. For source impedance tuning, a MauryMicrowave 8045D slide tuner was used.

Gallium nitride transistors are reported to be very robustdevices [1], [2] and the transistors tested were no exception.Indeed, the devices we tested are capable of high drain voltages(well over 30 volts) and high drain current, resulting in DCpower dissipation of over three watts with no special cooling,and without any detectable damage to the device.

However, the best noise performance is not typically foundat high drain bias voltages [9]. From measurements, it wasdetermined that the best noise performance is obtained at drainvoltages below 10 volts, where the devices have only justentered into saturation. The high power handling ability of thetransistor is not without benefit, even for noise applications: itwould allow a low-noise amplifier to be placed in a receiverfront-end without protection, for example.

IV. RESULTS & DISCUSSION

Both transistor configurations were measured at differentbias points. Small-signal scattering parameter (S-parameter)measurements and noise figure measurements were taken.The common-gate configuration exhibited high instability andrelatively low gain when stabilizing elements were added.While common-gate configurations are seldom used alone asan amplifier stage, they are often used in cascode amplifiers.However, given the weak performance of the measured circuits,we have not yet studied this configuration in much detail, withmore attention being given to the common-source configuration.

Using a tuner, noise figure measurements were taken at sevendifferent source impedances. This allows noise parameters tobe determined, with the extra source impedances reducing theeffect of measurement errors on the noise measurements [10].Fig. 5 shows curves of the minimal noise figure determinedfrom measurements for two common-source fixtures. As canbe seen from the curves, the measured Fmin is around 1.5 dB,except for a spike around 6.5 GHz.

This large spike was not predicted by simulation. Electro-magnetic simulation of the integrated circuit does not indicate ahigh loss at this frequency, though this behaviour was observedin both common-source measurements. There appears to be anunexpected interaction involving the chip capacitor. Simulationsindicate a small dip on the insertion gain curve at this frequency,although not of the size indicated by the measured results.While its resonant frequency is not located in the measuredband, its parasitics could be worse than predicted or may beresonating with other parasitics in the circuit, leading to loss.

However, as shown in Fig. 6, high gain can be obtainedfrom the gallium nitride devices. With appropriate matching,19 dB gain can be obtained with the transistor remainingunconditionally stable. The problem discussed in the previous

6 7 8 9 100

2

4

6

Frequency [GHz]

F min

[dB

]

Fig. 5. Measured minimal noise figure, Fmin, for the fabricated common-sourceconfigurations

6 7 8 9 10

0

5

10

15

20

Frequency [GHz]

Gm

ax[d

B]

Fig. 6. Measured maximum available gain for the two fabricated common-source configurations.

paragraphs applies to the gain curves as well, with a largerthan expected dip appearing in the gain measurements.

From the S-parameters of the test fixture, a predictivemodel [8] was applied to determine the minimal noise figureof the entire circuit. To do this, the effect of the gate anddrain biasing circuits, as well as the stabilizing resistor had tobe removed from the measurements. The results were fittedto a small-signal HEMT model. Noise parameters were thencalculated using this model and the DC characteristics of thetransistor. The interested reader can find a more completedescription of this model in Ref. [8].

Fig. 7 shows the modelled minimum noise figure with theminimum noise figure determined directly from measurement

Page 4: [IEEE the American Electromagnetics Conference (AMEREM) - Ottawa, ON, Canada (2010.07.5-2010.07.8)] 2010 14th International Symposium on Antenna Technology and Applied Electromagnetics

6 7 8 9 100

2

4

6

Frequency [GHz]

F min

[dB

]

MeasuredModelled

Fig. 7. Measured minimal noise figure, Fmin and modelled minimal noisefigure for the common-source configuration.

results. As can be seen, the curves have roughly the samemagnitude, with the model predicting slightly higher noisefigure than was determined by measurements. The main differ-ence between the curves is mainly due to the aforementionedcapacitor issue around 6.5 GHz.

V. CONCLUSION

Some preliminary results pertaining to the use of hybridintegrated circuits for use in low-noise gallium nitride-basedsystems were discussed in this paper. Measurements indicatethat good noise figures (approximately 1.5 dB) are attainablewith an appropriate input matching network, even when usingdiscrete devices meant for designed for power applications.Further, it is also possible to obtain high gain using a hybridintegrated circuit.

Measurements and noise figure are in general agreement,with a predictive model indicating slightly higher noise figuresthan were measured. However, a capacitor issue appears to becausing higher than expected loss at one frequency in the bandof interest.

ACKNOWLEDGEMENTS

The authors would like to thank the Natural Sciences andEngineering Research Council of Canada (NSERC) for itsfinancial support.

The authors would also like to express their appreciationto Agilent Technologies, Inc., for the loan of measurementequipment.

REFERENCES

[1] R. Quay, F. van Raay, J. Kühn, R. Kiefer, P. Waltereit, M. Zorcic,M. Musser, W. Bronner, M. Dammann, M. Seelmann-Eggebert,M. Schlechtweg, M. Mikulla, O. Ambacher, J. Thorpe, K. Riepe, F. vanRijs, M. Saad, L. Harm, and T. Rödle, “Efficient AlGaN/GaN HEMTpower amplifiers,” in Proceedings of the 3rd European MicrowaveIntegrated Circuits Conference, October 2008, pp. 87–90.

[2] Y.-S. Lee, M.-W. Lee, and Y.-H. Jeong, “A 40–W balanced GaN HEMTclass-E power amplifier with 71% efficiency for WCDMA base station,”Microwave and Optical Technology Letters, vol. 51, no. 3, pp. 842–845,March 2009.

[3] B. Luo, J. W. Johnson, F. Ren, K. K. Allums, C. R. Abernathy, S. J.Pearton, R. Dwivedi, T. N. Fogarty, R. Wilkins, A. M. Dabiran, A. M.Wowchack, C. J. Polley, P. P. Chow, and A. G. Baca, “DC and RFperformance of proton-irradiated AlGaN/GaN high electron mobilitytransistors,” Applied Physics Letters, vol. 79, no. 14, pp. 2196–2198,October 2001.

[4] W. Lu, V. Kumar, E. L. Piner, and I. Adesida, “DC, RF, and microwavenoise performance of AlGaN–GaN field effect transistors dependenceof aluminum concentration,” IEEE Transactions on Electron Devices,vol. 50, no. 4, pp. 1069–1074, April 2003.

[5] S. Lee, K. J. Webb, V. Tilak, and L. F. Eastman, “Intrinsic noiseequivalent-circuit parameters for AlGaN/GaN HEMTs,” IEEE Transac-tions on Microwave Theory and Techniques, vol. 51, no. 5, pp. 1567–1577,May 2003.

[6] C. H. Oxley, “A simple approach including gate leakage for calculatingthe minimum noise figure of GaN HEMTs,” Microwave and OpticalTechnology Letters, vol. 33, no. 2, pp. 113–115, April 2002.

[7] S. L. Rumyantsev, N. Pala, M. S. Shur, and R. Gaska, “Effect of gateleakage current on noise properties of AlGaN/GaN field effect transistors,”Journal of Applied Physics, vol. 88, no. 11, pp. 6726–6730, December2000.

[8] C. Sanabria, A. Chakraborty, H. Xu, M. J. Rodwell, U. K. Mishra,and R. A. York, “The effect of gate leakage on the noise figure ofAlGaN/GaN HEMTs,” IEEE Electron Device Letters, vol. 27, no. 1, pp.19–21, January 2006.

[9] I. D. Robertson and S. Lucyszyn, RFIC and MMIC Design. London:The Institution of Engineering and Technology, 2001.

[10] R. Q. Lane, “The determination of device noise parameters,” Proceedingsof the IEEE, vol. 57, no. 8, pp. 1461–1462, August 1969.