Trends in Low-voltage Embedded RAMs Kiyoo Itoh, Kenichi Osada, and Takayuki Kawahara

Central Research Laboratoxy, Hitachi, Ltd. k-itoh@crl.hitachi.co.jp

Abstrucf-Low-voltage high-density embedded (e-) RAMs, focusing on RAM cells and peripheral circuits, are described. First, challenges and trends in low-voltage e-RAMS are described based on the SIB issue of RAM cells, and leakage and speed-variation issues of peripheral circuits. Next, state- of-the-art 'low-voltage e-DRAMS and e-SRAMs are investigated, focusing on leakage reduction. Finally, future prospects for rRAMs are discussed in terms of low-voltagc designs.

1. INTRODUCTION

Low-voltage high-density embedded RAMs (e-RAMS) aiming at sub-I-V operations are becoming increasingly important because they play critical roles in reducing power dissipation and chip size of MPU/MCU/SoC for power- aware systems. To create such e-RAMs, however, many challenges remain with RAM cells and peripheral circuits [ I , 21: For RAM cells, in addition to being the smallest and simplest cell possible, signal-to-noise ratio (Sm) must be maintained high to ensure stable operations because the ratio is always worsened at low voltages. Note that the ratio is closely related to the signal charge, signal voltage and leakage in a cell. For peripheral circuits both leakage and speed variations must he reduced [ I , 21 because they are prominent at a lower voltage even for a fixed design parameter variation. Unfortunately, the parameter variations are more enhanced as the devices are scaled down.

In this paper, first, challenges and trends in low-voltage e-RAMS are described in terms of the SM issue in RAM cells, and leakage and speed-variation issues of peripheral circuits. Next, state-of-the-art low-voltage e-DRAMS and e- SRAMs are investigated, focusing on leakage reduction. Finally, future prospects for e-RAMs are discussed. Here, of various leakage issues, subthreshold-current issue is mainly discussed.

11. CHALLENGES AND TRENDS r~ LOW-VOLTAGE e-RAMS

A. MMCeIls Signal Charge: Maintaining the signal charge (Q,) of non- selected cells [I , 21 is crucial because Q, is decreased as the power supply voltage (VDD) is lowered, and the storage- node capacitance of cell (C,) is decreased with device scaling. Otherwise, data-retention characteristics are degraded. Using an on-chip ECC as a system solution, and adding a capacitor to the cell node are effective solutions. Signal Voltage: Reductions in Vr variation (u(Vr)) and Vr mismatch (sV,) between paired MOSTs [ I , 21 lower the minimum value of operable VDD. In particular, a reduction in or compensation for sVr in flip-flop circuits (i.e., an

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SRAM cell itself and a sense amplifier) effectively increases the Qs or signal voltage on the data line. The reductions are crucial especially for the 6-T SRAM, the operations of which are sensitive to variations. Unfortunately, however, both o( Vr) and sVr of e-SRAMs are statistically and physically larger than those of e- DRAMS despite the use of a lithographically symmetric cell [3]. This is because more flip flops are used, and the FET size accepted in each flip flop is smaller, causing o(Vr) and N T t o be more susceptible to process variations. Gain cells such as 3-T cells [2] can overcome the issue with enough signal voltage even in an extremely low-voltage region. Leakage: Reducing subthreshold current is essential not only to maintain the refresh time of DRAM cells hut also to suppress an increase in the retention current of SRAM cells [l, 21. Thus, circuit development to control the gate voltage and Vr has been active. However, the Vr of the transfer MOST in the I-T DRAM cell must be high and is not scalable [ l , 21 to ensure the maximum refresh time (fREFmar)

through leakage reduction. Thus, the word-line voltage (V,) must be high for a full-VDD write to the cell, exemplified by 3.3V at VDD= 2V for a low-cost 64-Mb design and 1.7V at VDD = 1V for a high-speed 64-Mb design [4]. This V, is provided by the so-called word bootstrapping. Even with a low-actual Vr, the high Vr is effectively achieved by the so- called negative word-line (NWL) scheme that produces gate-source offset driving, as explained later. The Vr of the 6-T SRAM cell must also be quite high and is not scalable to meet retention-current specifications because subthreshold currents in the cell rapidly increase as Vr decreases, as shown in Fig. I [ I , 21. For a low-power design of a 1-Mb e-RAM that allows consuming a leakage of 0.1

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Fig. 2 Leakage reduction efficiency of various schemes [2].

pA at Tmu*= 75 "C, for example, the Vrat 25°C might be as high as 0.71 V. For a high-speed design accepting a larger leakage, the Vr can he as low as 0.49 V with a I-Mb e- RAM that allows consuming 10 pA at q),,ar= 50°C.

B. Peripheral Circuits Leakage: A high-speed reduction scheme applicable even to the active mode is essential because leakage eventually dominates the total active current of an e-RAM as Vr is lowered [ I , 21. Thus, it is better if the scheme reduces more leakage with a smaller voltage swing (i.e., better reduction efficiency) or confines the load capacitance to the small. If the scheme is applied to inactive (i.e., non-selected) blocks that dominate the total leakage of the e-RAM, the leakage of the e-RAM in the active mode is minimized. Fortunately, peripheral logic circuits in e-RAMS accept such schemes and reduce leakage easily and effectively [2].

Basic circuit concepts for reducing suhthreshold current are to use a higb-Vr MOST that is achieved with a high- actual-VT or a low-actual-VT MOST. Various reduction schemes [2] to raise the Vr of a low-actual V, MOST statically or dynamically have been proposed dating back to 1992 [2], as shown in Fig. 2. Of the schemes, gate-source backbiasing categorized as gate-source self-backbiasing (AI) and gate-source offset driving (A2) is best in terms of reduction efficiency. Speed Variations: Suppressing speed variations in peripheral circuits [2] is essential because the degree of speed variation for any given variation in design parameters is increased by lowering VDD. Unfortunately, design parameters such as Vr increase with technology scaling. The challenge, for example, is to control Vr stringently, compensate for Vr variation through controlling substrate biases or internal VDD generated by a voltage-down converter, or use new devices with less Vr variation.

111. STATE-OF-THE-ART e-DRAMS

A 0.09-pm 16-Mb e-DRAM [5] operating at a record- setting low voltage of 0.6 V was recently presented. It used a 0.195-pm2 trench capacitor (C,= 40 fF) I-T cell. The

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total operating power at 0.6 V and at a 20-11s row cycle was only 39 mW, and the standby and sleep-mode currents at 0.9 V and 105°C were as low as 328 and 34 pA, respectively. Figure 3 shows the data lines, each connecting 128 cells, and sense amps (SAS). Many internal voltages are generated by on-chip converters mainly consisting of charge pumps. An excessively boosted word voltage of 3 V is probably needed for a high-speed charging of a large C , rather than for a full-VDD write. Substrate biases of the SA and other periphery circuits are statically controlled in accordance with process and temperature variations to suppress the speed variations and subthreshold currents. Consequently, the speed of an inverter was improved by 63% for slow process conditions (i.e., high Vr), and the subthreshold current was reduced by 75% for fast process conditions (i.e., low V,), Instead, these significant improvements suggest that operations would be very sensitive to substrate noises. However, a triple-well structure for isolating the floating array substrate from floating pin peripheral substrates, coupled with half-VDD sensing, keeps these substrates quiet. A low Vr of 0.2 V is used for SA MOSTs (MlLM4) to enable high-speed half- VDD sensing, while a normal Vr of 0.3 V is used for SA- driver MOSTs (M5, M6) to reduce the dc current in standby mode. In the sleep mode, the gate-source offset driving of the NMOSTs and PMOST (above VDD and below VSS by 0.3 V) completely cuts the subthreshold currents. The RAM data is retained by periodically existing sleep mode and performing burst refresh cycles at 20 ns, as shown in the figure. The refresh scheme minimizes pump currents of the converters for -0.3 V and VDD +0.3 V, enabling a simple design for the converters. The gate-source offset driving and various switched-source impedances (SSls) [ I , 21 were used throughout sense-amp drivers and a row decoderiword driver block to reduce subthreshold currents. Mode transitions between active, standby, and sleep modes are fast because loads that on-chip voltage converters must drive are kept small.

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IV. STATE-OF-THE-ART e-SRAMs

Two circuit schemes [2, 71 have been proposed to reduce the leakage: raising the cell's NMOST source in the standby mode and maintaining the power supply of the cell high so that the VTand for.can he preserved high and thick.

Figure 4 illustrates a 0.13-pm 300-MHz I-Mb e-SRAM module operating at 1.2 V [6]. The leakage is reduced with three schemes: confining the active area to the small (#1 in the figure) by dividing a module into 4 hanks (BKO-BK3) to reduce the leakage to one-fourth by selecting only one hank with turning on M3 and M5; reducing the leakage in non- selected banks with switched-source impedance (SSI) [ l , 2](SSla and SSIw); and cutting the leakage of the peripheral circuits in the sleep mode with a power switch[2](#5). In non-selected hanks in the active or standby modes of the module, an impedance (MI) in SSla automatically creates a small raised voltage (6, at the common source of cells as a result of the subthreshold-current flows from many cells. Thus, the resultant suhstrate-source backhiasing (#3, B2 in Fig. 2) to the cross-coupled off-NMOST in each cell raises the Vr, enabling the leakage to he reduced. The necessary8 however, is large (e.g., 0.3 V) due to the bad reduction efficiency of the scheme, and the common source is heavily capacitive due to many cells being connected. Hence, high- speed operation is not possible. Here, the diode (M2) clamps the source voltage, so Qs is not reduced by an excessive6 SSlw also reduces the leakage of each off- PMOS in the word driver block three ways [2]: gate-source self-backbiasing (#2), substrate-source backbiasing (#3), and a drain-induced barrier lowering (DIBL) effect (M). The gate-source backhiasing, however, has the best reduction efficiency [ I , 21, necessitating a small 6~ for a large leakage reduction. In addition, the power-line capacitance of the word drive block can be light. Thus, leakage in the block is greatly and quickly reduced. Results indicated that leakage currents were reduced by 25%, 67%, and 95% for the high-speed active mode with only SSlw tuned on, for the slow-speed active mode with both SSIa and SSIw turned on, and for the sleep mode, respectively. Even so, however, a 1.2-V Voo is still high, and a reduced Q, in the standby mode would pose a problem.

Figure 5 shows the raised power-supply (VoH) scheme [2] High-Vr cross-coupled MOSTs are used to reduce subthreshold currents. Low-Vr transfer-MOSTs, coupled with the NWL scheme to cut leakage during non-selected periods, increase the cell read current. The resultant degraded static noise margin (SNM) is compensated for by increased conductance of cross-coupled MOSTs by the raised supply ( VDH) that is generated by a charge pump or a voltage-down converter of the U0 power supply. Furthermore, the VDH maintains the Qs and drivability of cross-coupled MOSTs despite a high V , and large o(Vr) and fir. Obviously, the cell current and SNM for the worst Vr combination are greatly increased for both a high-speed design of Vr = 0.49 V and a low-power design of Vr = 0.71 V even with a small boost of 0.1 V. Thus, the VDH scheme is

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Fig. 5 Raised power supply (V,) 6-T SRAM cell [21: (8) for cell circuit. and a buuertly curve in the worst V,eornbinalion for SNM and I,.,,. (b) and (c) for SNM and versus V,(Q,J for a high-speed design with V,(Q,J=V,(QLL)= 0.49 V and for a law-power design with V,(Q,J=V,(Q,J= 0.71 V. A 0.13-prn device model was used.

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Fig. 6 Comparisons between I-T and 3-T DRAM cell6 and 6-T SRAM cell.

likely to make a I-V operation possible even in the usual design conditions of a 100-mV SNM and 20-pA cell current, while the conventional VDD scheme (i.e., no raised power supply and a fixed high-Vr transfer MOSTs) makes a 1-V operation at Vr = 0.71 V impossible. It turns out that a 0.8- V operation is extremely difficult even for Vr = 0.49 V. Despite keeping MOST sizes to the same while others are scaled down, the cell size could be reduced for each technology generation.

A dynamic-double-gate SO1 (D2G-SOI) [7] reduces the Vr variation and the variation in Vr mismatch thanks to reductions in short and narrow channel effects and dopant atoms. In addition, the double gate MOST structure increases the on-current while decreasing the off-current, if the gate and well are connected. Thus, ifapplied to the 6-T cell, the SNM should be greatly improved.

V. FUTURE PROSPECTS

Figure 6 compares existing RAM cells in terms of cell size, signal charge Q,, and signal voltage. For the 6-T cell, the VDD scaling down to sub-I-V is extremely difficult, as explained previously, due to the requirement of a high Vr for a small retention current and ever-larger variations of Vr and sVr with device scaling. Moreover, decreased Qs as VDD is lowered unavoidably requires additional capacitance (C,) at the cell node to prevent soft errors from occurring. Thus, alternatives such as the raised power supply scheme and FD-SO1 cells are required. Even so, the large cell size of the 6-T cell will eventually limit the use of the cell to relatively small-memorycapacity applications. Although the I-T cell is smallest, it requires a large C, for enough signal voltage, while the 3-T and 6-T cells need only a small C, against soft errors. This calls for quite complicated processes for stacked or trench capacitors. Thus, much simpler capacitors are preferable. Structures that were intensively studied when the transition of planar capacitors to three-dimensional capacitors took place in the early 1980s might be candidates, if a small data-line capacitance array is combined to relax the requirement for the necessary C,. Gain cells [2] such as the 3-T cell widely used in the early 1970s might be used again, as suggested by a CAM

cell with a stacked capacitor (C, = 30 fF) [SI. This is because of the advantages they provide: low-voltage operation capability, relatively small size, and simple structures compatible with a logic process. This could happen if high-speed sensing is developed. Note that the word bootstrapping and NWL, which have been commonly used for modem DRAMS, will also improve the design flexibility of the 3-T and 6-T cells. A stable and reliable sensing will be extremely important at a lower VDD for peripheral circuits. Precise controls for internal voltages and low-power design for on-chip voltage converters and noise suppression-especially at substrates-will also be keys to solving subthreshold-current and speed-variation issues and stable operations. If FD-SO1 devices such as D2G-SO1 resolve V,variation issue even with increased cost, these devices will simplify peripheral circuit designs that make coping with the issue increasingly complicated. In addition, new gate insulators free from gate-tunneling currents must be developed soon.

VI. CONCLUSION

This paper presented challenges and trends in low-voltage RAMS in terms of signal charge, read signal voltage, and leakage in RAM cells and subthreshold current and speed variations in peripheral circuits. State-of-the-art e-DRAMS and e-SRAMs were then discussed. Based on these considerations, future prospects were considered with emphasis on the need for gain DRAM cells, new SRAM cells such as a boosted power-supply cell and fully-depleted SO1 cell, on-chip low-power voltage converters, and precise controls for internal voltages with converters for stable and reliable operations in both RAM cells and peripheral circuits.

REFERENCES Kiym Itoh, VLSI M e n m y Chip Design, Springer-Verlag. 2001 Y. Nakagome et al., “Review and prospects af lowvoltage RAM circuits,” IBM J. R & D, vol. 47, no. 516, pp. 525-552. Sep.lNov. 2003. K. Os& et al., “Universal-Vdd 0.65-2.0V 32 kB Cache using Voltage-Adapted TimingGeneration Scheme and a Lithographical- Symmetric Cell,” 2001 ISSCC, Dig. Tech. Papers, pp. 168-169, Feb. 2001. K. ltoh et al., “Review and Fuhm Prospects of Lowvoltage Embedded-RAM Cells.” CICC2004 Dig. October 2004. K. Hardee et al., “A 0.6V 205MHz 19.k tRC 16Mb Embedded DRAM,” 2004 ISSCC Die. Tech. Papers. pp. 494495, Feb. 2004. M. Yamaaka et al., “A 360 MHz 25;AIMbLeakage On-Chip SRAM Module Featuring Process-Variation Immunity and Low-Leakage- Active Mode for Mobile-Phone Application Processor,” 2004 ISSCC Dig. Tech. Papen, pp. 494495, Feb. 2004. M. Yamaoka et al., “Low Power SRAM Menu for SOC Application Using Yin-Yam-Feedback Memory Cell Technology,” Symp. VLSl Circuits Dig., June 2004. H. No& et al., “A 143MHz I .IW 4.5Mb Dynamic TCAM with Hierarchical Searchine and Shift Redundancy ArchitecNre.” 2004 ISSCC Dig. Tech. Pap&, pp. 208-209, Feb. 2004.

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