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A Contact Electromigration Study of AI-Si-Cu Alloys M. Repeta, J. Kolk, M. Saran, V.Q.Ho Northern Tel eco m Electron ics 185 Corkstown Rd., Nepean Ontario, K2H 8V4 Tel: (613) 763-2215 Fax: (613) 726-2661 Introduction With the advent of VLSl device density, new materials and technologies are being developed to ensure that interconnects and interlevel contacts are reliable. In addition to the use of Si doped AI, barrier metallization has been introduced to prevent electromigration-induced junction spiking. To enable increased current densities, Cu has also been added to the AI alloy. It could be argued that with the use of a barrier metal, silicon in the AI-alloy may be removed altogether. The experiments reported here were designed to ascertain the validity of this argument. Experiment Figure 1 illustrates the electromigration test structure used in this study. It consists of an n+ resistor, 4pm wide, on a p-type substrate. The resistors were stressed at a constant current of 22.5mA at 220°C, with the contact identified as #1 in figure 1 held at the highest potential. In the process used to fabricate these devices, a titanium silicide is formed in the contact windows by rapid annealing of a ~OOA sputtered titanium layer. This silkidation, performed at 750°C for 30 seconds in a nitrogen ambient, also forms approximately 150A of titanium nitride on the surface[l]. Following this, an additional 500A of reactively sputtered titanium nitride, 65OOA of aluminum alloy, and 500A of MoSip antireflective coating are deposited in a multi-chamber sputtering system. Three different aluminum alloys were investigated: AI-1 %Si, AI-O%Cu, and Al- l%Si-OS%Cu. A sample of 90 devices was tested in each case. The failure criteria chosen were a 50% increase in resistance, or 50pA of leakage to substrate. Results The predominant failure mode for the three metallizations studied in this work It should be noted that in the case of the AI-PhCu alloy, although was resistance increase. A lognormal plot showing the three failure distributions is illustrated in Fig.2. the predominant failure mode was resistance increase, 8% of the devices failed very early in the experiment because of high leakage current. This was not observed with the alloys containing alloys silicon, which were found to fail exclusively for high resistance. The I-V characteristics found in the majority of cases after stress shows a somewhat non-linear resistance between the two resistor contacts. More noticeably, the resistance between the resistor contact at the highest potential and the substrate is very high compared to the lower potential contact. In some AI-2%Cu devices, the two June 12-13,1990 VMlC Conference TH-0325-1/90/0000-0351 $01 .OO C 1990 IEEE 35 1

[IEEE Seventh International IEEE Conference on VLSI Multilevel Interconnection - Santa Clara, CA, USA (12-13 June 1990)] Seventh International IEEE Conference on VLSI Multilevel Interconnection

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Page 1: [IEEE Seventh International IEEE Conference on VLSI Multilevel Interconnection - Santa Clara, CA, USA (12-13 June 1990)] Seventh International IEEE Conference on VLSI Multilevel Interconnection

A Contact Electromigration Study of AI-Si-Cu Alloys

M. Repeta, J. Kolk, M. Saran, V.Q.Ho Northern Tel eco m Electron ics

185 Corkstown Rd., Nepean Ontario, K2H 8V4 Tel: (613) 763-2215 Fax: (613) 726-2661

Introduction

With the advent of VLSl device density, new materials and technologies are being developed to ensure that interconnects and interlevel contacts are reliable. In addition to the use of Si doped AI, barrier metallization has been introduced to prevent electromigration-induced junction spiking. To enable increased current densities, Cu has also been added to the AI alloy. It could be argued that with the use of a barrier metal, silicon in the AI-alloy may be removed altogether. The experiments reported here were designed to ascertain the validity of this argument.

Experiment

Figure 1 illustrates the electromigration test structure used in this study. It consists of an n+ resistor, 4pm wide, on a p-type substrate. The resistors were stressed at a constant current of 22.5mA at 220°C, with the contact identified as #1 in figure 1 held at the highest potential.

In the process used to fabricate these devices, a titanium silicide is formed in the contact windows by rapid annealing of a ~ O O A sputtered titanium layer. This silkidation, performed at 750°C for 30 seconds in a nitrogen ambient, also forms approximately 150A of titanium nitride on the surface[l]. Following this, an additional 500A of reactively sputtered titanium nitride, 65OOA of aluminum alloy, and 500A of MoSip antireflective coating are deposited in a multi-chamber sputtering system.

Three different aluminum alloys were investigated: AI-1 %Si, AI-O%Cu, and Al- l%Si-OS%Cu. A sample of 90 devices was tested in each case. The failure criteria chosen were a 50% increase in resistance, or 50pA of leakage to substrate.

Results

The predominant failure mode for the three metallizations studied in this work

It should be noted that in the case of the AI-PhCu alloy, although was resistance increase. A lognormal plot showing the three failure distributions is illustrated in Fig.2. the predominant failure mode was resistance increase, 8% of the devices failed very early in the experiment because of high leakage current. This was not observed with the alloys containing alloys silicon, which were found to fail exclusively for high resistance.

The I-V characteristics found in the majority of cases after stress shows a somewhat non-linear resistance between the two resistor contacts. More noticeably, the resistance between the resistor contact at the highest potential and the substrate is very high compared to the lower potential contact. In some AI-2%Cu devices, the two

June 12-13,1990 VMlC Conference TH-0325-1/90/0000-0351 $01 .OO C 1990 IEEE 35 1

Page 2: [IEEE Seventh International IEEE Conference on VLSI Multilevel Interconnection - Santa Clara, CA, USA (12-13 June 1990)] Seventh International IEEE Conference on VLSI Multilevel Interconnection

resistances between the resistor contact and the substrate have slightly increased and still remain very low but the resistance between the two resistor contacts has decreased considerably, from 70R before stress to 7R after stress. SEM analysis on several of these devices showed the presence of a metal filament between the two contacts, indicating that the diffusion barrier has failed catastrophically. A typical SEM micrograph is shown in Fig.3, for a typical failed device after the passivation has been removed.

Discussion and Conclusion

The major failure mechanism for all three alloys was found to be resistance increase at the contact where electrons flow from the silicon into the aluminum, due to electromigration of aluminum away from the contact area. The significantly higher values of median time to failure for the two alloys containing copper reflect the higher resistance to electromigration of these alloys.

In the case of AI-2%Cu, the early failures exhibiting junction leakage and/or metal filament growth are indicative of a failure of the barrier layer, probably due to barrier defectivity. Although no specific defect has been identified, it is plausible that a pinhole in the barrier would result in a small metal spike, formed by dissolution of silicon in aluminum during the sinter process. Such a defect could be small enough to be undetected initially, and yet be the site of current crowding in the electromigration test.

It is found that silicon in the aluminum alloy greatly reduces the incidence of early failures of the barrier layer. This may be due to the ability of Si in the alloy to suppress initial spiking at barrier defect sites.

The median failure times observed in this work suggest that the use of silicon- free aluminum alloys in conjunction with a contact barrier may be viable; however, the observed percentage of early failures indicates that the defectivity must be well controlled.

Reference

[ 1 ] V.Q. Ho, "Characterization of a Rapid Thermal Anneal TiN,O,/TiSi2 Contact Barrier", J. Electr.Mat.,Vol. 18, No. 4, 4989

352

Page 3: [IEEE Seventh International IEEE Conference on VLSI Multilevel Interconnection - Santa Clara, CA, USA (12-13 June 1990)] Seventh International IEEE Conference on VLSI Multilevel Interconnection

Contact to Sub. 2

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3-7 um 1 Contact Window 1 . 5 ~ 1.5um 7 4

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- TopView - - Side View -

Fig. 1 Schematic diagram of test structure used .- 'I---

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Fig.2 Contact failure distributions

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Fig.3 SEM of a catastrophic barrier failure

353