A New Short Circuit Power Model

for Complex CMOS Gates

Qi Wang, Sarma B.K. Vrudhula

Center for Low Power Electronics

Department of Electrical and Computer Engineering

The University of Arizona, Tucson, AZ 85721

qi,sarma@ece.arizona.edu

Abstract

In this paper we propose a new model for short circuit power estimation of CMOSgates. The short circuit power of a CMOS gate is estimated by converting the gate into

an equivalent CMOS inverter and all input signal waveforms into a single equivalent input

signal for the inverter. The channel width and the input to the equivalent inverter are

functions of the waveforms of all the inputs. This is di�erent from the traditional approaches

where only worst case situations are considered. HSPICE simulation of NAND gates using

a commercial 0.25 �m CMOS process show that the proposed new short circuit power model

for CMOS gates is much more accurate than previously reported models.

1 Introduction

Traditional power optimization and estimation techniques for digital CMOS circuits focuson the dynamic power dissipation, caused by charging and discharging the load capacitancesat the gate outputs. However, as the device sizes and threshold voltagea continue todecrease, the short circuit power dissipation (Psc) is no longer a negligible factor [5, 10].Psc is due to the simultaneous conduction of the PMOS and NMOS transistors duringthe input and output transitions. Although the problem of the Psc modeling for CMOSinverters has received a much attention recently [2, 7, 8, 10], little work has been done onthe Psc modeling of complex CMOS gates.

A common approach to solve this problem is to reduce a CMOS gate into an equivalent

inverter for short circuit power estimation. The key issue here is to determine the channelwidths of the transistors of the equivalent inverter and the e�ective input signal fed toit. This problem has been addressed for CMOS gate delay estimation in [3, 4, 6]. Thetraditional approach is to determine the e�ective input to the equivalent inverter based onfastest (slowest) input signal of the CMOS gate for parallel (series) connected MOSFETs [4,6]. This approach may result in signi�cant errors in delay estimation [3]. In [3], thee�ective signal is heuristically chosen to be the \average" of the overlapping input signalsof the CMOS gate, as shown in Figure 1. Although this approach improves the accuracy ofdelay prediction, it is not suitable for short circuit estimation. For example, in Figure 1(b),the short circuit current ows from VDD to GND from time t1 to t4. This is because after t4one of the PMOS transistors will be turned o� and no conducting path from VDD to GNDexists. However in the approximation shown in Figure 1(b), the e�ective signal (plotted

in dotted line) will be presented beyond t4. Therefore using the e�ective input signal inFigure 1(b) for short circuit power estimation will lead to inaccurate results.

t1 t2

t3 4t

t1

t34t

t2GND

Vdd

GND

Vdd

(a) (b)

Figure 1: Derivation of e�ective input signal toward estimating the output falling propa-gation delay of a 2-input NOR gate in [3]. The solid lines are the original input signalsand the dotted lines are the e�ective input to the equivalent inverter for di�erent relativedelays of input signals.

The traditional approach to compute the channel width of the equivalent transistoris also straightforward [6, 3]. For example, the equivalent transistor width of MOSFETsconnected in series is the inverse of the sum of the reciprocal of the channel width of eachindividual transistor; and the equivalent transistor width of parallel connected MOSFETsis simply the sum of the width of each individual transistor. In [4] a much better approx-imation for the equivalent transistor width is given where the equivalent transistor widthdepends on the relative delays of input signals. One shortcoming of this method is that itrequires computing technology dependent parameters using HSPICE simulation.

In this paper, we propose a new approach to the problem of Psc modeling for complexgates. The new solution can be viewed as a generalization of the methods in [3] and[4] in that both equivalent channel width and the e�ective input signal are dependent onthe relative delays of the input signals of the CMOS gate. Additionally, the models forcomputing the equivalent channel width and e�ective input signal are di�erent from [4]and [3] respectively.

We start with a 2-input NAND gate as shown in Figure 2(a). The model of an equivalentinverter of the 2-input NAND for Psc estimation for di�erent input combinations is describedin Section 2. The extension of the model to other complex CMOS gates is discussed inSection 3. Experimental results on the proposed model for 2-input NAND gates are shownin Section 4. Finally, conclusions and future directions of the work are given in Section 5.

2 Psc Model for 2-input NAND Gates

In this section, we present a new approach toward reducing a 2-input CMOS NAND gateto an equivalent inverter for Psc estimation. Given the equivalent inverter and the inputsignal, the Psc model for CMOS inverters proposed by [10] is used to estimate the shortcircuit power of the NAND gate. One key di�erence between the approach to be presentednext and other approaches [6, 3, 4] is that the derived equivalent inverter and input signalwill depend on the relative delays of the input signals. This will be further elaborated uponin Sections 2.1 to 2.3. For a switching signal k, let tk be the time the transition starts, sk

be the transition time and rk be the time when the transition completes, i.e. rk = tk + sk.The Transition window () of a gate is de�ned as the time interval when there exists adirect path from VDD to GND during the input and output transitions. Henceforth, it willbe referred to simply as a window.

CL

Vdd

Pa Pb

Na

Nb

a

b at t b rabr

a

b

(a) (b)

Figure 2: An example for e�ective input signal and equivalent inverter approximationof a 2-input NAND gate for Psc estimation. (a) A 2-input NAND gate. (b) The inputwaveforms.

2.1 Case 1. Both Inputs Changing from 0 to 1

When both inputs of a 2-input NAND gate change from 0 to 1, the output of the NANDgate will drop from 1 to 0. Note that in this case the driving path consists of the two NMOStransistors connected in series and the output will not change if any one of the inputs is01. The transistors responsible for the short circuit current are the two PMOS transistorsconnected in parallel. There will be a short circuit current as long as one of the inputs hasnot reached 1. Therefore, the window of the NAND gate when both inputs are rising canbe simply approximated by:

= max(ra; rb) � max(ta; tb) (1)

For example in Figure 2(b), the output voltage will not start to drop until tb since beforetb the input b is 0. The total short circuit current will become 0 at ra since both PMOStransistors are o� at that time. Therefore the time interval [tb; ra] is the only interval thenthere exists a direct path from VDD to GND.

The loading factor (L) for each input signal is de�ned as the ratio of the portion ofeach input signal transition within the window to the size of the window. For example,for the input waveforms of the NAND gate shown in Figure 2(b), = ra � tb; La =(ra � tb)= = 1; Lb = (rb � tb)=. The loading factor indicates how much each signal andthe corresponding transistor (the signal it is connected to) contributes to the overall short

1To be more precise, the output will not change if any one of the inputs is less than the NMOS threshold

voltage,Vt;n. Using logic value 0 or 1 instead of the threshold voltage values of PMOS and NMOS simplify

the discussion.

circuit current. In this example, the PMOS transistor Pa in Figure 2(a), is on within thewhole window period so its loading factor is 1. On the other hand, the PMOS transistorPb will be o� after rb, hence it contributes to the total short circuit current only duringthe time interval [tb; rb], i.e. Lb = (rb � tb)=. In general, the loading factor for the inputsignal k of a 2-input NAND gate when both inputs are rising can be computed as follows:

Lk =

(rk�max(ta;tb)

max(ra;rb)�max(ta ;tb)if rk > max(ta; tb)

0; otherwise.

)k = 1; 2 (2)

Note that if Lk = 0, it means that signal k will stay at the non-controlling value (logic1) during the whole transition period (window) of the other input signal.

Having de�ned the loading factor for each signal, the equivalent channel width of thePMOS and NMOS transistor of the equivalent inverter are calculated as follows:

Wp;eqv = La � WPa + Lb � WPb (3)

Wn;eqv =(WNaWNb

(2� La)(2 � Lb))

WNa(2� La) +WNb(2� Lb)

(4)

As an example, assume that WPa = WPb = WP and WNa = WNb= WN , and consider

the case when La = 1 and Lb = 1, i.e. both input signals start to switch at the sametime with the same slope. From Equations 3 and 4, Wp;eqv = 2WP and Wn;eqv = WN=2.These are exactly the same formulas used by the traditional approach for Psc estimation [3].Therefore Equations 3 and 4 are a generalization of the traditional approach to reducinga 2-input NAND gate to an equivalent inverter for delay estimation. As another example,when La = 1 and Lb = 0, Wp;eqv = WP and Wn;eqv =

23WN . This is as expected since the

PMOS transistor Pb is o� during the input and output transition time and does not causeany short circuit current to ow during the transition. On the other hand, the pull downpath should have better conductivity compared with the case when La = 1; Lb = 1 sinceNb will be always on during the period that the output falls. Note that either La or Lb willbe 1 all the time, therefore Wn;eqv is in the range of [12WN ,

23WN ].

Finally the slope of the equivalent input signal for the inverter is simply �1. Havingobtained the channel widths for the transistors of the equivalent inverter and the inputslope for the 2-input NAND gate, the Psc model given by [10] for inverters can be used toestimate the Psc of the gate.

2.2 Case 2. Both Inputs Changing from 1 to 0

The analysis of this case is similar to Case 1. The path responsible for the short circuitcurrent consists of the two NMOS transistors in series. The window can be calculated asfollows:

= min(ra; rb)�min(ta; tb) (5)

This is because as soon as one of the inputs start to fall, the path from VDD to GND alsostarts to form. The path will cease to exists if at least one of the inputs becomes 0. Theloading factor for the input k can then be calculated as.

Lk =

(min(ra;rb)�tk

min(ra;rb)�min(ta;tb)if tk < min(ra; rb)

0; otherwise.

)k = 1; 2: (6)

The formulas for theWp andWn are the same as those in Equation 3 with the exceptionthat di�erent loading factors are used. The equivalent input slope of the inverter is still�1. Note that the value of here is di�erent from the one obtained by Equation 1.

2.3 Case 3. One Input Rising and the Other Input Falling

If two transitions start far enough apart then the problem is reduced to the case whereonly one input switches. These have been been handled in case 1 and 2 where the loadingfactor of one input is 1 and the loading factor of the other input is 0. However, if thetwo transitions are su�ciently close, then the problem becomes more complicated. If thetwo transitions start at the same time and have the same transition time, then ideally theoutput will always stay at logic 1. Consequently no short circuit current ows during thetransition. However, if the two transitions start at di�erent times or start at the same timebut with di�erent transition times, then it is possible that a glitch will be presented at theoutput. In this case there will be some short circuit current. Unfortunately, a reasonablyaccurate estimation of this current requires complicated transient analysis of a transistorwhich is not practical. However, the glitch is normally smaller in magnitude compared tothe full output swing during a normal transition and therefore the short circuit current willalso be smaller. Our solution to this problem is that when the two transitions start at thesame time, the Psc is taken to be 0; when the two transitions start far enough apart, thesingle input transition model, a special case of Case 1 and 2, is used to reduce the gate toan equivalent inverter to estimate Psc.

3 Extension the Model to More Complex CMOS Gates

Another advantage of the above procedure is that it is easy to extend the model to morecomplex CMOS gates. For example, for a k-input NAND gate with all inputs rising, theresults are as follows:

Wp;eqv =kX

j=1

Lj WPj (7)

Wn;eqv =1Pk

j=111

WNj(2�Lj)

(8)

Lk =

(rk�max(t1;���;tk)

windowif rk > max(t1; � � � ; tk)

0; otherwise.

)(9)

= max(r1; � � � ; rk)�max(t1; � � � ; tk) (10)

In this case the discharging path consists of NMOS transistors connected in series. Therewill exist a short circuit path when all NMOS transistors are on until all input signals settleto logic 1, i.e. all PMOS being turned o�. Given the de�nitions of the window () and theloading factor (L), the above equations are easy to understand.

The models for other cases of NAND gates and NOR gates can be derived analogously.In general, to reduce k transistors connected in parallel (series) to an equivalent singletransistor, Equation 7 (8) should be used. However, the loading factors and the windowwill be di�erent for di�erent scenarios. First the window for a particular input transition

pattern and topology of the complex gate is determined. Then the loading factor of eachsignal can be easily calculated according to the de�nition.

4 Experimental Results

The proposed model of Psc for CMOS gates was veri�ed by HSPICE simulation on a 2-inputNAND gate for di�erent combinations of input waveforms. The Psc model for the equivalentinverter is from [10] which was shown to be very accurate for current deep submicrontechnology. The MOSFET model parameters and HSPICE models were obtained froma commercial 0.25 �m process. Three sets of experiments were conducted correspondingto the three sets of input waveforms shown in Figure 3. In each set of experiments twodi�erent load capacitances were considered, one of 50 fF and the other of 100fF.

..........

(a)

..... .....

(c)

..... .....

(b)

Input

a

Input

b

Figure 3: Input waveforms for di�erent sets of experiments of the Psc estimation of a CMOS2-input NAND gate. (a) Experiment setup I. (b) Experiment setupII. (c) Experiment setupIII.

Input waveforms for the experiment set I were shown in Figure 3(a). In this setup, inputa has a 2 nano second transition time for both rising and falling transition. The transitiontime of the input waveform b varies from 2 nano seconds to 5 nano seconds. Note that alltransitions start at the same time. For the experiment set II, both inputs have the sametransition time but the starting time of transitions were di�erent. The di�erence betweenthe starting time of a and b varies from 0 nano seconds to 5 nano seconds, assuming thata always starts to switch at time 0, as shown in Figure 3(b). Experiment setup III was acombination of I and II. That is, a and b have di�erent transition times as well as di�erentstarting times, as shown in Figure 3(c).

The experimental results are shown in Tables 1, 2, and 3. The column labeled CL

shows the load capacitance in fF for each experiment. P0 is the Psc value in micro wattsobtained from the HSPICE simulation. P1 and P2 were the Psc values obtained from theproposed model and traditional model respectively. The terms error1 and error2 are therelative errors of P1 and P2 as a percentage of P0. In Table 1, the column slew shows thedi�erent transition times for signal b in the experiment setup I. In Table 2, the column startshows the di�erent start times of signal b in the experiment set II. In Table 3, the columnsstart and slew were the start times and transition times of signal b in the experiment setIII.

From the experimental results we can see that the proposed Psc model for CMOS gateswas much more accurate than the traditional models. For example, for the experiment set

CL slew P0 P1 error1 P2 error2(fF) (ns) (� W) (� W) (� W)

50 2.0 6.36 6.023 -5.4% 6.02 -5.4%

50 2.5 6.21 7.29 17.3% 8.14 30.9%

50 3.0 8.15 8.551 4.9% 10.42 27.8%

50 3.5 9.20 9.849 7.0% 12.85 39.6%

50 4.0 10.75 11.196 4.1% 15.41 43.4%

50 4.5 12.32 12.593 2.2% 18.09 46.8%

50 5.0 13.70 14.039 2.5% 20.88 52.4%

100 2.0 5.38 4.68 -13.0% 4.68 -13.0%

100 2.5 4.85 5.616 15.8% 6.33 30.6%

100 3.0 6.09 6.558 7.7% 8.13 33.6%

100 3.5 7.39 7.538 2.0% 10.07 36.2%

100 4.0 8.59 8.563 -0.3% 12.11 41.1%

100 4.5 9.91 9.635 -2.8% 14.26 43.9%

100 5.0 11.10 10.752 -3.1% 16.51 48.7%

Avg 2.8% 32.6%

Table 1: Comparison of the proposed Psc model and the HSPICE simulation for a 2-inputNAND gate given the experiment setup I

I, the average error of the new model was within 3% of the HSPICE simulation while theerror of the traditional model was about 33%. Overall the new model was within 10% ofthe HSPICE simulation.

5 Conclusions and Future Work

Power estimation and optimization for deep submicron CMOS logic circuits requires ac-curate modeling of short circuit power dissipation [1]. In this paper we described a newshort circuit power model for CMOS complex gates. Unlike the traditional models, the newmodel is a function of the relative delays of the input transitions of the CMOS gates. Conse-quently the contributions of each input signal and the connected transistors to the total Pscof each transistor during the switching period can be accurately modeled for di�erent inputwaveforms, e.g. di�erent transition starting time and di�erent slopes. HSPICE simulationson a 2-input NAND gate with several input waveforms show that the new model is muchmore accurate than the traditional Psc models for CMOS gates which are normally basedon the worst case analysis. Since limited computation is required in the new models, thesemodels can be used for accurate short circuit power estimation for modern VLSI circuitswith millions of gates.

Future directions of the work in this area can be pursued in the following ways: (1)verifying the model with more complex CMOS gates, i.e. AOI gates, by HSPICE simulation;(2) solving the problem of Psc estimation for simultaneous and opposite input switching;(3) utilizing the new models at the gate level for the short circuit power minimization ofCMOS circuits.

CL start P0 P1 error1 P2 error2(fF) (ns) (� W) (� W) (� W)

50 1.0 6.35 6.02 -5.1% 6.02 -5.1%

50 1.5 5.67 6.12 8.0% 6.02 6.2%

50 2.0 5.91 6.02 1.9% 6.02 1.9%

50 2.5 5.48 5.74 4.7% 6.02 9.8%

50 3.0 5.52 5.27 -4.5% 6.02 9.1%

50 3.5 5.48 5.27 -3.8% 6.02 9.8%

50 4.0 5.47 5.27 -3.5% 6.02 10.1%

50 4.5 5.46 5.27 -3.4% 6.02 10.4%

50 5.0 5.45 5.27 -3.2% 6.02 10.5%

100 1.0 5.35 4.68 -12.4% 4.68 -12.4%

100 1.5 4.44 4.71 6.2% 4.68 5.5%

100 2.0 4.32 4.60 6.3% 4.68 8.2%

100 2.5 4.17 4.35 4.2% 4.68 12.2%

100 3.0 3.98 3.96 -0.5% 4.68 17.6%

100 3.5 3.89 3.96 1.9% 4.68 20.3%

100 4.0 3.87 3.96 2.4% 4.68 20.9%

100 4.5 3.85 3.96 3.0% 4.68 21.7%

100 5.0 3.85 3.96 3.0% 4.68 21.6%

Avg 0.3% 9.9%

Table 2: Comparison of the proposed Psc model and the HSPICE simulation for a 2-inputNAND gate given the experiment setup II

6 Acknowledgement

We wish to thank Dr. Tom Dillinger with the Rockwell Semiconductor Systems, in SanDiego, California for his support of this work. This work is also supported by Centerfor Low Power Electronics (CLPE). CLPE is an NSF S/IUCRC center with industrialsupport by Analog Devices, Analogy, Ambit, Burr Brown, Gain Technology, interHDL,Intel, Microchip, Motorola, Rathyeon, Rockwell, Texas Instruments, and Western Design.

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CL start slew P0 P1 error1 P2 error2(fF) (ns) (ns) (� W) (� W) (� W)

50 1.0 5 10.82 10.37 -4.1% 20.88 93.0%

50 1.5 4 8.48 8.17 -3.7% 15.41 81.8%

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100 3.0 1 2.61 1.94 -25.7% 1.94 -25.7%

Avg -9.3% 50.6%

Table 3: Comparison of the proposed Psc model and the HSPICE simulation for a 2-inputNAND gate given the experiment setup III

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