IEEE JOURNAL ON SELECTED AREAS IN ...faculty.poly.edu/~tsr/wp-content/uploads/CV/MTJ/2009-10...IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 27, NO. 8, OCTOBER 2009 1367 On-Chip

IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 27, NO. 8, OCTOBER 2009 1367

On-Chip Integrated Antenna Structures inCMOS for 60 GHz WPAN Systems

Felix Gutierrez, Jr. Student Member, IEEE, Shatam Agarwal, Student Member, IEEE, Kristen Parrish, StudentMember, IEEE, and Theodore S. Rappaport, Fellow, IEEE

Abstract—This paper presents several on-chip antenna struc-tures that may be fabricated with standard CMOS technology foruse at millimeter wave frequencies. On-chip antennas for wirelesspersonal area networks (WPANs) promise to reduce interconnec-tion losses and greatly reduce wireless transceiver costs, whileproviding unprecedented flexibility for device manufacturers.This paper presents the current state of research in on-chipintegrated antennas, highlights several pitfalls and challengesfor on-chip design, modeling, and measurement, and proposesseveral antenna structures that derive from the microwavemicrostrip and amateur radio art. This paper also describesan experimental test apparatus for performing measurements onRFIC systems with on-chip antennas developed at The Universityof Texas at Austin.

Index Terms—WPAN, 60 GHz, RFIC, CMOS, on-chip an-tenna, millimeter wave, mmWave communications, passive ra-diating elements.

I. INTRODUCTION

W ITHIN the past decade, the wireless communicationscommunity has become increasingly interested in the

worldwide 60 gigahertz (GHz) radio frequency (RF) band [1],[2], [3], [4], [5], [6], [7], [8]. In 2001, the United StatesFederal Communications Commission (FCC) released 7 GHzof bandwidth (57-64 GHz) for unlicensed use, while othergovernments have similarly allowed portions of the 60 GHzband to be used without a license. While the precise frequencyallocation is different in each country, all bands share acommon 5 GHz of continuous bandwidth centered at 60 GHz(see Figure 1). The IEEE 802.15.3c WPAN committee hasbeen advancing technologies in this frequency band since2003.With such a large RF bandwidth available at 60 GHz,

data rates of several gigabits per second (Gbps) are attainablewithin local areas, greatly surpassing possible wireless trans-mission capability. Wireless personal area networks (WPANs)at 60 GHz will revolutionize the home, workplace, andclassroom, and will enable a vast array of applications, suchas uncompressed high definition media transfer. Libraries ofbooks, high definition movies, and data files will be transferredin seconds.

Manuscript received 1 April 2009; revised 31 March 2009.All authors are with the Wireless Networking and Communications

Group (WNCG), in the Department of Electrical and Computer Engi-neering, The University of Texas at Austin, Austin, TX, 78712. Portionsof this work have been submitted for presentation in IEEE Globecom2009. This project is funded by the US Army Research Laboratory undercontract number W011F-08-1-0438, and the WNCG Industrial Affiliatesprogram (e-mail: [email protected], [email protected], [email protected], [email protected]).Digital Object Identifier 10.1109/JSAC.2009.091007.

Fig. 1. 60 GHz frequency bands in various countries, from [5], [6].

In order for 60 GHz technology to be adopted rapidly,device and system costs must be kept as low as possible.Integrated circuit (IC) fabrication processes such as SiGe andGaAs are suitable for analog circuits operating at 60 GHz,but are relatively expensive. Fully integrated CMOS offersthe greatest cost savings and highest yield, especially whenconsidering packaging, integration, and interconnect issues.CMOS IC technology, which has been optimized for digitalcircuitry and is used extensively by most fabless semicon-ductor manufacturers throughout the world, is a cost effectivesolution for millimeter wave RF devices.

As described in the literature [9], [10], [11], [12], [13],[14], [15], [16], RF circuits and systems operating at 60 GHzusing CMOS technology are now viable and can be producedusing standard fabless techniques at foundries such as TSMCand UMC. However, integration of the antenna with the RFelectronics on one chip in a single, standard fabrication cycle,is a novel approach that has only recently received attention.Implementing an antenna in the same semiconductor processas integrated circuits is called an integrated antenna, and hasbeen pioneered in [17], [18], [19], but the utility and value ofthis approach in a single fabrication process is most apparentfor millimeter wave systems [10], [11], [20], [16]. While otherauthors have made use of techniques such as the dielectriclens, these techniques require extensive deviation from thestandard CMOS process [21], [22], [23].If the radiating elements of a 60 GHz transceiver could

be integrated with the other electronics on a single chip in astandard CMOS process, a great deal of cost savings wouldbe realized, both at the chip level, as well as for the manufac-

0733-8716/09/$25.00 c© 2009 IEEE

1368 IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 27, NO. 8, OCTOBER 2009

turer of the wireless product. Today, wireless communicationdevices such as personal computers and cell phones typicallycontain six or more separate radio transceivers. For example,standard laptops already have transceivers for Bluetooth, WiFi,Cellular (Wide Area Network), dual band PCS, and UWBradios contained in a single consumer product. The numberof radios in a laptop computer or high-end cell phone willonly increase over time, and it is clear that more standardsand technologies will dictate the need for as many as 12 to 14radios in high end personal communicators by the year 2012.By producing on-chip antennas in a standard CMOS circuit

fabrication cycle, multiple manufacturing issues are eliminatedor lessened. Unshielded “windows” in the device casing couldallow RF waves to propagate to and from the on-chip an-tenna, enabling manufacturers to eliminate complex embeddedantenna and expensive feedlines and cabling that are usedtoday. At 60 GHz, the physical dimensions of antennas aresuch that they can fit on a small (e.g. 5mm X 5mm) die,suggesting that an entire system on a chip can be manufacturedinexpensively in one step without any special packaging ordifficult assembly or wiring. Even if on-chip antennas arefabricated as stand alone chips, separate from the bulk ofRFIC electronics, the savings and design flexibility realizedby original equipment manufacturers (OEMs) of consumerelectronic (CE) devices (e.g. laptops, set top boxes, cellphones, etc.) would be substantial. If antennas became simplesocket solutions, OEMs could simply place many low costantenna chips throughout the printed circuit board (PCB) whileusing simple PCB transmission lines and switching/phasingto provide arbitrarily high-gain radiation patterns that workin concert with the particular mechanical and physical layoutand shielding of a CE device. Essentially, on chip antennas,whether passive or active (with basic RF amplification stages),would provide many degrees of freedom for the design andimplementation of CE devices, while eliminating or greatlyreducing the Bill of Material Costs for RF antennas. The largeantenna gains and pattern flexibility at 60 GHz will supportreliable low power, high bandwidth communications over shortdistances with minimal power drain, as the antenna gains aretraded for transmitted power consumption to overcome RFpropagation losses and obstructions in the channel [7], [8].Unfortunately, combining RFIC electronics with integrated

antennas at 60 GHz poses several major challenges. One majorissue is the materials used in standard CMOS technology arenot optimized for millimeter wave structures, thus as the oper-ating frequency approaches the millimeter wave regime, deviceperformance deteriorates due to losses in the metallizationlayers as well as losses in the doped bulk silicon substrate.Additionally, models for passive and active devices at 60

GHz are not yet thoroughly proven and are continuing toevolve. The discrepancy between simulation and actual per-formance of 60 GHz radiating devices introduces the need forextensive iterations to improve today’s simulation tools. De-termining radiating fields from the CMOS substrate requiresrobust and accurate field solvers, and many of the commercialfield solvers have not been rigorously tested or verified bymeasurement at 60 GHz and above. Furthermore, specializedmeasurement systems are needed to experimentally determineradiation efficiencies, gains, and impedances of on-chip anten-

nas. Researchers must develop a strong feedback loop betweenproven millimeter wave simulation capabilities, fabricationtechniques, and measurement capabilities of devices in orderto develop design guidelines for on-chip antennas at 60 GHz.Finally, after the challenges of fabricating an antenna onto

a substrate are met, the integration of this antenna withactive circuitry introduces more challenges. On-chip antennasoperate best when mounted on thick, low dielectric substrates.However, active components perform better on thin, highdielectric substrates [24]. Therefore, in theory, one cannotimplement maximally performing circuitry on the same chipas an optimal antenna. Also, an on-chip antenna could radiateonto RF circuitry contained in the same chip, which couldcause deleterious electromagnetic interference (EMI).This paper summarizes the emerging field of integrated

antennas. Section II describes recently reported results inthe field of 60 GHz integrated antennas. Section III presentsseveral novel antenna concepts, with extensive simulation re-sults. These antenna concepts indicate promising approaches,as well as challenges that must be overcome. Section IVdescribes an experimental measurement system developed atThe University of Texas at Austin for the test and measurementof on-chip antennas and RFICs up to 67 GHz. The paperconcludes with a synopsis of results from this work.

II. PAST WORK IN 60 GHZ ON-CHIP ANTENNAS

Previous researchers have reported on-chip antennas usingCMOS processes for use in the 60 GHz band. Several differentantenna configurations have been simulated, fabricated, and toa much lesser extent, verified by measurement.Y. P. Zhang, et al., have implemented both inverted-F and

quasi-Yagi antennas on a standard low resistivity substrate(10 Ωcm) [25]. These antennas were implemented with aspecialized BEOL technology to overcome the challengescaused by the substrate. In this fabrication, proton implantationin the substrate is used to increase the resistivity, reducesubstrate losses, and improve performance.The maximum radiation for the inverted-F antenna occurred

above the antenna, and radiation along the horizon (off theedge of the chip) was 32 dB weaker than at the zenith(directly above the chip). Using the Zeland IE3D simulationtool, the authors found a radiation efficiency of 3.5%, whichis unfortunately typical in much of the literature to date. Bycomparison, typical radiation efficiencies for antennas in freespace are much higher, on the order of 70% or more.The quasi-Yagi in [25] was found to exhibit maximum gain

in a direction directly above the substrate of the chip (atzenith), and not off the end of the chip (on the horizon) aswould be expected for a Yagi antenna in free space. The max-imum gain was measured as -12.5 dBi at 65 GHz. Simulatedradiation efficiency was 5.6%. The crosspolarization radiationfor this antenna (shown in Figure 6 of [25]) is significantlyweaker than the copolarization radiation.While return loss and maximum gain were measured with a

probe station and network analyzer using a method describedin [25], the authors did not measure radiation patterns. Also,the authors defined their simulation substrates as an infiniteperfectly conductive ground plane. This simple yet unrealisticassumption can greatly alter simulation results.

GUTIERREZ et al.: ON-CHIP INTEGRATED ANTENNA STRUCTURES IN CMOS FOR 60 GHZ WPAN SYSTEMS 1369

In 2008, researchers from National Cheng Kung Universitycreated a coplanar waveguide (CPW) feedline and an on-chip 3-element Yagi antenna in standard 0.18 μm CMOStechnology [26]. The authors used Ansoft HFSS to simulatethe antenna structure and obtain a radiation efficiency ofapproximately 10%. As in [25], no radiation measurementswere made for the on-chip antenna. Antenna gain was reportedas -10.6 dBi at 60 GHz.These same authors also implemented a triangular

monopole antenna in the same 0.18 μm CMOS technology[27]. The simulated radiation efficiency of this antenna wasapproximately 12%. The maximum value of the gain wascalculated from S-parameters to be -9.4 dBi at 60 GHz.It is clear from past works that the design and implemen-

tation of on-chip antennas is difficult and very inefficient.Most of the structures presented in literature radiate withmaximum gain directly above the chip (0 ◦ from zenith), andnot off the end (approaching the horizon) as a typical Yagior horizontally oriented antenna would behave in free space.Gain and radiation efficiencies are very poor, typically yieldinggains of -12 dBi to -16 dBi. Additionally, antenna radiationpatterns have not been measured for any of the antennas in[27], [26], [25].

III. NEW CONCEPTS FOR 60 GHZ INTEGRATEDANTENNAS

One challenge with designing antennas to be fabricated on-chip is the small distance (typically several microns) betweenradiating elements, the surrounding metal layers, and the bulksilicon of the IC. Interactions with the ground plane and thelossy silicon substrate causes near field energy to dissipaterapidly around the antenna, which greatly reduces radiationefficiency and gain.Researchers and amateur (ham) radio operators have long

known of the issues of transmitting over ground planes. Hamshave designed passive high-gain antennas to communicateover great distances throughout the world. Stacking and phas-ing these directional antennas in an array boosts gains evenfurther at HF frequencies. By adapting passive directionalantennas in the amateur radio art at frequencies between 1and 30 MHz, it is conceivable to create high gain antennasat millimeter-wave frequencies on ICs by properly scalingantenna dimensions. Antennas such as the rhombic [28], theYagi, the long wire [29], and even low-profile [30] and loopantennas [31] have been commonly used in amateur radio,but are now considered for the novel application of passiveintegrated millimeter wave antennas. This section considersthe design of popular HF antennas (the dipole, Yagi, rhombicand loop) for use at millimeter wave frequencies on a CMOSsubstrate.

A. Overview of simulation methods

We considered a substrate model for standard CMOS0.18μm IC technology as shown in Figure 2. We model achip with common dimensions of 5 mm x 5 mm with 6metal layers above bulk silicon. Since the modeled groundplane is confined to the dimensions of the chip, diffractionmay introduce radiation on the lower hemisphere (below the

Fig. 2. Illustration of IC model including silicon dioxide layers for a typicalCMOS integrated circuit. Not to scale.

die). The dielectric between metal layers (silicon dioxide) ismodeled as lossless, while the losses in silicon bulk substrateare modeled with conductivity (σ) of 10 S/m, as in [25] andin [32].Realistic millimeter wave antennas were modeled with

Ansoft HFSS (High Frequency Structural Simulator), a leadingcommercial finite element method field solver which simulatesthree-dimensional structures and produces S-parameters andradiation patterns. HFSS is used in both [26] and [27] , aswell as numerous other works.The effective wavelength at 60 GHz for an IC substrate is

estimated by using the frequency and material properties ofthe top IC layer (silicon dioxide, εr = 3.9), where

λfreespace =1√

ε0μ0f(1)

λeff =1√εμf

=1√

ε0εrμ0f=

λfreespace√εr

. (2)

where λfreespace is 5 mm for 60 GHz, and λeffective iscalculated by including the effect of the dielectric constant.Here, λeffective = 2.53 mm.We explored on-chip antennas based on the basic half-wave

dipole, the multi-element Yagi, the rhombic antenna, and theloop antenna. These simple antennas have historically beenvery reliable and provide reasonable gain, high front-to-backand front-to-side ratios, and radiation near the horizon.We identified the following key issues: a) how performance

is a function of on-chip placement of radiating elements; b)how design guidelines should be applied to on-chip antennadesign, and how these guidelines differ from standard antennadesign in free space above ground; c) the tolerances thatexist between the widths, lengths, and spacings for variousradiating and parasitic on-chip elements; and d) the maximumachievable gain, and the direction of this maximum gain, fora wide range of new integrated passive on-chip antennas.

B. Feed systems

In order to accurately simulate antennas, the feed systemsthat carry the signal from the on-chip circuit output to theantenna inputs must also be simulated with a 50 Ω source.Simulations of antennas without feed systems were slightlydifferent from those of the antennas fed by simple feedstructures. Two feed systems were examined in simulation.The concept of stacked vias was used to form these feed

lines. For the dipole antenna, a via is extended from Metal 6


Fig. 3. Feed system for the dipole antenna.

Fig. 4. Feed system for the Yagi antenna.

down to Metal 1, to transfer the signal from an inner layer tothe top layer. For initial calculations, we approximated the twoparallel vias as a parallel plate waveguide, in order to derivedimensions that would approach a 50 Ω impedance.From [33], the parallel plate feedline has an impedance

of Zo = η bw , where w is the width of the transmission line

plates, b is the spacing between plates, and η is the intrinsicimpedance in the material. By noting that η in silicon dioxideis approximately half of η in free space, we deduced the properspacing between the two feed plates should be approximately14 the width of the dipole elements to maintain a 50 Ωimpedance. This feed system is shown in Figure 3. Metal 1is the lowest metal layer, where RF electronics interconnect,and Metal 6 is the top layer, where antenna elements wouldmost likely be fabricated. The signal is fed from the on-chipoutput to the Metal 1 layer and connected to the antenna onMetal 6 by a stack of vias on each side.For the Yagi antenna, a slightly different via feed system

was used, shown in Figure 4. The Yagi feed had wider viascompared to the parallel plate transmission line used in thedipole model (discussed below), in order to demonstrate thesensitivity of feed line performance to manufacturing variabil-ity. Our simulations showed negligible differences between thetwo feed systems.The rhombic and loop antennas were fed directly with a

60 GHz source and a 50 Ω source impedance. Due to the

Fig. 5. Top view of on-chip integrated dipole antenna (not to scale) andradiation pattern for this antenna. Maximum gain is -7.3 dBi (radial powerunits are in dBi). As indicated, φ is the azimuthal angle in the XY plane,where the X axis is 0 ◦ and the Y axis is 90 ◦. θ is the elevation angle wherethe Z-axis is 0 ◦, and the XY plane is 90 ◦.

Fig. 6. S11 characteristics of two dipole antennas with different elementwidths.

wideband nature of the rhombic antenna, additional matchingnetworks were not necessary to achieve a sufficient impedancematch. Unless otherwise stated, all simulations used a sourcewith a standard 50 Ω impedance to excite the antennas.

C. On-chip dipole antenna at 60 GHz

To understand on-chip antenna properties, we first consid-ered half-wavelength dipoles using a wide range of line widthsand orientations. The best performance with respect to gainwas obtained by placing a center fed dipole on the edge ofthe chip (See Figure 5).Using equation (2), an on-chip dipole with leg length λ/4

= 632.5 μm was simulated using a 30 μm antenna width.Each dipole λ/4 element was shortened to 570 μm to shiftminimum S11 up to 60 GHz as seen in Figure 6. MinimumS11 shows an optimal impedance, to improve power transferand efficiency. When the width of the dipole elements isdoubled to 60 microns while keeping the lengths the same,we observed that S11 is minimized at 56.5 GHz (as opposedto 59.5 GHz). If the dipole is mounted on the center of thechip, as opposed to the edge, then the gain is a very poor -13.6 dBi, due to the lossy substrate and the close proximity ofthe radiation angle to the horizon. As shown in Figure 5, theedge mounted antenna (width of 30 μm) exhibits maximumgain of -7.3 dBi at an elevation angle of 0 ◦ above the substratehorizon (θ = 90 ◦), and has a typical broadside pattern. This


Fig. 7. Top view of three individually simulated two-element on-chip Yagiantennas (not to scale). The Yagi antenna was simulated at the center, lowerright corner, and right edge of the 5mm x 5mm chip.

directionality provides the on-chip circuitry some radiationprotection. Radiation efficiency is still poor, at approximately9%. With element widths of 60 μm, the maximum gainincreases to -6.7 dBi, approximately 9 dB less than that of afree space dipole antenna. These significant changes highlightthe importance of understanding antenna performance on-chipas it is relatively unknown today.

D. On-chip Yagi antenna at 60 GHz

The Yagi antenna uses parasitic metals around the dipole toreflect and direct energy to achieve increased gain. There areseveral degrees of freedom when designing a Yagi antenna,such as the spacing, lengths, and widths of each parasiticelement. We examined how spacing and widths affect Yagiperformance on silicon, as well as the optimal antenna orien-tation to achieve maximum gain.Simulations of a 2-element Yagi, consisting of a driven

element and a parasitic reflector, showed highest gain whena Yagi antenna was centered along the chip edge as shownin Figure 7. Using a thinner dipole width w = 15 μm, theYagi dipole (driven element) length was adjusted to maintain aminimum S11 at approximately 60 GHz. Optimal performancewas found when each leg of the driven element was increasedto � = 597 μm (approximately 5% longer than the singledipole). The center feed spacing between each λ/4 elementwas 7 μm.We first investigated performance as a function of the

distance between the reflector and the driven element of aYagi antenna. The Yagi dipole was placed at the center ofthe 5mm x 5mm chip. According to [31], Yagi reflectorsin free space should be spaced between 0.15λ and 0.20λ.Given that the Yagi quarter-wave driven element resonatedat � = 597 μm, we estimated the wavelength to be 2.388mm, which is comparable (within 4%) to our result from(2), and denoted this length as λ. A reflector was iterativelypositioned from 0.01λ to 0.25λ in increments of 0.01λ awayfrom the dipole. We observed S11 and gain. The reflectorwidth wy was identical to the dipole (15 μm) and the lengthwas set to �y = 0.55λ, as suggested by [31]. Figure 8 showsa comparison of S11 of the Yagi antenna as the reflector

Fig. 8. S11 (dB) as the reflector is moved away from the driven element.Spacing is measured from the edge of the driven element to the edge of thereflector. Also shown is the centered 597 μm dipole quarter-wave elementwithout any reflector and the scaled 574 μm quarter-wave element dipolewith the 0.11λ-spaced reflector.

Fig. 9. Gain of a dipole vs. a .25λ-spaced reflector Yagi. The left plot iselevation (φ = 90 ◦) and the right is azimuth (θ = 90 ◦). Radial power unitsare in dBi.

was moved away from the dipole. Note the S11 resonanceis shifted to a lower frequency when a reflector is added andthe minimum S11 occurred when the Yagi reflector was 0.11λaway from the dipole. To bring the resonance back up to 60GHz using a 0.11λ spaced reflector, each driven element wasscaled down to 574 μm in order to resonate at the appropriatefrequency, denoted in Figure 8. Gains also increased slightlywith the addition of the reflector, which is consistent withantenna theory [31]. Gains also increased as the reflector wasmoved away from the dipole. At spacings between 0.20λ and0.25λ, the maximum gains were very similar, with a reflectordistance of 0.25λ having the highest gain at the horizon,shown in Figure 9. At distances larger than 0.25λ, gain wasfurther diminished. Thus, it appears Yagi antennas with a0.25λ reflector spacing exhibit both a reasonable S11 to a50Ω source impedance and maximum horizon gain.With a 0.25λ spacing between the driven element and the

reflector, we investigated the role of reflector width in Yagiperformance. The spacing was held constant at 0.25λ fromthe edge of the driven element to the edge of the reflector.S11 decreased slightly by 1 dB overall as the reflector widthwas increased from 15 μm to 160 μm. We noted incrementalgain increases as width was increased, differing only by 0.5dB over the entire range of widths. This shows that the widthof the reflector conductor does not appreciably impact gain or


Fig. 10. S11 changed drastically as the 60 GHz on-chip Yagi antenna wasmoved to different locations on the IC. “Edge” denotes right edge, and “EdgeEdge” denotes lower right corner. “Dipole” is the 597 μm dipole placed atthe center.

Fig. 11. Reactance (the imaginary part of impedance) was measured foreach antenna. Note that the center-located Yagi had a reactance close to zeroand provided the best S11 response at 60 GHz.

impedance matching of the on-chip Yagi. As we will showsubsequently, this does not hold true for rhombic antennas.Next, we investigated how Yagi performance changes as

the antenna is moved across the chip. We used the 0.25λ-spaced reflector with width 160 μm. We placed the antennaat the center, right edge, and lower right corner of the chipas seen in Figure 7. We noted large variations in S11 asthe Yagi antenna moved from the center of the chip to theedges, as seen in Figure 10. The minimum S11 occurred atfrequencies above 60 GHz as shown. Adjusting the lengths ofthe driven elements gave minimum S11 at 60 GHz, thoughdid not provide an acceptable impedance match (S11 is largerthan -10dB, even at the minimum). This emphasizes the valueof choosing the appropriate location for on-chip antennas.Figures 12 and 13 show the resulting S11 and gain changes asthe antenna is moved, respectively with adjusted impedance.The performance is compared to that of a dipole at the centerof the chip. The 2-element Yagi along the right corner of thechip achieved the highest gain of -3.55 dBi, a front-to-backratio of 10.4 dB, and maximum radiated intensity at 20 ◦ abovethe horizon. The efficiency was 15.8%, which is much greaterthan the numbers reported in [27], [26], [25]. By moving theYagi antenna to an edge, maximum gains improved by 7.65dB compared to the Yagi located at the center of the chip andby 10.05 dB over a dipole at the center of the chip.

Fig. 12. S11 (dB) parameter as the Yagi antenna is moved across the chip.

Fig. 13. Antenna gains as the Yagi antenna is moved across the chip. Theleft plot is elevation (φ = 90 ◦) and the right is azimuth (θ = 90 ◦). Radialpower units are in dBi. The radiation plots from Figure 9 are reproduced here.

Impedance transformation components may be necessaryto improve the impedance match to an acceptable level.The impedances of the Yagi antennas at each location wereextracted (Figure 11). We noted that the centered Yagi’s reac-tance close to zero provided excellent S11, and we proceededto adjust the 50 Ω source impedance by the respective amountsfor the edge and corner Yagi. The source impedance fed tothe Yagi along the edge was adjusted to 50 + j33 Ω and thesource impedance fed to the Yagi at the corner was adjustedto 50 + j60 Ω.

E. On-chip rhombic antenna at 60 GHz

The rhombic antenna is a diamond shaped broadband di-rectional antenna commonly used in the 3 - 30 MHz fre-quency range by shortwave broadcast stations and ham radiooperators. Large rhombic structures are constructed severalmeters above ground. Here we consider scaling them to on-chip solutions. To implement a true rhombic antenna, eachleg of the antenna must be longer than two wavelengths [34].This poses a problem for on-chip antenna designers: if λ in thematerial is approximately 2.5 mm, we are barely able to fit aleg of length 2λ on the edge of our 5 mm chip, although largerchips could easily be fabricated for more directive passiveantennas.We considered a rhombic antenna along the perimeter of the

chip where each leg length is approximately 4.9 mm (nearly2λ) as shown in Figure 14. The rhombic and loop antennaswere fed with a 60 GHz source and a 50 Ω source impedance.Two primary design parameters of a rhombic antenna in freespace are the angle γ (indicated in Figure 14) and the height


Fig. 14. Top view of a simulated 60 GHz on-chip rhombic antenna. Therhombic angle γ and trace width are indicated. The point where the antennais connected to the 60 GHz source is denoted ”Feed Points”.

above ground. The ground height is analogous to the substratethickness of the chip in our model and can be optimized usingwafer thinning techniques. A third rhombic design parameter,exclusive to small scale antennas such as an on-chip antenna,is trace width (indicated in Figure 14. These three designparameters were varied to ascertain the performance of on-chip rhombic antennas operating at 60 GHz.The first design parameter tested was the rhombic angle,

γ. The substrate thickness was held constant at 750 μm, feedpoints were separated by 3 μm, and trace width was 10 μm.The angle γ, was incremented from 5 ◦ to 45 ◦. Antenna gainat the horizon (φ = 90 ◦, θ = 90 ◦) as well as maximum gainwere observed. The results in Figure 15(a) show that the angleof largest horizon gain is γ = 39 ◦.Using γ = 39 ◦, the substrate thickness was decreased from

750 μm to 50 μm. The results shown in Figure 15(b) demon-strate that horizon gain increases as the substrate thickness isdecreased. An optimal value for horizon gain is observed at110 μm thickness which is λ/23 (λ with respect to εr = 3.9).A thinner substrate allows higher gains and efficiencies sincethe degrading effects of the lossy silicon substrate are reduced.Using both a γ = 39 ◦ rhombic angle, and a 110 μm

substrate thickness, the trace width of the on-chip rhombic wasincreased from 10 μm to 1900 μm. The results are shown inFigure 15(c). The maximum horizon gain occurs with a tracewidth of 1445 μm (about 57%λ) with a gain nearly -3 dBi.The angle of maximum gain begins to shift from the horizonas trace width increases.Generally, free space rhombic antennas are constructed of

electrically thin copper wires, so the thickness of these wiresis not a design parameter. However, repeated tests have shownthat on-chip rhombic antenna performance is enhanced withthicker trace widths. Figure 16 shows a comparison betweena conventional rhombic antenna with thin trace widths anda higher gain rhombic antenna with thicker trace widths. Az-imuth and elevation radiation plots are presented in Figure 16.The rhombic antenna with trace width 200 μm achieves ahorizon gain of -8 dBi while the rhombic with trace width =1445 μm can achieve a greater horizon gain close to 0 dBi.

(a) Gain vs. angle γ. Maximum horizon gain observedat 39 ◦.

(b) Gain vs. substrate thickness. Maximum gain ob-served at 110 μm.

(c) Gain vs. trace width. Maximum horizon gain ob-served at 1445 μm.

Fig. 15. Gain of the 60 GHz on-chip antenna as a function of (a) angle γ, (b)substrate thickness, and (c) trace width. Maximum gain occurred at an angleof 39 ◦, substrate thickness of 110 μm, and trace width of 1445 μm. ”MaxGain” denotes the maximum antenna gain while ”Horizon Gain” denotes thegain at φ =90 ◦, θ =90 ◦).

The rhombic antenna has been optimized with respect tohorizon gains; however, to transfer maximum power to theantenna, the S11 should be minimized at 60 GHz. If amatching network is not available to minimize S11, the widthof the feed points can be adjusted. The rhombic feed widthwas adjusted to 660 μm (26% of λ) to obtain an acceptableimpedance match to the standard 50 Ω source impedance. Thiscaused the S11 to decrease to a flat -13 dB and thus allow mostof the available power to be accepted by the antenna whentransmitting. Additionally, the horizon gain of the antennaslightly increased from -3 dBi to -1.27 dBi with the increasedfeed width. The S11 of -13 dB for the on-chip rhombic antenna


Fig. 16. Comparison of two 60 GHz on-chip rhombic antennas. Increasingtrace widths increases horizon gains, as seen in the radiation plots (φ = 90 ◦, θ= 90 ◦, radial units in dBi). The wide rhombic antenna showed gains increasedby 6-8 dBi when trace widths were increased from 200 μm to 1445 μm.

was flat across the entire 57-64 GHz band which shows widebandwidth.The optimized rhombic antenna with radiation pattern is

shown in Figure 16. Horizon gain was -1.27 dBi and overallmaximum gain was -0.2 dBi. The radiation efficiency was85%, due primarily to a thinned lossy substrate. These gainsoccurred with γ = 39 ◦, 110 μm substrate thickness, 1445 μmtrace width, and a feed width of 660 μm.Although the simulation results are promising for the rhom-

bic, the size of the antenna and the area used by it onthe chip may cause electromagnetic interference with circuitcomponents, thus suggesting several rhombics may best bepackaged as a stand alone passive chip.

F. On-chip loop antenna at 60 GHz

The loop antenna is a simple and versatile antenna type usedextensively in AM radio and military applications. Loop an-tennas can be classified into two categories: electrically small,with circumferences (C) less than one-tenth of a wavelength(C < λ/10), and electrically large, whose circumference isapproximately a free-space wavelength (C ∼ λ) [35], [36].The gain of a loop antenna is directly proportional to its area;the larger the loop, the greater the gain [31], [35]. Smallloop antennas are therefore poor radiators, and are seldomused for transmission in radio communications. They are,however, employed at the receiving station because of theirlower loss resistance, thus exhibiting higher signal-to-noiseratio. We examined the performance of a large square loopantenna on chip, with overall lengths between 2λ and 4λ.Antenna circumferences than these lengths approach rhombicsizes which are discussed in the preceding section.We considered a square loop antenna at an edge of the chip,

where each leg length could vary between 1.25 mm (λ/2) and2.5 mm (λ), as shown in Figure 17. The antenna was fed with a

Fig. 17. Top view of a simulated 60 GHz on-chip square loop antenna.Three design parameters namely, the leg length, the trace width and the feedwidth are indicated.

60 GHz source and a 50 Ω impedance. The design parametersof an on-chip loop antenna include the leg length, the substratethickness, the trace width, and the distance between the feedpoints. These parameters, indicated in Figure 17, were variedin order to obtain the optimal performance of the 60 GHz on-chip loop antenna.The first design parameter examined was the substrate

thickness. Since the maximum gain in the rhombic antennawas observed for a trace width of 1445 μm, we scaled thisdimension by a factor of 4 (ratio of rhombic leg lengths toloop leg lengths = 2λ:λ/2 = 4:1), to obtain a starting valueof the trace width for the loop, equal to 360 μm. The feedwidth was held constant at 3 μm. The substrate thickness wasincremented from 50 μm to 700 μm, and the antenna gainat the horizon as well as the maximum gain were observed,for five different leg lengths between λ/2 and λ. The resultsin Figure 18 show that the maximum gains are obtained forsubstrate thicknesses between 100 μm and 300 μm. Hence, wechose an average value of 200 μm for the substrate thicknessfor further analysis.Using the substrate thickness as 200 μm, trace width was

then varied for different leg lengths. Figure 19 shows thevariation of the maximum and the horizon gain with the tracewidth for a λ leg length loop antenna. While the maximumgain peaks at a trace width of 1 mm, the horizon gain achievesa peak at a trace width of 0.82 mm.Similar experiments were completed for the leg lengths

and the trace widths, with the parameters resulting in theoptimal maximum and horizon gain recorded. We observedthat the maximum gain begins to shift from the horizon asthe trace width increases. Figure 20(a) shows the variationof these optimal trace widths with respect to leg length.This demonstrates a design guideline that can be used whendesigning 60 GHz on-chip loop antennas of a specific length.For example, from the figure, a trace width of 600 μm wouldresult in the maximum horizon gain for a 2 mm (4λ/5)leg length loop antenna. Using the optimal trace widths, themaximum and horizon gain variation with leg length is shownin Figure 20(b). The gains increase with the increasing leglength. This is an expected result as the loop gains are directlyproportional to the loop area [35].


(a) Max. Gain vs substrate thickness for different leg lengths

(b) Horizon Gain vs. substrate thickness for different leglengths

Fig. 18. (a) Max Gain and (b) Horizon Gain variations with substratethickness for 5 different leg lengths between λ/2 and λ. Trace width and feedwidth equal 360 μm and 3 μm respectively. Maximum gains are obtained forsubstrate thicknesses between 100 μm and 300 μm.

Fig. 19. Gain vs trace width for a λ leg length loop antenna. The maximumgain and the horizon gain attain peaks at trace widths equal to 1 mm and0.82 mm, respectively.

Using the optimal loop antenna obtained with dimensions λleg length, 1 mm trace width, and 200 μm substrate thickness,we increased the feed width from 3 μm to 340 μm. Asobserved in rhombic antennas, the antenna gains increasedwith increasing feed widths, as shown in Figure 21. Themaximum gain and the horizon gain equaled -1.2 dBi and-3.4 dBi, respectively, at a feed width of 340 μm. Increasingthe feed widths minimized the S11 at 60 GHz and hence

(a) Trace widths resulting in best maximum and horizon gainvs leg length. A λ/2 leg length loop antenna exhibits bestgains at a trace width of 320 μm.

(b) Maximum and Horizon Gain vs leg length, using the tracewidths given by Figure 20(a). A λ leg length loop exhibits amaximum gain of -3.5 dBi and a horizon gain of -4.1 dBi.

Fig. 20. A useful guideline in terms of (a) optimal trace widths for a specificleg length loop antenna and (b) the respective gains obtained. The λ leg lengthloop antenna exhibits the maximum gain of -3.5 dBi at 1 mm trace width.

Fig. 21. Gain vs feed width for a λ leg length loop antenna. The maximumgain and the horizon gain attain peaks at feed width equal to 340 μm.

ensured better power transfer to the antenna. Figure 22 showsthe variation of the S11 parameter for different feed widths, theminimum being -23 dB for a feed width of 340 μm. Similarto the rhombic antenna, the bandwidth of the on-chip loopantenna is wide and spans the entire 57-64 GHz frequencyband.The optimized loop antenna with radiation pattern is shown

in Figure 23. The overall gain obtained was equal to -1.2dBi, while the horizon gain equal to -3.5 dBi. The radiationefficiency was 77%. The optimal loop antenna results were


Fig. 22. S11 plots for different feed widths for a λ leg length loop antenna.The minimum S11 obtained is equal to -23 dB for a feed width of 340 μm.

Fig. 23. Radiation plot of the optimized on-chip loop antenna (φ = 90◦, θ =90◦ , radial units in dBi)

obtained with 2.5 mm (λ) leg length, 1 mm trace width, 200μm thick substrate, and 340 μm feed width.We also investigated how the performance of the loop

antenna changes as it is moved across the chip. We foundsimilar gain and directivity patterns at the edges, center andthe sides of the chip. This is in contrast to the behaviorof the on-chip Yagi antennas, whose performance varied asthey were moved across the chip. This implies that loops canbe fabricated anywhere on the chip with no degradation inperformance which would be useful for fabricating phasedloop-arrays, when multiple loops with similar performance canbe phased together to achieve a high gain and directivity at thehorizon. Since the area required by a loop antenna is 25% thatrequired by a similar rhombic antenna, loop antennas will havemany useful applications in integrated antenna technology.

IV. FACILITIES FOR ON-CHIP ANTENNA WORK AT THE

UNIVERSITY OF TEXAS AT AUSTIN

The Wireless Networking and Communications Group(WNCG) at The University of Texas has invested approx-imately $1,000,000 to build a state-of-the-art measurementfacility for RF circuitry and on-chip antennas up to 67 GHz(see Figure 24). The facility includes a probe station consistingof several devices for making in-situ measurements on circuitsubstrates, and allows for thorough characterization of VSWR,gain, coupling losses, as well as other characteristics.By using the probe station and vector network analyzer, it

is possible to measure signal strengths transmitted by the in-situ IC antenna which are received by a small conical hornantenna. We can find the minimum far-field distance, R, givenby [37],

Fig. 24. Measurement facilities in the WNCG lab at UT Austin

Fig. 25. Proposed far-field measuring capability.

R =2D2

λ(3)

where D is the largest antenna dimension. With a maximumdimension of 5 mm (constrained by the chip) and a λ of 5 mm,R is only 10 mm. Hence, a large anechoic chamber or openspace is not required for far-field measurements. However, thefar field range of the receiving antenna must also be taken intoaccount when determining the appropriate spacing between thetwo antennas.In order to confirm the simulations discussed above, as well

as future on-chip antenna simulations, we are constructingan automated antenna measurement system that makes useof a rotating conical horn antenna. The system in Figure 25is based on the system described in [38]. In our system,the receiving conical antenna rotates on an axis at a con-stant distance from the probe-fed IC antenna, acquiring fieldmeasurements for one cut of the radiation pattern, wherethe φ (azimuth) angle is fixed, while the θ (elevation) angleis incrementally stepped. This rotation is automated by acomputer-controlled motor that accurately records positiondata while received power is measured. When one rotational“cut” is completed, the base of the rotation is moved asindicated along the plate edge, changing the φ angle andrepeating the θ angle sweep. This system allows us to constructa far field pattern for elevation angles θ = 0 to 80◦, and allazimuth φ angles.It is crucial that all reflective surfaces and other possible

interferers, especially the probe station, be covered with radio-absorbing substance, as in [39]. Pre-test and calibration will


account for losses from cables, probe tips, and other elementsin the measurement system. Deconvolution of radiation fromthe probe tips, measured while feeding dummy loads, willallow additional multipath effects to be removed. Widebandchannel sounding methods may additionally be used here toresolve true patterns.

V. CONCLUSION

We have presented various 60 GHz passive antennas sim-ulated for implementation on an integrated circuit. TypicalCMOS metals, dielectrics, and substrates were used. Antennaswere designed to fit on an IC die size of 5mm x 5mm. Theantennas implemented were the dipole, Yagi, rhombic, andloop antennas. We found key relationships between the dipoleand the Yagi element spacing and found antenna performanceis maximized when the antennas are placed at the edge of thedie. Based on S11, the Yagi antenna resonated best with a0.11λ reflector spacing. When moving from the center of thechip to the right edge, the maximum gains of both the dipoleand Yagi antenna increased by nearly 7 dB. At the corner ofthe chip, the dipole and the 2-element Yagi had maximumgains of -6.7 dBi and -3.5 dBi, respectively.A novel application of the rhombic antenna to IC technol-

ogy was also explored. Here, we found the optimal angle,substrate thickness and trace width for implementing rhombicantennas in CMOS technology. Using these optimal param-eters, simulations showed that it is possible to achieve amaximum antenna gain of -0.2 dBi and horizon gain of -1.27 dBi, the highest reported for any on-chip antenna todate. Similar experiments were performed on a loop antenna,approximately a quarter of the rhombic antenna’s size, yieldinga maximum gain of -1.2 dBi.While our results show higher gains than previously re-

ported, on-chip antennas tend to have very low efficiencies andpose a unique challenge for antenna and chip designers. How-ever, integrating antennas with circuitry will greatly advancecommunications technology by lowering costs and providingunprecedented flexibility for WPAN devices.

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Felix Gutierrez, Jr. (S’ 08) received the B.S.E.E.degree from the University of Texas at Austin in2006 and the M.S. degree in electrical engineeringfrom Texas A&MUniversity in 2008. He is currentlypursuing a Ph.D. degree at the University of Texas atAustin. Mr. Gutierrez is a Baumberger Endowmentscholar, Radio Club of America scholar, GraduateDiversity fellow, and a Cockrell School of Engineer-ing fellow. Mr. Gutierrez is one of five individualsawarded the 2009 Marconi Young Scholar awardby the Marconi Society. Mr. Gutierrez is a member

of the Wireless Networking and Communications Group (WNCG) and hasconducted undergraduate and graduate research in the area of wireless com-munications. His research interests include antenna design, radio frequencyintegrated circuits, communication systems, and an array of other areas hiscuriosity desires.

Shatam Agarwal received the B. Tech degree inelectrical engineering from Indian Institute of Tech-nology Kanpur, in 2004. He is currently workingtowards his M.S. degree in electrical and computerengineering at the University of Texas at Austin. Hisresearch interests include Analog/RF IC design andmillimeter-wave circuit design.

Kristen Parrish (S’ 07) received the B.S. degreein Electrical Engineering (magna cum laude) fromRose-Hulman Institute of Technology (Terre Haute,IN) in 2008. She is currently working toward theM.S. degree at the University of Texas at Austin,where she is supported in part by a fellowshipfrom the Cockrell School of Engineering. Ms. Par-rish has held summer intern positions at RaytheonTechnical Services Company (Indianapolis, IN) andLGS Innovations (Florham Park, NJ). She is cur-rently completing an internship at Texas Instruments

(Dallas, TX). Her research interests include RFIC and packaging design,electromagnetic theory and simulation, and communication systems.

Theodore S. Rappaport is the William and BettyeNowlin Chair in Engineering at the University ofTexas at Austin and is the founding director of theWireless Networking and Communications Group(WNCG) at the university’s Austin campus, a centerhe founded in 2002. Prior to joining UT Austin,he was on the electrical and computer engineeringfaculty of Virginia Tech where he founded one ofthe world’s first university research and teachingcenters dedicated to the wireless communicationsfield. Prof. Rappaport has been a pioneer in the fields

of radio wave propagation and wireless communication system design, andhis work has influenced many international wireless standard bodies. He isone of the world’s most highly cited authors in the wireless field, havingauthored or co-authored over 200 technical papers, 100 US and internationalpatents, and several books. In 2006, Rappaport was elected to serve on theBoard of Governors of the IEEE Communications Society (ComSoc), and waselected to the Board of Governors of the IEEE Vehicular Technology Society(VTS) in 2008. In 1999, his pioneering work on site-specific RF propagationand system design received the IEEE Communications Society Stephen O.Rice Prize Paper Award. In 1989, he founded TSR Technologies, Inc., acellular radio/PCS software radio manufacturer that he sold in 1993 to whatis now CommScope, Inc (NYSE: CTV). In 1995, he founded Wireless ValleyCommunications Inc., a site-specific wireless network design and managementfirm that he sold in 2005 to Motorola, Inc. (NYSE: MOT). Rappaport hastestified before the US Congress, has served as an international consultantfor the ITU, has consulted for over 30 major telecommunications firms, andworks on many national committees pertaining to communications researchand technology policy. He is a highly sought-after consultant and technicalexpert. When he is not working or teaching, he enjoys singing, marathontraining, amateur radio (N9NB), and traveling. He received B.S., M.S., andPh.D. degrees in electrical engineering from Purdue University in 1982, 1984,and 1987, respectively.

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