IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 5, MAY ...kentesar/Kamran_J16.pdf · A. Basic Idea: Qualitative Analysis ThebasiccelloftheproposedLNA isthecompositeNMOS/ PMOS transistors

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 5, MAY 2011 1111

An Inductor-Less Noise-Cancelling BroadbandLow Noise Amplifier With Composite Transistor Pair

in 90 nm CMOS TechnologyMohamed El-Nozahi, Member, IEEE, Ahmed A. Helmy, Student Member, IEEE,Edgar Sánchez-Sinencio, Fellow, IEEE, and Kamran Entesari, Member, IEEE

Abstract—A new broadband low-noise amplifier (LNA) is pro-posed in this paper. The LNA utilizes a composite NMOS/PMOScross-coupled transistor pair to increase the amplification whilereducing the noise figure. The introduced approach provides par-tial cancellation of noise generated by the input transistors, hence,lowering the overall noise figure. Theory, simulation and measure-ment results are shown in the paper. An implemented prototypeusing IBM 90 nm CMOS technology is evaluated using on-waferprobing and packaging. Measurements show a conversion gain of21 dB across 2–2300MHz frequency range, an IIP3 of 1.5 dBm at100 MHz, and minimum and maximum noise figure of 1.4 dB and1.7 dB from 100 MHz to 2.3 GHz for the on-wafer prototype. TheLNA consumes 18 mW from 1.8 V supply and occupies an area of0.06 mm .

Index Terms—Composite transistor pair, low noise amplifier,noise cancelation, wideband.

I. INTRODUCTION

T ODAY, the advances in semiconductor technology guidethe progress in the wireless communications circuits

and systems area. Various new communication standards havebeen developed to accommodate a variety of applications atdifferent frequency bands, such as digital video broadcastingat 450–850 MHz, FM transceivers at 87–108 MHz, satellitecommunications at 950–2150 MHz, global positioning system(GPS) at 1.2 GHz, and cellular radios at 850–1900 MHz.The modern wireless industry is now motivated by the globaltrend of developing multi-band/multi-standard terminals forlow-cost and multifunction transceivers [1]–[3]. Stackingseveral front-ends for the reception of various standards wasone of the design trends to realize these wideband receivers[1]–[3]. Today, the design trend is now focused on using singlewideband front-ends in order to accommodate all the standardsusing a single front-end as well as reduce the chip area. Single

Manuscript received September 01, 2010; revised January 16, 2011; acceptedJanuary 21, 2011. Date of publication April 05, 2011; date of current versionApril 22, 2011.This paper was approved by Guest Editor Yuhua Cheng.M. El-Nozahi was with the Department of Electrical and Computer Engi-

neering, Texas A&M University, College Station, TX 77843 USA. He is nowwith Vidatronic Inc., College Station, TX 77840USA (e-mail: [email protected]).A. A. Helmy, E. Sánchez-Sinencio, and K. Entesari are with the Department

of Electrical and Computer Engineering, Texas A&M University, College Sta-tion, TX 77843 USA (e-mail: [email protected]; [email protected];[email protected]).Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/JSSC.2011.2118310

wideband front-ends face many challenging problems includingvery low noise figure, high linearity requirements, and low areaconsumption.Wideband low-noise amplifiers (LNAs) are key building

blocks in wideband front-ends. Inductor-less topologies havebeen proposed to reduce the area consumption [4]–[14]. TheseLNAs usually rely on resistive feedback techniques for wide-band input matching, which leads to poor noise figure, andhence, poor sensitivity. In addition, due to the flicker noise, theyare not suitable for sub-100-MHz communications. Therefore,noise cancellation techniques have been proposed in the liter-ature to overcome the poor noise figure of these inductor-lesswideband LNAs [4], [7]. These techniques depend on thematching between the devices to be able to achieve the requirednoise figure reduction. The best reported noise figure using thisapproach is 1.9 dB [4]. Reducing the noise figure below 1.9 dBis still challenging and a solution is provided in this paper.The proposed broadband LNA in this paper achieves a low

noise figure by utilizing a composite NMOS/PMOS transistorpair connected in a cross-coupled configuration to provide par-tial noise cancellation of the main transistors [15]. The pro-posed solution does not rely on the matching between the de-vices making the new architecture more tolerant to process vari-ation. The paper is organized as follows. In Section II, the con-ventional wideband LNA with resistive matching is discussed.Section III presents the basic idea of the proposed widebandLNA. Also, analytical expressions for the performance param-eters are derived. Section IV discusses the actual circuit imple-mentation, the optimum sizing of the proposed LNA, and com-parison to the conventional LNAs. Section VI demonstrates themeasured and simulated results for on-wafer and packaged pro-totypes. Finally, Section VII concludes the paper.

II. BACKGROUND

Fig. 1 presents the conventional broadband LNA with resis-tive shunt feedback matching. For this architecture, the differ-ential input resistance, , and differential voltage gain,

, are given as follows:

(1)

(2)

where is the transconductance of the transistor. consists of the load resistance

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1112 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 5, MAY 2011

Fig. 1. Conventional broadband LNA with resistive matching.

and the output resistance of the transistor . Considering thethermal noise of the input transistor, and , and assumingthe LNA is designed with perfect matching ,the noise figure is calculated from [14]

(3)The parameter is the transistor thermal noise factor. The

first term in (3) is due to the thermal noise of the transistor,while the second and third ones are due to and , respec-tively. For this LNA, the noise figure is mainly determined bythe noise contribution of the MOS transistor. To design for alower , the value of has to increase through eitherincreasing the transistor aspect ratio or current consumption. In-creasing the aspect ratio increases the input/output capacitanceand therefore limits the wideband operation. This limitation isshown later in the paper through schematic-level simulations.On the other hand, increasing the current increases the powerconsumption of the LNA. Typically, the minimum isaround 1.8 dB.The main reason for the high noise figure can be explained

qualitatively using Fig. 2. In this figure, the noise due to theNMOS transistor at the right section of the circuit is considered.The left section is replaced with its equivalent input resistance,

. As shown, the noise current generates an output voltage,. Then, produces a voltage at node , which is then

amplified by the left section with an opposite polarity. The exactanalysis shows that , and therefore the total outputnoise doubles, leading to a higher noise figure. To overcome thisproblem, a new architecture is proposed to avoid doubling theoutput noise voltage, and as a result reduces the lower limit ofthe noise figure than the one defined by (3).

III. PROPOSED WIDEBAND LNA

Fig. 3 shows the simplified schematic of the proposed broad-band LNA architecture. This architecture is similar to the con-ventional broadband LNAwith resistive matching, however, theoverall noise figure is reduced by incorporating the transistor

and connecting the gate of to the gate of in across-coupled fashion. As shown below, this composite config-uration of the NMOS and PMOS transistors reduces the output

Fig. 2. Equivalent circuit model showing the effect of noise current of forthe conventional LNA.

Fig. 3. (a) Simplified schematic of the proposed LNA architecture, and (b) half-circuit model.

noise of the two transistors and results in a lower output noise.The input matching is adjusted through the feedback resistance

and the effective transconductance of the overall LNA.

A. Basic Idea: Qualitative Analysis

The basic cell of the proposed LNA is the composite NMOS/PMOS transistors configuration shown in Fig. 4. In this config-uration, the NMOS and PMOS transistors appear in series, andthe inputs are assumed to be and . Ideally, if the two inputshave the same amplitude and phase, then the source voltage ofthe two transistors, , is the same as the input leading to a zerooutput current. On the other hand, if the two inputs have thesame amplitude but differ in phase, then is an AC groundresulting in a finite output current. Hence, this configurationamplifies the differential voltage and rejects the common-modeone. Due to series configuration of the two transistors, shown inFig. 4, the effective transconductance, , is given by the

EL-NOZAHI et al.: AN INDUCTOR-LESS NOISE-CANCELLING BROADBAND LNA WITH COMPOSITE TRANSISTOR PAIR IN 90 nm CMOS TECHNOLOGY 1113

Fig. 4. Composite NMOS/PMOS transistor architecture.

series combination of the NMOS and PMOS transistors. As aresult, the output current is given by

(4)

(5)

where and are the transconductance of theNMOS and PMOS transistors, respectively. The compositeNMOS/PMOS transistor is used as the basic cell to reducethe overall noise figure of the LNA shown in Fig. 3(a). Theamplification of the input signal is demonstrated by consid-ering the half-circuit model shown in Fig. 3(b). In this model,input signals to gates of and carry different polarity

leading to an amplification of the input signal. Incase both inputs have the same polarity , the outputAC current is zero, leading to common-mode noise rejection.Considering the noise generated by the NMOS and PMOS

transistors, the cross connection leads to partial noise cancel-lation of the generated noise. The partial noise cancellationis clarified qualitatively for the proposed architectures, asshown in Fig. 5. In this figure, the noise current due to theright NMOS transistor, , is considered. The left section isreplaced by its input impedance, which is analytically derivedusing the small signal model in Fig. 6. The outcome of thisanalysis shows that for noise analysis the left section could bereplaced with an input impedance of (seethe Appendix). represents the source impedance, whichappears in series with . The noise currentproduces an output noise voltage, . Then, generates anoise voltage at nodes and . These two voltages drive theleft section and produce an output noise voltage, , which isa fraction of ( , ). Due to the cross con-nection, carries the same polarity as , and thereby thedifferential output noise voltage and noise figure are reduced.Similarly the noise generated by is partially canceled. Inthe conventional case, and carry different polarities,and therefore the conventional LNA with resistive feedbackhas higher noise figure.

B. Performance Parameters

In this subsection, analytical expressions for the inputimpedance, voltage gain, and noise figure of the proposed LNAare demonstrated.1) Input/Output Transfer Function: The transfer function of

the proposed LNA in Fig. 3(a) is calculated using the half-cir-cuit small-signal model shown in Fig. 7. In this model,and are the gate-source capacitance of the NMOS/PMOS

Fig. 5. Equivalent circuit model showing the effect of noise current of forthe proposed LNA.

transistors, while and are the output and source para-sitic capacitances as shown in the figure, respectively. Also, theeffect of output conductance of transistors and is ne-glected for simplicity.Small-signal analysis results in a differential transfer function

as follows:

(6)

where is the mid-band gain, is the pole at the output,and and are due to the parasitic capacitances ,

, and . In case and , thesource voltage of and is AC ground, and henceand cancel out each other and are not effective. This is alsoconcluded from (6), when . However, in case

, the zero location appears at the lower frequency comparedto the non-dominate pole location. Because and appearafter the dominate pole, the gain expression effectively has asingle pole as demonstrated in (6). The above analysis is verifiedusing circuit-level simulation. The results for both the simula-tion and the analytically evaluated expression in (6) are shownin Fig. 8. In this simulation, the current through is steeredto avoid increasing the supply voltage. In the actual implemen-tation, the load resistance is replaced with a PMOS transistorin a push-pull architecture to provide higher gain. Fig. 8 showsthat the output pole determines the 3-dB upper cut-off frequency


Fig. 6. Equivalent small-signal model to find the input impedance of the left section for noise analysis. (a) Actual model. (b) Reduced mode using .

Fig. 7. Half-circuit small-signal model of the proposed LNA.

Fig. 8. Schematic-level simulated frequency response of the proposed LNAversus the analytical expression in (6) ( mS, mS,

, , fF, fF, fF,fF).

( dB, G rad/s). In addition, the effectof and does not appear up to 5 GHz. Simulations showtheir effect starts to appear after 20 GHz in this example.The approximated gain expression in (6) is similar to the gain

expression of the conventional LNA with resistive feedbackgiven by (2), and therefore it has the same gain properties. Inaddition, the output pole for both the proposed and the conven-tional LNA is similar with the assumption of having the same. Increasing the gain requires a higher value of ,

which reduces the upper cut-off frequency of the LNA. This isan indicative of the design trade-offs between gain and band-width that is also seen in conventional amplifier.

2) Input Impedance: Using the small-signal model in Fig. 7,the half-circuit input impedance of the proposed LNA is analyt-ically given by

(7)

where is the gain of the LNA defined in (6) consideringthe dominant pole , and is the gate-drain capacitanceof NMOS transistor. The input impedance is composed of threeparallel impedances as follows: 1)which is responsible for the input matching; 2)

which is due to the finite input capacitance; and3)which appears due to non-equal values of and . For

, the source voltage of NMOS/PMOS transistorsis a virtual AC-ground, and the input impedance is clearly theparallel combination of the first two terms in (7). However inthe actual design, it is hard to guarantee similar andbecause of the design or process mismatches, and thereforethe third term in (7) is effective. In this design, andare assumed to be equal, and therefore the third term can beremoved as an approximation.The above analysis is verified using circuit-level simula-

tions and the results are shown in Fig. 9. In this plot, thehalf-circuit input impedance is normalized to for boththe schematic-level simulated and analytically-evaluated re-sults. The results indicate that initially the input impedance ismatched to the source resistance . Then around 1 GHz theinput impedance starts to increase because of the gain reduc-tion. At 3 GHz, , and start to be effective andthus the input impedance is reduced.The differential input impedance, ,

could be further simplified in terms of poles and zeros using(7) as follows:

(8)


Fig. 9. Schematic-level simulation of the half-circuit input impedance nor-malized to of the proposed LNA versus the analytical expression in (7)( mS, mS, , , fF,

fF, fF, fF, fF).

where

(9)

Eq. (9) demonstrates that the mid-band value of the inputimpedance, depends on the value of and theratio of similar to the conventional LNA defined in(1). Changing either of these quantities helps to improve thematching, i.e., . As an example, to reduce thevalue of either the value of has to increaseor the value has to decrease. Increasing leadsto a lower noise figure, however, the input capacitance in-creases leading to a poor matching at higher frequencies, i.e.,lower bandwidth. On the other hand, reducing the value of

lowers the gain and hence increases the noise figure.This is the trade-off between increasing the bandwidth of theinput impedance versus having a lower noise figure at higherfrequencies.3) Noise Figure: The different noise sources affecting the

overall noise figure of the LNA are shown in Fig. 10, whereonly the noise contributors of half of the circuit is shown. Theeffect of the parasitic capacitances will be ignored to simplifythe analysis and because noise figure is important in the mid-band of operation. Assuming and , theresultant output differential noise voltage due to ,is given by

(10)

where is the noise current due to both thermal and flickernoise. The first term is the transimpedance gain for the noisecurrent generated by . The doubling is due to the fact thatthere are two of each device, one on each half-circuit. Assumingperfect matching, (10) reduces to

(11)

Fig. 10. Noise sources in the proposed LNA.

The input-referred voltage noise due to is obtained bydividing (11) by defined in (6)

(12)

The noise current of is due to its thermal and flicker noisevoltage. This current is given by

(13)

where is the Boltzmann constant, and are the thermaland flicker noise factors, respectively, is the DC current,

is the oxide capacitance per unit area, and is the channellength of . Substituting (13) in (12), the input-referred noisevoltage is as follows:

(14)

Similar analysis is applied to the remaining noise contributorsof the circuit. The input-referred voltage noise due to ishence given by

(15)

The input-referred voltages noise due to the thermalnoise of and , and

are as follows:

(16)

(17)


Fig. 11. Schematic-level simulation of the noise figure of the proposed LNAversus the analytical expression in (7) ( mS, mS,

, , fF, fF, fF,fF, fF, , , ,

).

Finally, the total noise figure is obtained by summing thequantities of (14), (15), (16), and (17) and then dividing by

. is the noise generated by the source re-sistance at the input of the LNA. Hence, the total noise figure,

is as follows:

(18)

The above analysis shows that the noise contribution of theNMOS/PMOS transistor is reduced compared to the conven-tional LNA in (3), while the noise contribution of the feedbackand load resistances remains the same. Assumingand for simplicity, the noise contribution (thermal andflicker) of the NMOS/PMOS transistors is reduced by one-halfcompared to the conventional architecture. A similar conclusionis also reached for the flicker noise. As a result, the lower limitof the noise figure of the low noise amplifier with resistive feed-back is reduced using the proposed approach. It is important tomention that this architecture requires higher supply voltage.Fig. 11 shows the simulated and the analytically-evaluated

noise figure of the proposed LNA. At low frequencies, the noisefigure increases because of the flicker noise. At higher frequen-cies, the noise figure starts to increase again because of the fi-nite bandwidth of the LNA, which increases the noise contri-bution of the feedback resistance. The effect of parasitics wasnot included in deriving (18), and therefore, the analytical ex-pression does not follow the simulated schematic-level resultsaround and above the cut-off frequency. Simulations also showthat the noise contribution at higher frequencies (around 1 GHz)is mainly thermal noise due to the NMOS/PMOS transistorsand resistances. Schematic-level noise analysis indicates thatthe noise contribution of the NMOS/PMOS transistors is almostthe same as the feedback and load resistances. This result pointsout that the noise contribution of the transistors is reduced suchthat they are not the main noise contributors. In this example,the minimum value of is 1.7 dB. However, in the actualcircuit implementation, the noise figure is further reduced byusing a push-pull architecture.

IV. CIRCUIT IMPLEMENTATION

A. Circuit Description

Fig. 12(a) shows the actual implementation of the proposedLNA. In this implementation, the load, , is replaced by aPMOS transistor, forming a push-pull architecture. Thistransistor serves two main purposes: 1) to provide the DC cur-rent biasing, and 2) to provide an additional gain to increase theoverall gain and reduce the noise figure of the LNA. The DCbiasing is adjusted with the current source , which is mir-rored through the current mirror . This current also deter-mines the gate-source voltages of and , and thereforeno additional DC biasing circuit is required. The DC voltage ofthe output node is determined from the gate-source voltages of

and , i.e. .The gate of is biased to ground through the resistance ,which is much higher than the value of the source resistance, .Transistor also provides an additional transconductance

to increase the overall gain of the LNA. Increasing the overallgain helps to reduce the noise contribution of the load andfeedback resistances, and therefore lowering the overall noisefigure. With the additional transistor, the voltage gain,input impedance, and noise figure are modified as follows:

(19)

(20)

(21)

where is the transconductance of . It is importantto mention that adding another composite transistor as the loadhelps in reducing the NF more, however it requires a highersupply voltage.The capacitors and are added to isolate the DC bi-

asing of each gate of the transistors. These capacitors and theresistors and limit the lower cut-off frequency of theamplifier. The lower cut-off frequency can be estimated by ex-pressing the output current at the lower frequencies as follows:( and )

(22)


Fig. 12. Complete schematic of (a) the proposed broadband LNA demonstrating the biasing circuit, and (b) the buffer V .

TABLE ICIRCUIT ELEMENT VALUES AND TRANSISTOR ASPECT RATIOS FOR THE

IMPLEMENTED LNA AND BUFFER

Finally, the lower cut-off frequency can be analytically calcu-lated using (22) to find the 3-dB cut-off frequency. The resultant3-dB lower cut-off frequency is

(23)

In this implementation, the lower cut-off frequency is ad-justed around 2 MHz. Widths of the transistors are increased byusing maximum number of fingers to reduce the required cur-rent to achieve a specific . The upper value for widths ofthe transistors is limited by the required upper cut-off frequencyaround 2.4 GHz. In addition, increasing the transistor widthhelps to reduce the flicker noise and required headroom. On theother hand, width per finger is minimized to reduce the effectiveseries gate resistance resulting in higher gain and lower noisefigure. A buffer is designed to drive the 50 load impedance.Fig. 12(b) shows the schematic of the buffer. Table I shows thecircuit element values and transistor aspect ratios for the pro-posed LNA and buffer.

B. Sizing the Composite Transistor

The composite NMOS/PMOS transistors are sized in a wayto maximize the bandwidth. In this subsection, a design method-ology is presented to find the optimum width of the NMOS andPMOS transistor. The input capacitance of the LNA is propor-tional to the gate-source capacitance and hence the width and

length of the input devices. The input capacitance is writtenas

(24)

where , and are the channel width andlength of the NMOS and PMOS transistors, respectively. isthe oxide capacitance per unit area. Eq. (24) indicated that theinput capacitance depends on . Reducing this quantitymaximizes the bandwidth of the amplifier. The value of the re-quired effective transconductance determines both values. Theinverse of the transconductance for long and short channel de-vice approximation is given by

long channel

short channel

(25)

where is the velocity saturation constant. Eqs. (24) and (25)are used along with a constrained optimization algorithm to findthe optimum value of and . This optimization problemis defined as follows:

(26)

The constrained optimization in (26) is solved analyticallyusing Lagrange multipliers, resulting in the following designrequirement for the ratio :

long channel

short channel.(27)


Fig. 13. Input capacitance normalized to its minimum value versus formS.

Fig. 13 shows the input capacitance normalized to its min-imum value versus a sweep of for a constantmS using (24). As depicted, there is an optimum value for

both and to minimize the input capacitance. In thisdesign, the optimum value of is around 59mS. In the actualimplementation, and are designed for 50 mS each,which reduces the input bandwidth by 4%.

C. Comparison With Conventional LNA

In this subsection, a comparison of the proposed LNA withthe conventional one is demonstrated through schematic-levelsimulations. In both topologies, the push-pull architecture isemployed. In addition, the biasing current is fixed to 10 mA(5 mA in each half circuit). Fig. 14 shows the simulated min-imum noise figure versus the value of and for theproposed and conventional LNA, respectively. As depicted, forthe same transconductance the proposed LNA achieves a lowernoise figure compared to the conventional one. There is a dif-ference of 0.3 to 0.5 dB in the noise figure. For example, with atransconductance of 55 mS the proposed LNA achieves a min-imum noise figure of 1.3 dB versus 1.65 dB for the conventionalcase.Increasing the transconductance of the conventional LNA

helps to reduce its minimum noise figure. However, the min-imum is limited to 1.52 dB for the same current consumptionof 10 mA. This is because increasing the transconductancerequires the increase of the width of the input device, whichincreases the input capacitance, and hence reduces the band-width. This is clarified through schematic-level simulation ofthe bandwidth versus the transconductance value in Fig. 14.For the same transconductance, both amplifiers have the samebandwidth because the bandwidth is limited by the output polein this example. However, to design for the same noise figureand current consumption, the transconductance of the con-ventional architecture has to be higher than the proposed one,leading to a lower bandwidth. As a result, the proposed LNAprovides the minimum noise figure for the same bandwidth. Inaddition, its lower limit for the noise figure is lower than theconventional one, making it suitable for designing a broadbandLNA with sub-1.5-dB of minimum noise figure.

Fig. 14. Minimum NF (top) and bandwidth (bottom) versus the transconduc-tance value of proposed and conventional LNAs mA/half-circuit .

Fig. 15. Die photo of the proposed LNA.

The linearity of the proposed LNA is slightly lower than theconventional one. This is due to the higher supply voltage re-quirement. Also, the proposed LNA does not have an inherentnonlinearity cancellation similar to the noise. Schematic-levelsimulations show that for a gain of 20 dB, the conventional ar-chitecture achieves an IIP3 of 0.5 dBm, while the proposed oneachieves an IIP3 of 1 dBm. Increasing the linearity requiresincreasing the supply voltage, which results in higher powerconsumption.

V. SIMULATION AND EXPERIMENTAL RESULTS

The broadband LNA is fabricated using 90 nm CMOStechnology provided by IBM. The die micrograph is shown inFig. 15, where the area of the LNA core is mm . Twomeasurement setups are used for estimating the performance ofthe LNA. The first setup uses on-wafer probing. In this setup,the input and output signals are applied using a G-S-G-S-Gdifferential probe, and the DC signals are applied using an 8-pinDC-probe. This measurement setup is used to extract the perfor-mance of the LNA without the effect of external components.


Fig. 16. Measured and simulated and voltage gains for the on-waferprototype.

Fig. 17. Measured and voltage gain for the packaged prototype.

It provides a comparison with the existing reported broadbandLNAs that use on-wafer probing in their measurements. In thesecond measurement setup, the LNA is encapsulated in a microleadframe (MLP) package, where the input/output signals areapplied/monitored using an FR-4 printed circuit board (PCB).In the case of MLP package, the RF and DC signals are appliedfrom a PCB-board. This measurement setup is used to evaluatethe performance of the LNA including the PCB traces andpackaging effect.Figs. 16 and 17 show themeasured and simulated for both

measurement setups. In the case of the on-wafer measurement,is lower than 10 dB up to 1.6 GHz, while it reduces to

1.1 GHz in the case of the packaged model. The reduction inthe bandwidth in the packaged model is due to the increase ofinput capacitance because of the PCB traces. Better design ofthe PCB could lead to better performance.The measured and simulated voltage gains after de-embed-

ding the buffer effect are also shown in Figs. 16 and 17. Amid-band gain of 21 and 20 dB is measured for the on-waferand packaged LNAs, respectively. The 1 dB difference in themid-band gain is due to the extra losses introduced by the tracesat the output of LNA. The lower cut-off frequency is 2 MHz,while the upper cut-off frequency is 2.3 GHz and 1.1 GHz forthe on-wafer and packaged LNAs, respectively. The differencein the upper cut-off frequency is due to the extra capacitanceat the input and output of the packaged prototype. The differ-ence in the lower cut-off frequency could be due to the lower

Fig. 18. Measured and reverse isolation for the on-wafer prototype.

Fig. 19. Measured and reverse isolation for the packaged prototype.

Fig. 20. Measured and simulated noise figures versus the operating frequencyfor the on-wafer prototype.

cut-off frequency of the balun used in the measurement. Thebuffer drives the 50 impedance of network analyzer. A mea-sured better than 13 dB across the band of interest is ob-tained as shown in Figs. 18 and 19. The measured reverse iso-lation, , is lower than 30 dB for both cases.The measured and simulated noise figures versus the op-

erating frequency for the on-wafer prototype are shown inFig. 20. The excess noise due to the buffer is de-embeddedfrom measurements by measuring its output noise when theLNA is switched off. This excess noise is then subtracted fromthe total output noise of LNA+buffer. The noise figure of theLNA reaches a minimum value of 1.4 dB. Around 1.6 GHz,


Fig. 21. Measured noise figure versus the operating frequency for the packagedprototype.

Fig. 22. Measured versus the operating frequency for the on-waferprototype.

the noise figure starts to increase, reaching a maximum valueof 1.7 dB at 2.3 GHz, which is the upper cut-off frequency ofthe proposed LNA. At 100 MHz, the noise figure is 1.75 dB.For the packaged prototype, the noise figure also reaches aminimum value at 900 MHz. Below this frequency, the noisefigure increases because of the flicker noise reaching 1.9 dBat 100 MHz. Above 900 MHz, the noise increases because ofthe bandwidth of the LNA which is limited by the packageparasitics. These measurements show that the proposed LNAachieves an almost constant noise figure from 100 MHz upto its upper cut-off frequency. This property does not exist inmany existing broadband LNAs, which achieve a minimumnoise figure at a specific frequency and have a much highernoise figure across the entire frequency range.A two-tone IIP3 measurement is performed for the LNA and

the results are shown in Fig. 22 and Fig. 23 for the on-wafer andpackaged prototypes, respectively. The two tones are appliedwith the same amplitude and a frequency offset of 1 MHz. Ameasured IIP3 higher than 1.5 dBm is obtained for both theprototypes.The LNA, excluding the output buffer, consumes 10 mA

from 1.8 V supply. The performance of the proposed LNA andcomparison with existing state-of-the-art inductor-less broad-band LNAs around the same frequency range are summarizedin Table II. As shown in the table, the proposed broadbandLNA with composite NMOS/PMOS transistors provides the

Fig. 23. Measured versus the operating frequency for the packagedprototype.

minimum noise figure, and has less variations across 100MHz to the upper cut-off frequency when compared to thestate-of-the-art architectures.

VI. CONCLUSION

A broadband LNA employing a new noise-cancelling tech-nique is proposed in this paper. The LNA relies on a com-posite NMOS/PMOS transistor pair for implementing the noisecancellation. The theory shows that the proposed approach re-duces the lower limit of the conventional LNA with resistivefeedback, allowing for a noise figure below 1.5 dB. Also, op-timum sizing of the composite transistors was demonstrated inthe paper. On-wafer measurements of a fabricated prototypeusing 90 nm CMOS technology show a voltage gain of 21 dBwith a 3-dB bandwidth of 2.3 GHz. A minimum noise figure of1.4 dB and an IIP3 of 1.5 dBm are also measured. The mea-sured noise figure is lower than the best reported noise figureby 0.5 dB. In addition, measurements of a packaged prototypewere also presented. The LNA consumes 18 mW from a 1.8 Vsupply.

APPENDIX

In this appendix, the input impedance, , in Fig. 6(b), isderived for the noise analysis. Using KVL:

(28)

Assuming perfect matching and using (9), (28) is simplifiedto

(29)

Hence, the input impedance for the noise analysis is given by

(30)

The above expression points out that the equivalent inputimpedance is the source impedance between nodes and, and a series resistance of to ground.


TABLE IIPERFORMANCE SUMMARY OF THE PROPOSED BROADBAND LNA AND COMPARISON WITH THE EXISTING WORK

Estimated from data provided in the corresponding papers.power gain.

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Mohamed El-Nozahi (S’00–M’10) received theB.Sc. and M.Sc. degrees, both in electrical engi-neering, from Ain Shams University, Cairo, Egypt,in 2000 and 2004, respectively. He received thePh.D. degree from Texas A&M University in 2010.From 2000 to 2004, he was a Teaching and Re-

search Assistant with the Electronics and Communi-cations Engineering Department, Ain Shams Univer-sity. In Summer 2007, he was a Design Intern withTexas Instruments, Dallas, TX. In Summer 2009, hewas a Design Intern with Qualcomm, San Diego, CA.

From 2010 to 2011, he was withMarvell Semiconductor, Santa Clara, CA. Since2011, he has been with Vidatronic Inc., College Station, TX. His research inter-ests include transceivers system and circuit design at millimeter-wave frequen-cies and power management ICs.Dr. El-Nozahi was the recipient of the 2009 Semiconductor Research Corpo-

ration (SRC) Design Challenge Award and the TI Excellence Fellowship from2006–2009.


Ahmed A. Helmy (S’09) was born in Cairo, Egypt,in 1983. He received the B.Sc. degree (with honors)and the M.Sc. degree in electronics engineering fromCairo University, Giza, Egypt, in 2005 and 2008,respectively. He is currently working toward thePh.D. degree in electrical and computer engineeringat Texas A&M University, College Station, TX.From 2005 to 2008, he was a Research Assistant

with the Yousef Jameel Science and TechnologyResearch Center, The American University, Cairo,Egypt. From 2005 to 2008, he was a teaching

assistant with the Electronics and Communications Engineering Department,Cairo University. His research interests include RFIC design, CMOS sensors,and MEMS systems.

Edgar Sánchez-Sinencio (F’92) was born inMexico City, Mexico. He received the degree incommunications and electronic engineering (Pro-fessional degree) from the National PolytechnicInstitute of Mexico, Mexico City, the M.S.E.E.degree from Stanford University, Stanford, CA, andthe Ph.D. degree from the University of Illinoisat Urbana-Champaign, in 1966, 1970, and 1973,respectively.His research work has more than 2650 citations ac-

cording to the Thomson Reuters Scientific CitationIndex. He has graduated 42 M.Sc. and 34 Ph.D. students. He is a coauthor of sixbooks on different topics including RF circuits, low-voltage low-power analogcircuits, and neural networks. He is currently the TI J. Kilby Chair Professor andDirector of the Analog and Mixed-Signal Center at Texas A&MUniversity. Hispresent interests are in the areas of power management, RF communication cir-cuits, and analog and medical electronics circuit design.

Dr. Sánchez-Sinencio is a former Editor-in-Chief of IEEE TRANSACTIONS ONCIRCUITS AND SYSTEMS II. In November 1995 he was awarded a Honoris CausaDoctorate by the National Institute for Astrophysics, Optics and Electronics,Mexico. This degree was the first honorary degree awarded for microelectroniccircuit-design contributions. He is a co-recipient of the 1995 Guillemin-CauerAward for his work on cellular networks. He was also the co-recipient of the1997 Darlington Award for his work on high-frequency filters. He received theIEEE Circuits and Systems Society Golden Jubilee Medal in 1999. He alsoreceived the prestigious IEEE Circuits and Systems Society 2008 TechnicalAchievement Award. He was the IEEE Circuits and Systems Society’s Rep-resentative to the IEEE Solid-State Circuits Society during 2000–2002. He wasa member of the IEEE Solid-State Circuits Society Fellow Award Committeefrom 2002 to 2004. He is a former IEEE CAS Vice President-Publications. Hiswebsite is: http://amesp02.tamu.edu/sanchez.

Kamran Entesari (S’03–M’06) received the B.S.degree in electrical engineering from Sharif Uni-versity of Technology, Tehran, Iran, in 1995, theM.S. degree in electrical engineering from TehranPolytechnic University, Tehran, Iran, in 1999, andthe Ph.D. degree from the University of Michigan,Ann Arbor, in 2005.In 2006, he joined the Department of Electrical

and Computer Engineering at Texas A&M Univer-sity where he is currently an Assistant Professor.His research interests include design of radio-fre-

quency/microwave/millimeter-wave integrated circuits and systems, RFMEMS, related front-end analog electronic circuits, and medical electronics.Dr. Entesari was the corecipient of the 2009 Semiconductor Research Corpo-

ration (SRC) Design Contest Second Project Award for his work on dual-bandmillimeter-wave receivers on silicon. He is the recipient of the 2011 NationalScience Foundation (NSF) CAREER Award.

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 5, MAY ...kentesar/Kamran_J16.pdf · A. Basic Idea: Qualitative Analysis ThebasiccelloftheproposedLNA isthecompositeNMOS/ PMOS transistors