Design of Low-Voltage Low-Power Multiphase Switched-Current Sinusoidal Oscillators

X. D. Jia and R. M. M. Chen

School of Creative Media City University of Hong Kong

Tat Chee Avenue, Kowloon, Hong Kong,China Email: xdjia@ee.cityu.edu.hk

Abstract

Circuit design and siniiilatiorz of low-porrvr low- voltcrge tiiultiphase switched-current siniisoidal oscillators are presented in this paper. In order- to achieve /orr,-pon’er lobv-vdtcige atid high erccurcicj, S‘I nieniot?. cell, balariced strircture. level shijter; GGA arid class A B techniques crre employed in our designs. All our designs have beeri validated by trmsistor level SPICE sitnulatioris.

I. Introduction

Over the years, the interest towards low-power low-voltage IC has consistently grown. This is primarily due to the increasing importance of portable equipment in all market segments like, for instance, telecommunications, computers, and consumers[ I ] .

The switched-current (SI) technique[2-41 is a relatively new analogue sampled-data signal processing technique that fully exploits digital CMOS tcchnology. Its applications to filtering, A/D and D/A converting have been studied extensively since 1989[2-4,7-1 I]. But its applications to the design of other nonlinear circuits like oscillators[5,6] have not yet attracted as much attention as switched-current filters. AID and D/A converters.

In this paper circuit design and simulation of low- power low-voltage multiphase switched-current sinusoidal oscillators are presented. These oscillators can be implemented in low-voltage low-power mixed signal VLSI circuits and hence have a wide range of practical applications in communications, signal processing and power electronics.

11. The Generalized Schemes

Multiphase oscillators have a wide range of practical applications in communications, signal processing and power electronics. Figures I and 2 give the generalized schemes to realize multiphase switched-current oscillators (SIOS). Figure I is for odd integer N and Figure 2 is for even integer N . The basic building blocks are the inverting (or non- inverting) SI dumped bilinear intcgrators.

After loop gain analysis. the conditions of oscillations and the frequencies of oscillations can be derived. Results of the derivations for N = 3.4,..6 are given in Table I .

Thus. thc oscillation frequency f, i b determined by the clock frequency f, and coefficients A and B which represent the transistor scaling factors in SI circuits. Sensitivity analysis shows that these oscillators enjoy low sensitivities.

111. Low-Power Low-Voltage SI Integrator Using S31 Cell and Balanced Structure

The basic building blocks in our designs are the inverting (or non-inverting) SI damped bilinear integrators. The performances of S I 0 circuits based on second generation current memory ce11[3,5,6] are affected by the non-ideal behaviour of MOS transistors. These non-ideal behaviours of’ MOS transistors will cause errors in S I 0 circuits, which include charge injection errors, mismatch errors, drain conductance errors. setting errors and noise errors[4,6]. Crucial to the success of SI0 circuits is the precision of its building blocks.

The two-step sampling process (S’I) was introduced to reduce all types of errors [7]. S’1 memory cell is an elegant and simple SI memory cell. But i t still has three problems: finite output switch on- resistance, drain-gate feedback capacitance and anomalous settling behaviour resulting from drain- substrate capacitance[8, IO]. To overcome these problems, an enhanced S’I was proposed[8]. While this has been shown to work effectively, i t is at the cost of complexity and performance.

Our designs are based on a newly developed high-speed low-distortion SI memory cell, called S31 (the seamless S’I cell)[lOj. This cell operates on the same two-step principle of the early S‘I but produces a virtual earth input voltage on both coarse and fine sampling phases. In order to operate on low voltage, some techniques introduced in[ 1 I ] are employed i n

our design. Moreover a balanced circuit configuration

0-7803-6253-5/00/$10.00 02000 IEEE. 52 1

is used in our design to achieve the highest level of analog performance.

Figure 3 shows the low-voltage S31 bilinear damped integrator used in our multiphase oscillator design.

In the integrator shown in Figure 3, all the switches, whose gate connecting to VDD, are the compensating resistors proposed in[& IO]. Since the level shifter and GGA (grounded gate amplifier) introduced in [ l l ] are employed in the circuit, our integrator can work in low-voltage range ( 1 3 -3 V).

Even through lowering the voltage of power supply can reduce the power consumption dramatically, there are still rooms for further improvement of the power consumption by using Class AB[4,9,12,13] and other techniques. Class AB techniques allow the signal magnitude to exceed that of the bias current and therefor offer a potential approach to realise power efficient SI circuits. Class AB techniques described in[4] are employed in our multiphase S I 0 designs.

IV. Design Examples and Simulation Results

As the design examples, a three-phase SI0 and a five-phase SI0 have been implemented. The condition of the oscillation and frequency of the oscillation of the three-phase SI0 are

The sensitivities off,, to the clock frequency f, and coefficient B for a three-phase SI0 are

and -

for

The condition of the oscillation and frequency of the oscillation of the five-phase SI0 as well as its sensitivity analysis are also completed. They are not given in this paper due to page limitation.

The performances of three-phase S I 0 and five- phase SI0 have been validated by transistor level SPICE simulations. Figure 4 shows the output waveform of the three-phase S I 0 with k,=O. 1 16, kb=

0.1 and VDD=2.5 V. The SPICE simulations demonstrate that the proposed SI0 can work properly under the low supply voltage ( 1 . W -3V). Figure 5 shows the output waveform of the five-phase S I 0 with k,= 0.125, kb= 0.2 and VDD=2.5 v .

V. Conclusions

Low-power low-voltage multiphase SI0 designs are presented in this paper. Until now, while there are numerous papers on multiphase oscillator, few of these use SI technique. In order to achieve low-power low-voltage and high accuracy, S'I memory cell, balanced structure, level shifter, GGA and class AB techniques are employed in our designs.

Also a three-phase SI0 and five-phase SI0 are given as design examples. These SIOs have been validated by transistor level SPICE simulations. Using other newly developed techniques[ 12,131 to further reduce the supply voltage, say below 1.5 V, and improve the power efficiency is undergoing and will be reported in later publications.

Key references

I . R Castello, F Montecchi, F Rezzi, and A B asc hiro tto, "Low-Vol tage Analog Filters," IEEE Trans. Circuit and System-I: Fundamental Theory and Applications, Vol. 42, No. 11, Nov. 1995, ~ ~ 8 2 7 - 8 4 0 .

2. J. B. Hughes, N. C. Bird, L. C. Macbeth, "Switched Currents- a new technique for analog sampled-data signal processing," in IEEE ISCAS'89 Proceedings, pp 1584- 1587, May 1989.

3. J. B. Hughes, I. C. Macbeth, and D. M. Pattullo, "Second generation switched-current signal processing," in ISCASPO Proceedings, pp.2805- 2808, May 1990. .

4. C. Toumazou, J. B. Hughes and N. C. Battersby, Switched-currents-- an analogue technique for ,

digital technology, IEE Peter Peregrinus Ltd. 1993.

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5. X. D. Jia and R . M. M. Chen, “A Novel Switched- Current SinuSoidal Oscillator,” International journal of Circuit and Applications, Vol. 26, ~ ~ 3 0 1 - 3 0 5 , 1998.

6. X. D. Jia, Switched-Current Oscillator Circuit design and Simulation, and associated Parallel Processing Techniques, Ph.D Thesis, Dept. of E. E., City University of Hong Kong, 1998.

7. J . B. Hughes and K. W. Moulding, ”S21: A Switched-Currcnt Technique for High Performance,” Electr. Lett., Vo129, pp. 1400- 1401, 1993.

8. J. B. Hughes and K. W. Moulding, “Enhanced S21 Switched-Current Cells,” in Proc. ISCAS’96, pI- 187-191, 1996.

9. R. J. van de Plassche, W. M. C. Sansen and J. H. Huijsing, Analog Circuit Design-Low-Power

Low-Voltage, Integrated Filters and Smart Power, Kluwer Academic Publishers, 1995.

10.B. Hughes and K. W. Moulding, ”S’I: The Seamless S21 Switched-Current Cell,” In Proc. ISCAS’97 pp.113-116, June 1997.

11 . Simek and V. Musill, “LOW-Voltage S21 and S’I Cells for Sigma-delta Signal Processing,” In Proc. ISCAS’98, May 1998.

12.A Worapisher, J B Hughes, and C Toumazou, “ Class AB Technique for High Performance Switched-Current Memory Cells,” In Proc. ISCAS’99, May 1999.

13. C H Lin and M Ismail, ‘‘ Design and Analysis of An Ultra Low-Voltage CMOS Class-AB V-I Converter for Dynamic Range Enhancement,” In Proc. ISCAS’99, May 1999.

-A- -A- -A- _._ -A- 1 - Bz-’ 1 - Bz-I

Figure 1 Basic scheme for odd-phase SIOs

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Figure 3 Circuit configuration of low-voltage S"I balanced billinear damped integrator, k I

, Ulld s =- . where ,,- I + 4, 1 + kh

- i<"'rU1> . ,L",-> 4 - &<".->

. - ~ . . ......... ~ ... .... " I 1 ! ... !... . ... I . . . . . . . . . ! ............... .: ..... ../ . ..~. ~ ........

i ..*! .. ... t ....... ...I ... I.. .... . . . . .! ..... c .......... j I.- L.Y. L.6- XI.* ..- *.- ..U

L'" P

Figure 4. Output waveforms of the three-phase S I 0 with k,=O. I 1, kb=O. 1 and VDD=3V

Figure 5. Output waveforms of the five-phase SI0 with k,=O. 125, kb=0.2 and VDD=2.5V

Table I Conditions and frequencies of oscillation of multiphase SIOs.

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