NEW DESIGNS OF 14-TRANSISTOR PPM ADDER

Rizwan Mudassir, H. El-Razouk, Z. Abid and Wei Wang Department of Electrical and Computer Engineering

University of Western Ontario London, Ontario, Canada, N6G 5B9

email: rmudassi@uwo.ca; helrazou@uwo.ca; zeabid@eng.uwo.ca; wwang@eng.uwo.ca.

Abstract

In this paper, we propose improved designs of full adders, known as Plus-Plus-Minus (PPM) adders, for Redundant Binary (RB) number systems applications. The proposed two PPM adder designs use 14 transistors and are derived from new algorithms. They achieve reduction in the time delay, power consumption, and chip area, compared to currently available designs. Furthermore, the proposed 14-transistor adders have been used to build two efficient designs of on-line radix-2 redundant multipliers. All the proposed designs have been implemented using 0.18µm CMOS technology. The implementation results show that the proposed PPM adders have significant reduction in both power consumption and time delay compared to the 24-transistor PPM adder.

Keywords: PPM adder; redundant binary system; on-line multiplier; low power adder.

1. Introduction

Fast and low power operation of a digital system is greatly influenced by the performance of the adders [3]. Hence, improving the performance of the Plus-Plus-Minus (PPM) adders would greatly advance the execution of binary operations inside a circuit. In this paper, two efficient designs of PPM adders, for redundant number system applications, are proposed. The Redundant Binary (RB) number system differs from conventional binary number system in that the individual digit of RB number can be represented by three values {1, 0, -1}. In arithmetic operations, the use of this signed digit format allows each bit of the result to be obtained in parallel without carry propagation. PPM adder is used as the basic building block in RB system to handle the signed digit operations. Thus, improving its performance is critical for enhancing the overall performance of RB-based DSP systems. There are a variety of PPM adders in the literature, both at the gate level and transistor level [1] [2] [4]. A previously proposed PPM adder design [1] uses 24 transistors based on a CMOS structure. This 24-transistor design is shown in Fig. 1 (20 transistors were shown in Fig. 1 of [1] while two more inverters are required). Since the performance of an adder would affect the digital system (as in multipliers and dividers), a PPM adder should be designed targeting the

maximum reduction of power consumption, time delay and chip area. Therefore reducing the number of transistors, in a PPM Adder, to a minimum without compromising the performance of the adder is the main goal of this work.In this paper, we propose new designs of a 14-transistor PPM adder, based on sharing and balanced methods which were derived from new algorithms. The proposed adders achieve reduction in the number of transistors compared to the designs in [1] [2] [4]. Furthermore, the proposed 14-transistor adders have been used to build two designs of on-line radix-2 redundant multipliers. All the designs proposed in this paper have been implemented using 0.18µm CMOS technology. The implementation results show that all the new designs have superior performance (reduction in the time delay and power consumption) compared to previously proposed design. The organization of the paper is as follows: in section II, a brief overview and design aspects of PPM adders are given. Section III presents two 14-transistor PPM adders based on sharing and balanced methods and derived from a new algorithm. Section IV discusses the results along with a comparison with the previous PPM adder design. Section V presents two designs of the hybrid radix-2 redundant multipliers that incorporate the proposed PPM adders, the simulation results have been discussed in this section. Section VI concludes the paper.

2. PPM Adders

A radix-2 redundant signed-digit number system is based on a digit set S= {1, 0, -1}, where each digit can assume any of the three values from the set S and thus, redundancy is introduced in the number system. Such representation is very advantageous while designing high speed systems, since it allows “carry-free” addition [2-5]. A PPM adder (Figure 2) performs the addition of a redundant number x(where, −+ −= xxx ) to an unsigned binary number y,resulting in another redundant number expressed by an interim sum u- and a transfer digit t+. The input bits are defined as }1,0{,, ∈−+ yxx and the output bits are

, {0,1}t u+ − ∈ .The PPM Adder performs the following operation:

2x y x x y t u+ − + −+ = − + = − (1)

0-7803-8886-0/05/$20.00 ©2005 IEEECCECE/CCGEI, Saskatoon, May 2005

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Figure 1: A previous PPM adder design [1], where A, B, and C inputs correspond to x+, y, and x-

+x −x y

−u +t

Figure 2: PPM adder

In redundant binary signed digit number system, the signed-digit operation is taken care of by the PPM adder. Hence, PPM adders constitute an important component in any redundant signed digit arithmetic, since there is no need for an explicit mechanism to handle signed digit number. The most important feature of redundant signed-digit number system is that it allows carry free addition. This eliminates the carry-propagation which is the main cause of time-delay in an n-bit adder, thereby resulting in a fast operation. In redundant binary signed digit system, three possible digits {1, 0, -1} can be encoded using two bits.

Hence, each signed digit is represented as, −−+= xxx ,where +x and −x ∈ to {0, 1} and x∈ to {1, 0, -1} (see Table 1).

Table 1: Encoding of radix-2 redundant number system.

x x+ x - x ≡ x+ x -0 0 0 00-1 0 1 011 1 0 100 1 1 11

3. Proposed new 14-T PPM adders

Here, we propose two novel to designs of efficient 14-transistor PPM adder, where set-1 is based on sharing method and set-2 is derived from a new algorithm where

both output bits are generated simultaneously (balanced method). The proposed two designs are implemented using pass transistor logic and transmission gates and uses only 14 transistors. The proposed two designs have a full swing output voltages of the output signals u- and t+, thus the noise margins of these new designs are optimum. Based on the above equation (1), the sharing method can be derived as following.

yxxyxxu )()( −+−+− ⊕+⊕=

By denoting )( −+ ⊕= xxz and −+ ⊕= xxz , we have

u y z yz− = + (2a)

Similarly we have, )()( −+−−+++ ⊕+⊕= xxuxxxt

zuzx −+ += (2b) Notice that the part of the circuit used to generate u- is also used for t+ (shared method). The balanced method is derived from the following equations.

zyzyxxyxxyu +=⊕+⊕= −+−+− )()( (3a)

zyzxxxyxxxt +=⊕+⊕= +−+−+++ )()( (3b) Based on equations (2a), (2b) and (3a), (3b), three modules are used to implement the two sets of PPM adders as shown below:

PPM Adder modules

Module-1 consists of six transistors and generates the XOR and XNOR logic signals of z and z [6]. Module-2 consists of the four transistors. It is required to generate the interim sum (u-) using the signals z , z and y. This module uses the transmission gate implementation of the XNOR gate with no ground or power supply rails, thus eliminating the short circuit and leakage currents. Module-3 consists of two transmission gates and is required to generate the transfer digit (t+), given the control signals z , z , IN and x+. Set-1 of PPM adder (Fig.3) uses u- as their IN signal in Module-3 and set-2 (Fig. 4) uses y as IN signal. Module-3 uses 4 transistors and provides full output voltage swing. This module behaves as a multiplexer passing either x+ or IN depending on the control signals z and z .The (set 2) PPM adder is an improvement relative to (set 1) PPM adder, with the feature of a balanced generation of the output signals u- and t+. This leads to the simultaneous generation of the signals u- and t+ and lower time delay. Further improvement of the 14-T (set 2) adder is a 16-T

PPM

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PPM adder shown in figure 5. All internal and external nodes of the 16-T adder have full voltage swing in contrast to one internal node ( z ), in the 14-T adders, suffering from one threshold voltage loss. This feature is more critical in 0.13µm and subsequent CMOS technologies where the gap between the voltage supply and the threshold voltage is being reduced.

Figure 3 :( Set 1) 14-T PPM adder

Figure 4: (Set 2) 14-T PPM adder

Figure 5: 16-T PPM adder

4. Simulation Results of PPM Adders

The power dissipation and the time delay of the proposed PPM adders are computed when implemented in 0.18µm CMOS technology. All the values indicated in the Table 2 have been obtained at 125MHz under a load of 10fF. The width of N-MOS transistors is 0.5 um while the width of P-MOS is 0.8 um. In most designs today, the primary tradeoff is between power and delay and therefore the Energy Delay Product (EDP) has been used for benchmarking the performance of these circuits. The longest critical path delay values are considered for each adder which covers all 56 transitions [6]. The measured values for the time delay, average power dissipation and Energy Delay Product (EDP) are presented in Table 2. It is evident that lower values for EDP indicate better performance. The proposed 14-T PPM adders show lower power dissipation and a shorter time delay. The measured values of time delay of the new 14-T PPM Adder (Set 2) outperforms all the existing PPM adder designs with a noticeable improvement, since the transfer digit t+ is generated independently from the digit u-. The first proposed PPM adder (set-1) has 36% less power consumption and 13% lower time delay compared to the 24-transistor PPM adder [1]. The second proposed PPM adder (set-2) has also 32% less power consumption and 34% lower time delay compared to 24-T PPM adder. Therefore, the proposed designs are very attractive for the area-efficient and low-power high speed applications. The 16-T PPM adder performance is close to that of set-2 adder, its power dissipation and time delay are slightly higher (by about 10%).

Table 2: Simulation results of PPM adders

Adder type Power (µW)

Delay (ns)

EDP 2410−×(J-s)

24T-PPM [1] 23.12 0.518 06.20 Set-1 PPM 14.70 0.449 02.96 Set-2 PPM 15.79 0.343 01.86

5. On-line multipliers and implementation

The proposed PPM adders are used to build two on-line multipliers. The architecture of the hybrid radix-2 redundant (on-line) multipliers, [2] is shown in fig (6) and (7). The multiplicand b is a radix-2 redundant number while the multiplier a is a two’s complement number. Allthe full adders (FA) in both multiplier architectures have been implemented using pass transistor logic and transmission gates with a total of 16 transistors [6].

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Figure 6: Hybrid radix-2 redundant multiplier architecture-1 [2]

Figure 7: Hybrid radix-2 redundant multiplier architecture-2 [2]

The analysis has been carried out by performing simulation runs on Cadence environment with 0.18µm technology, and the results indicate a significant improvement in terms of power consumption and speed in addition to a reduction in the chip-area as a result of the use of the proposed 14 transistors PPM adder designs compared to the previously described 24 transistor PPM designs [1]. Tables 3 and 4 shows the simulation results for both architectures of hybrid radix-2 redundant multipliers, which incorporate the proposed 14-T PPM adder designs. The focus is on comparing the performances of the two architectures of on-line multipliers when using various PPM adder designs. For the calculation of the power consumption, only the multiplier section consisting of Full adders (FA), PPM adders and the Latches (D) was considered, since the goal of this work is to asses the performance of the proposed PPM adders. For the simulation of the time delay, the complete system has been taken into account.

Table 3: Simulation results for Architecture-1

Architecture-1[2]

Delay (ns)

Power (µW)

EDP x10-24

(J-s) 24-T PPM 0.514 67.96 17.9

Set-1 0.403 58.24 9.4 Set-2 0.365 57.72 7.6

Table 4: Simulation results for Architecture-2

Architecture-2[2]

Delay (ns)

Power (µW)

EDP x10-24

(J-s) 24-T PPM 0.509 93.8 24.3

Set-1 0.387 89.32 13.3 Set-2 0.275 91.45 6.9

6. Conclusion

In this paper, new PPM adder designs are proposed based on a sharing and balanced format derived from the PPM addition equation. In the proposed PPM adder, the number of transistors was reduced, while improving the performance, and without compromising the full swing of the output signals. The proposed adder has been implemented using CMOS 0.18µm technology. The implementation results have shown that the proposed 14 transistors designs have lower power consumption and higher speed while requiring fewer transistors compared to the previously published PPM adders. The proposed 14 transistors PPM adders are used to build two hybrid radix-2 on-line redundant multipliers. A significant reduction in power consumption, time delay, and area has been achieved in this multiplier implementation. These full adders can also be used as efficient building blocks for the VLSI implementation of many digital signal processing operations, image and video processing and microprocessors.

Reference

[1] A. Guyot, Y. Herreros and J. Muller, “JANUS, an on-line multiplier/divider for manipulating large numbers,” in Proceedings of 9th Symposium on Computer Arithmetic, pp. 106-111, 1989.

[2] K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation. New York: John Wiley & Sons, Inc., 1999.

[3] B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs, Oxford: Oxford University Press, 2000.

[4] A. Avizienis, “Signed digit number representation for fast parallel arithmetic,” IRE Transactions on Electronic Computers, vol. EC-10, pp. 389-400, Sept. 1961.

[5] H.R.Srinivas, et al., “High-speed VLSI arithmetic processor architectures using hybrid number representation,” Journal of VLSI signal processing,vol. 4, pp.177-198, April 1992.

[6] Ahmed M. Shams et al., “Performance Analysis of Low-Power 1-bit CMOS full Adder cells,” IEEE Trans. On VLSI systems, vol.10. No.1 Feb, 2002.

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