Automatic Design of Binary and Multiple-Valued Logic Gates on RTD Series∗

Krzysztof S. BerezowskiInstitute of Engineering CyberneticsWrocław University of Technologykrzysztof.berezowski@pwr.wroc.pl

Sarma B. K. VrudhulaNSF Center for Low Power Electronics

ECE Dept. University of Arizonasarma@ece.arizona.edu

Abstract

In this paper, we contribute to the binary and multiple-valued applications of resonant tunneling devices (RTDs).We propose a method of systematic design of physical pa-rameters of RTD based logic. From the abstraction of theirbehavior, we model the design space as a handful of systemsof linear inequalities generated for a given circuit topol-ogy and an arbitrary logic function. Any valid solution re-flects the physical parameters assignment that implementsthe function given. We solve these systems using off-the-shelf optimization tool and verify the results using SystemCbased RTD circuit model. Our simulations confirm, that thenumerical solutions are valid parameter assignments.

1. Introduction

The sustained growth of computing demands has beenlong-term fed by the development of the design and manu-facturing technologies. The device feature downscaling hasprovided an exponential growth in the volume of integratedlogic and made the integrated MOSFET transistor one ofthe cheapest creation of mankind. Nevertheless, MOSFETbased digital circuits are going to hit the scaling wall sooneror later. Beyond that, quantum mechanics will drive the be-havior of semiconductor structures, and the nanoscale quan-tum effect based devices are going to be the next relay.

Resonant tunneling diodes (RTD) have emerged asa promising technology for nanometer scale digital logic∗ This work was carried out at the National Science Foundation’sState/Industry/University Cooperative Research Centers’ (NSF-S/IUCRC) Center for Low Power Electronics (CLPE). CLPE issupported by the NSF (Grant #EEC-9523338), the State of Ari-zona, and an industrial consortium.Any opinions, findings, and conclusions or recommendations ex-pressed in this material are those of the author(s) and do not nec-essarily reflect the views of the National Science Foundation.Numerical experiments was performed in Wrocław Centre for Net-working and Supercomputing, Wrocław, POLAND.

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.50

0.5

1

1.5

2

2.5

3

3.5x 10

−4

V

I(V

)

← Ip = 0.28mA

← Ip = 0.23mA

← Iv = 30uAI

v = 26uA →

PDR1 NDR PDR

2

Vp

Vv

Figure 1. The examples of RTD I – V curveswith simple piece-wise linear approximations

[4]. They enjoy a handful of properties attractive for dig-ital logic [3]: (i) compact design, (ii) picosecond switchingtimes, (iii) inherent noise immunity, and (iv) capability ofrobust multiple-valued operation. Finally, RTDs are one ofa few nanotechnologies mature enough to be manufacturedin high volume [3] and integrated with CMOS [1, 2].

The physics of RTD allows for feasible and robustmultiple-valued logic (MVL) design [9]. In fact, RTDs havebeen applied in many MVL applications: basic gates [2, 9],memory cells [7], adders [5], and other [3]. Unfortunately,vast multidimensional parameter space of an RTD circuitmakes MVL design rather art than engineering. Althoughsome design methods exist [9], they are more guidelinesthan algorithms. In this work we address the problem andcontribute to the systematic design of the RTD-MVL logic.

2. Resonant Tunneling Devices

RTD is a sandwich-like structure [6] composed from fewlayers of small bandgap semiconductor (like GaAs) sepa-rated by two layers of high bandgap one (like AlGaAs). Thestructure enjoys the quantum electron tunneling through thedouble barrier at the resonant energy levels. The I − Vcurve of the device is non-monotonic, and exhibits the res-onance peak (Vp, Ip), as well as the corresponding valley(Vv, Iv). The device unveils two positive differential resis-tance regions: PDR1 ([0, Vp]) and PDR2 (V ≥ Vv); and the

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0 0.2 0.4 0.6 0.8 10

1

2

3

x 10−4

V

I(V

)

• ← LOW MEDIUM → • HIGH → •

0 0.1 0.2 0.3 0.4 0.50

0.5

1

1.5

2

2.5

3

3.5x 10

−4

V

I(V

)

• ← monostable

multistable (high)→ •• ← multistable (low)

Vbias

D1

D2

M1

M2

M4 D3

D4

M3

Y

B

A

A B

Y

Vbias

D1

D2M2M1

Y

BA

Figure 2. LEFT: A MOBILE circuit and its operation: monostable (red), and bistable (green). RIGHT:A MML circuit and its multistable operation. Stable operating points marked with bullets

negative differential resistance (NDR) ([Vp, Vv]) (Fig. 1).The connection of RTD and HBT, HEMT, MODFET, or

MOSFET transistor is usually referred to as resonant tun-neling transistor (RTT) [2, 3, 9]. The parallel connection isa bit more convenient as the resulting curve is a superposi-tion of RTD and transistor curves. Obviously, RTT curve iscontrollable by the gate voltage: roughly, when it increasesthe curve moves up toward higher current values [8].

The building block of an RTD binary logic is a bistablepair (Fig. 2). It enjoys two stable operating points deter-mining either low or high voltage at output Y [3]. Thisbehavior can be used to provide binary operation. The well-known operating principle is monostable to bistable transi-tion logic elements (MOBILE) [9] — a clocked RTD logicstyle. It is governed by the clocked supply voltage Vbias os-cillating from low VbiasL to high VbiasH value. The Vbias

range is designed (by preselecting VbiasL and VbiasH ) tomove the circuit from the monostable to the bistable state.

In the monostable phase the circuit is put into the ini-tial state. During the cycle, on the rising slope of Vbias,the circuit moves from the monostable to the bistable state.This can be graphically illustrated by sweeping the the loadcurve over the driver curve from VbiasL to VbiasH value.The operating point follows the curve with lower peak asthis device limits the current flow through the branch. Thusthe operating point moves from the PDR1 of this deviceto its PDR2, increasing the device resistance (the deviceswitches “off”). The other device stays in its PDR1 (i.e.low-resistance “on” state) throughout the cycle [9]. Sincethe elevation of the I − V curve is controlled by the gatevoltages, the relative positions of the of the peaks dependon the input voltages — so does the output node.

On the top of the Vbias slope, the node Y stabilizes atone of the bistable states according to the rule: if Ipload

<Ipdriver

, the output node stays low (load switches “off”,driver stays “on”), otherwise it goes high (load stays “on”,driver switches “off”). Once evaluated, the output is decou-pled from the input till the end of the cycle (latched up),

and exhibits strong noise immunity i.e. the circuit robustlytolerates disturbances of the Vbias voltage [2, 3].

The series of m RTDs, that differ in parameters, forms asingle m-peaked device [9]. By using it as a load and as adriver we obtain up to m + 1 stable operating points (Fig.2). Such a circuit, working under the oscillating supply volt-age, is called monostable to multistable logic (MML) and itsoperation is based on two properties [9]:

1. On the rising edge of Vbias, RTDs switch sequentiallyfrom “on” to “off”. The switching sequence followsthe increasing order of their peaks.

2. VbiasH has to be designed such that exactly k out outof 2n − 2 RTDs are able to switch “off” during thetransition. Thus the voltage of an output node dependson exactly which devices from the series went “off”.

Example: For the 3-valued logic (3VL) 4-RTD seriesfrom the Fig. 2 we assume, that the VbiasH has been de-signed to allow only two RTDs to switch off. Thus, depend-ing on physical parameters and input voltages, the switchingdevices can be [9]: (i) d1 and d2 driving the node Y low be-cause of low driver resistance and high load resistance, (ii)d1 or d2 and d3 or d4 driving the node Y medium becauseof the approximately equal load and driver resistances, or(iii) d3 and d4 driving the node Y high because of low loadresistance and high driver resistance.

3. The Design Method

The logic function of an RTD series is determined by itstopology and the device parameters [4]. Using different se-tups one topology can implement different gates. E.g. thetwo-input MOBILE circuit from the Fig. 2 is able to im-plement AND and OR functions. Compared to MOBILE,design space of MML circuit increases. The “capacity” ofits topology increases as well. This observation allows toformulate the following problem: given MVL function, RTTcircuit, and the bounds on the parameter ranges, find a validdevice parameter configuration to implement the function.

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Let us briefly discuss our approach on the MOBILE bi-nary circuit (Fig. 2). For every input combination the peakpositions are determined by: (i) the RTD peaks, and (ii) thetransistors drain currents. Assuming, the transistors work insaturation, we abstract circuit configuration by the quadru-ple 〈Ip1 , Ip2 , ∆p1 , ∆p2〉 where Ipi are the peaks, and ∆pi

are the drain current differences between neightbouring in-put logic values i.e. discretized transistor contributions tothe RTD peaks. We assume, without loss of generality,that there is no current flowing through the transistor forthe logic ‘0’ input. To simplify the discussion let us fix∆p = ∆p1 = ∆p2 i.e. the transistors are identical.

The following inequalities describes the series behavior:

Y ={

0 : Ip1 < Ip2(A, B)1 : Ip1 > Ip2(A, B) (1)

where Ip1 is the peak of the load, and Ip2(A, B) is the peakof the driver RTT, respectively. From the Kirchoff’s currentlaw, the RTT curves are superpositions. So the peak of thedriver can be denoted as Ip2(A, B) = Ip2 +∆p × (A+B).That allows us to formulate an inequality related to eachentry in the truth table of the function. All such inequalitiesform a linear system, i.e. for an OR gate we have:

Ip1 − Ip2 < 0, A + B = 0Ip1 − Ip2 − ∆p < 0, A + B = 1

−Ip1 + Ip2 + 2∆p < 0, A + B = 2(2)

The solution to that system is a valid parameter assignmentfor a MOBILE OR gate. E.g. the vector [Ip1 , Ip2 , ∆p]T =1mA·[0.28, 0.23, 0.25]T satisfies the system and guarantiescircuit manufacturability [10].

By analogy, we build the description of the MVLgate. We discuss the technique on the 3VL gate of Fig.2. On the top of MML principle, we additionally assumethat exactly two out of four devices switch during theMML transition. Let us now denote RTD peaks by thequadruple 〈Ip1 , Ip2 , Ip3 , Ip4〉 : Ipi ∈ Z+. Let us alsodenote the transistors contributions by the quadruple offunctions 〈∆p1(x1), ∆p2(x2), ∆p3(x3), ∆p4 (x4)〉 wherexi ∈ {‘0’, ‘1’, ‘2’} is the transistor input in logic domain.We reasonably assume, that the voltages (thus the currents)representing logic values are evenly distributed. Now wecan define the ∆pi(xi) functions as:

∆pi(xi) =

0, xi = ‘0’∆pi , xi = ‘1’2∆pi , xi = ‘2’

(3)

where ∆pi ∈ Z+ denotes an unitary contribution to thedevice peak current. As a result, in an RTT implementedas a parallel connection of an RTD and a transistor, Ipi

encapsulates the constant, and ∆pi the variable, componentof the peak. Now denote the peak of every RTT in the MVLcircuit (Fig. 2) as a function of its logic inputs:

Ii(xi) = Ipi + ∆pi(xi), i ∈ [1, 2]Ii(x3, x4) = Ipi + ∆p3(x3) + ∆p4(x4), i ∈ [3, 4] (4)

Our objective is to find the Ipi and ∆pi values such thatthe circuit satisfies given truth table. On the assumptionsundertaken, we guarantee stable series operation iff at leastthree peaks are in strictly increasing order for every inputcombination. Based on this observation, we write down theset of inequalities that governs the 3VL operation of the cir-cuit. From now on, while referring to I1, . . . , I4 we meanthe functions I1(x1), . . . , I4(x3, x4). We omit the parame-ters to avoid breaking inequalities into multiple lines:

• high (‘2’) output of the series:{I3 �= I4

max {I3, I4} < min {I1, I2} (5)

• medium (‘1’) output of the series:{I1 �= I3

max {I1, I3} < min {I2, I4} (6)

or

{I2 �= I3

max {I2, I3} < min {I1, I4} (7)

or

{I1 �= I4

max {I1, I4} < min {I2, I3} (8)

or

{I2 �= I4

max {I2, I4} < min {I1, I3} (9)

• low (‘0’) output of the series:{I1 �= I2

max {I1, I2} < min {I3, I4} (10)

For 3VL gate being designed, its parameters must hold (5)for ‘2’; (10) for ‘0’; and at least one of (6) – (9) for ‘1’output. It assures proper logic operation of the series.

Unlike MOBILE, MML series are described by non-linear inequalities. However, they are piece-wise linear,and this property can be used to convert them into twoalternative sets of linear systems following the pattern:{

A �= Bmax {A, B} < min {C, D} (11)

into their piecewise linear replacement:

A − B < 0B − C < 0B − D < 0

or

B − A < 0A − C < 0A − D < 0

(12)

Converting the inequalities for each input vector, we gener-ate a set of systems of 9 · 3 = 27 inequalities. Any solutionto any of the systems constitutes a function implementation.Unfortunately, the number of linear systems may vary from29 to 227 what makes the brute force approach quite costly.

Finding a solution to the system of strict inequalities isa problem. Clasical linear optimization techniques solvethe non strict systems. Fortunately, the shape of the convex(hyper-)polyhedron defined by each system is quite charac-teristic and it allows to find the solution in simple geometri-cal manner. Let us note, that plane defined by each inequal-ity (12) goes through [0, . . . , 0] point. Thus, if the polyhe-dron is non empty, it can be either the unbounded from the

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Table 1. Examples of three-valued gate definitions used and the computed parameter assignments

f1(A,B) 0 1 2

0 0 0 01 0 0 02 0 0 0

f2(A,B) 0 1 2

0 2 2 21 2 2 22 2 2 2

f3(A,B) 0 1 2

0 2 1 01 1 0 02 0 0 0

f4(A,B) 0 1 2

0 2 1 11 1 1 02 1 0 0

f5(A, B) 0 1 2

0 2 2 11 2 1 02 1 0 0

Function Id1 ∆d1 Id2 ∆d2 Id3 ∆d3 Id4 ∆d4

f1(A, B) 0.3750 0.2091 0.8112 0.6000 0.8475 0.6000 0.8837 0.8000f2(A, B) 0.8112 0.6000 0.7750 0.6000 0.3387 0.2000 0.3025 0.2000f3(A, B) 0.4159 0.2067 0.8475 0.4933 0.3755 0.3720 0.3936 0.7974f4(A, B) 0.8085 0.2816 0.8279 0.5528 0.2336 0.5591 0.5313 0.5713f5(A, B) 0.7669 0.4541 0.7362 0.5063 0.2361 0.4879 0.2361 0.5185

bottom (hyper-)pyramid or the open space bounded from itsone side by a half-open pyramid-like shape. For manufac-turability, we limit the design space by the (hyper-)cuboidof feasible parameters ranges — as lower and upper bounds— thus assuring the polyhedron is either empty or bounded.

We implement the geometric procedure of finding theinterior point of the polyhedron from its vertices computedby linear programming solver. By sequentially solving(both minimizing and maximizing) the set of objectives:

f(Ip1 , . . . , Ip4 , ∆p1 , . . .∆p4) = Ip2 + Ip3 + . . . + ∆p4

f(Ip1 , . . . , Ip4 , ∆p1 , . . .∆p4) = Ip1 + Ip3 + . . . + ∆p4

...f(Ip1 , . . . , Ip4 , ∆p1 , . . .∆p4) = Ip1 + Ip2 + . . . + ∆p3

we find the “top” and “bottom” points. Having all thesepoints, we compute the average over each coordinate. Theresulting point, is the interior point if the polyhedron is notempty. To check for emptiness we test, if the strict systemholds for the computed point. If it does, the solution is valid.

We implemented the exaustive search and evaluated ourmethod experimentally. We ran experiments for a set of3VL trivial and nontrivial gates. We got plenty of valid re-sults: the samples are shown in Table 1. We validated themby both SystemC-based MML simulations and analog Mat-lab simulations. The run times on a PIV based cluster variedfrom minutes to hours per gate (depending on its definition).Although, the implementation requires many improvementsthat we are working on, it suffices to prove our formulation.

4. Conclusion

In this work, we gave a systematic solution to the designproblem of binary and MVL logic on series of RTDs. Undera couple of reasonable assumptions we modeled the prob-lem as a handful of constrained optimization problems andshowed, that the solutions exist and that they are feasible.Thus the physical implementations exist as well. Furtherwork includes, formulation and solving of the discrete prob-lem in order to better fit the application domain as well asthe examination of the design space mathematical structure

in order to improve the search algorithms. Nevertheless, thefoundation for the approach has been proposed and demon-strated to be both correct and producing feasible results.

References

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[2] L. Ding and P. Mazumder. Noise-tolerant quantum MOScircuits using resonant tunneling devices. IEEE Trans. Nan-otech., 3(1):134–146, Mar. 2004.

[3] P. Mazumder, S. Kulkarni, M. Bhattacharya, J. P. Sun, andG. I. Haddad. Digital circuit applications of resonant tunnel-ing devices. Proc. IEEE, 86:664–686, Apr. 1998.

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[7] T. Uemura and M. Yamamoto. Proposal of four-valuedMRAM based on MTJ/RTD structure. In Proc. Int. Symp.Mult.-Val. Log., 2003., pp. 273–278, May 2003.

[8] T. Waho. Resonant tunneling transistor and its application tomultiple-valued logic circuits. In Proc. Int. Symp. Mult.-Val.Log., 1995. (ISMVL 1995), pp. 130–138, May 1995.

[9] T. Waho, K. J. Chen, and M. Yamamoto. Resonant-tunnelingdiode and HEMT logic circuits with multiple thresholds andmultilevel output. IEEE J. S.-St. Circ., 33(2):268–274, Feb.1998.

[10] Z. Yan and M. J. Deen. New RTD large-signal DC modelsuitable for PSPICE. IEEE Trans. on Comp.-Aided Des. Int.Circ. & Syst., 14(2):167–172, Feb. 1995.

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