New Material Deposition Technologies for Advanced Packaging

Joachim Kloeser and Paul Kasulke EKRA Eduard Krafi GmbH

Zeppelinstr. 16,74357 Bonnigheim, Germany jKloeser@ekra.com, pKasulke@,ekra.com

Phone: +49 (0)7143 88 44 -0; http://www.ekra.com

Abstract Survival in today's competitive electronics market

continues to depend on advances on manufacturing technology. For example, the transition to 300mm wafers has become for many semiconductor manufacturers inevitability in their highly cost-sensitive market. The whole Advanced Packaging Business is growing enormously and the push for wafer-level packaging is driven by the high potential to save cost by advanced humping processes.

Area Array Packages (Flip Chip, CSP and BGA) require the formation of bumps for the hoard assembly. Here cost effective bumping methods are needed which are not limited by the throughput, minimal pitch and yield. The industry is currently searching for new and lower cost bumping approaches to avoid high investment costs for the process equipment. Furthermore, in the field of advanced packaging there is a demand for high process flexibility. This includes that other materials like adhesives or epoxies must be deposited on the wafer or on hoards. Due to the demand of the industry to transfer the production to 300" wafer these deposition processes must be suitable for this wafer size.

1. Introduction The direction of the semiconductor industry since

inception has been to increase productivity while reducing costs. This applies as much to IC packaging as to wafer fabrication. The goal is to produce IC packages (or bare die) that are smaller, faster and better performing-all for less cost. To that end advanced IC packaging techniques, such as chip scale packages (CSP's), bare die, multichip modules (MCM's) and 3D packaging continue to emerge and move into production.

Wafer level CSP is the lowest cost packaging method available today. This is not the only advantage of this technique. The package is attached to the face of every die, so each is placed on the board in flip chip fashion, face down and therefore providing superior electrical performance.

As the infrastructure grows for wafer level CSP, flip chip, bumping and other services/products that aid the flip chip market will drop in price, further reducing the cost of flip chip.

Since the established methods need expensive equipment and tooling resulting in. high investment and manufacturing cost an important impact for the cost reduction will be the implementation of cost effective bumping processes for flip chip and wafer level CSP.

An already established approach for creating bumps on wafer level CSP and flip chips as well as for SMT process is

stencil printing technology. The stencil printing technology was introduced to apply solder deposits for FC on wafers. Wafers with pitches down to 150pm for flip chip applications can be achieved and current developments are targeting down to 1 0 0 ~ m .

This established and well known stencil printing technology is mainly used so far for wafer diameters up to 200mm and has to be adapted now to 300" wafers to fulfill the requirements of the industry. The adaptation can be achieved without significant changes of the process however the implementation of automated handling is necessary to prevent the damagehreakage of these large and expensive wafers. Figure 1 shows a comparison of IOOmm, 200" and 300" wafers. Also the demand for faster and smaller devices like e.g. memory modules requests new technology aspects, especially the possibility of applying different materials on the wafer. The deposition of eutectic SnF'b, lead-free solder, high temperature solder and non solder materials will be described here in detail.

Fig. 1 Comparison of different wafer sizes (sourcc: WG-UM, ~ ~ ~ i i ~ )

2. Material Deposition by Stencil Printing Stencil printing is a well established standard technology

with a wide infrastructure and a know how which has grown up during the long use in the surface mount technology (SMT). Among several bumping processes used in the industry today, printing offers the greatest potential for cost savings

Solder Bumping Process Flow A key issue for the introduction in the field of fine pitch

wafer bumping is the availability of suitable materials and production machines. Therefore many suppliers improved the properties of solder materials, stencils, squeegees and

0-7803-8205-6/03/517.00 02003 IEEE 31 1 2003 Electronics Packaging Technology Canference

printing machines. Additionally certain investigations conceming printing quality, yield, production costs and reliability of stencil printing have been carried out. The process flow for solder stencil printing is shown in Fig. 2.

Fig. 2 Wafer bumping process flow by stencil printing

Solder Bumping Results State of the art for stencil printing is a typical bump

pitch of 0.5“ - 1.25” for CSP’s and 0.1” - 0.25mm for flip hip applications. Fig. 3 shows examples for FC applications with eutectic and lead free solder pastes and a pitch of 250pm. In Fig. 4 a CSP with 500pm pitch and high lead humps is shown.

Fig. 3a Eut. Sn63Pb37, type 6, before and after reflow

Fig. 3b Sn95,5Ag4Cu0,5, type 6, before and after reflow

Fig. 3c Flip Chip bumps with eut. SoPh (left) and SnAgCu (right)

. I . ,. :. ,.

Fig. 3d Cross sections of reflowed solder bumps, eut. SnPb (left) and SnAgCu (right)

Fig. 4 Chip Sue Package, PbSSSnlOAgZ, 500pm pitch

Non Solder Bumping Currently for a number of applications non-solder-

bumps are used. In this special process the non conductive material is also applied on wafer level. In order to avoid undertilling the package a special type of compliant bump is deposited.

Due to reliability aspects a certain bump height is requested. To realize the expected bump height the material has to be deposited three times. Fig. 5 shows non solder bumps.

Fig. 5 A 3-layer structure of a non conductive bump

Fig. 5b Side-view and top-view of a non solder bump

312 2003 Electronics Packaging Technology Conference

and non solder bumping (Infineon)

Due to the fact that the non conductive material has no self alignment effect, very strong requirements on the positioning accuracy of the equipment are essential. To fulfill theses requirements the print- and repeatability accuracy has to be better than +/- 12,5pm. Figure 5.c show a very new package type, process by Infineon Technologies, using a redistribution technology a low cost non solder bumping process.

3. Equipment for Material Deposition on 300mm Wafers a) Wafer Print System

In front-end environments it is common to use cell configurations. Cells (also called cluster tools) are a collection of handling, processing and measuring machines tightly integrated together to implement a specific process step. The factory CIM control system treats this a single entity.

Tracking and handling of work in progress (WIP) is facilitated by requiring that wafers must always be retumed to the same slothassette after processing in a cell. This ‘uni-cassette’ handling strategy is often used for 200” wafer processing. And, for the strict handling needs of 300” wafers, this is a requirement. The cassette for 300” wafers - called a FOUP (Front Opening Unified Pod) - is a complex mechanism that accompanies its wafers throughout their fabrication processes. Fully loaded with 25 wafers the FOUP’s weigh is approximately 40 kg, which is too heavy for manual handling. Openers for the FOUP’s (or load ports) are sophisticated machines that present a standardized mechanical interface to automated material handling systems (AMHS).

The new cell-based wafer printing system from EKRA employs - as a basis configuration - a sophisticated wafer handling robot surrounded by printer, FOUP opener(s), and pre-aligner. Equipped with a dual end-effector (Fig. 6), the robot can typically unload and load a wafer and move to the next processing station within seconds.

After removing the wafer from the FOG’ and pre- aligning it, the robot directly and accurately places the wafer in a tixed print nest. Because there is no conveyor or shuttle svstem. the orinter’s desim is ereatlv simolified and

alignment accuracy enhanced. As opposed to in-line (or pass-through) systems, the wafer is loaded and unloaded from the same side of the printer. Figure I shows the X5 W300 equipment with robot handling and two FOUP load port stations.

Fig. 6 300mm wafer handling robot with dual end effectors

~~

Fig. 7 El& X5 W300 Wafer Print System

Additional machines, such as an oven, automatic optical inspection (AOI) or a second printer, can he integrated into this basis configuration. The total cycle time for a print cell is approximately 1 minute/wafer for many applications. Up to 5-6 stations (e.g., FOUP opener, pre-aligner, printer, AOI, & oven) can be serviced by the cell robot within this time frame.

In-line reflow ovens are commonly used in the wafer humping process. In this case it is impractical to retum wafers to their original cassette slots. The cell can be expanded by adding load port(s) to the end of the oven or a second handling station incorporating an A01 andor cleaning station.

The accuracy of a wafer printing process is a critical factor in wafer bumping applications. Currently the print nrocess is caoahle of bumn-to-hum0 oitches of down to 150

313 2003 Electronics Packaging Technology Conference

microns, and developments activities are now targeting 100 microns. In order to achieve maximum height-to-diameter ratios, the pads are 'over-printed' with solder paste. As a result, the edge-to-edge spacing of the printed paste deposits can be as small as 30-50 microns and the stability of the reflow process is strongly influenced by the alignment of this pattern on the wafer.

To address this challenge, EKRA has developed its X5 G printer with an alignment accuracy of +/-12.5 microns (at Cpm=2.0 or 6 sigma) over a 300 x 300" area. The chance of the wafer-to-stencil misalignment exceeding a range of +/-6.3 microns is less than 2 out of 1 million prints with this printer. In-situ inspection of the print quality and stencil opening after printing provides important feedback to ensure a constant, robust process.

b) Solder Jetting System Solder jet printing or solder jetting is a relatively new

technology that is similar to ink jet printing with the exception that molten solder droplets or spheres are being printed instead of liquid ink droplets. More common jetting techniques include continuous deflection jetting and drop on demand jetting.

Drop on demand jetting differs from continuous jetting by only producing jetted solder spheres when triggered. During drop on demand jetting, the jetting head is positioned over the desired wafer location and the jetting device is triggered to dispense a single solder sphere.

The main element required to jet solder is the printing head. Figure 8 shows the new multi channel printing head developed by EKRA.

Fig. 8 Prototype of the liquid metal print head (patent pending)

The design consists of a silicon print chip with 10 jetting channels for the solder flow (Fig. 9). The droplet formation occurs by special designed piezoelectric actors, the

corresponding drop diameter is 70pm. By modifying the nozzle the drop diameter van be varied from 25pm to 150pm. Each channel can be controlled separately, so that jet printing is performed simultaneously. The entire device functions by electronic pulse actuation of the piezoelectric material to cause wave propagation of the solder through the channel and out of the dispensing end with a droplet rate of 5 d s (Fig. IO).

'111 I I I I111 I I I 1 1 1 I I I I I I I I I 1 1 1 ll* Fig. 9 Micro mechanical Silicon print chip with 10 jetting channels for the solder flow

Due to the multiple channel design and the high drop forming frequency (2-10 kHz) a very high bump rate and throughput can be achieved. Therefore this method of drop formation is very well suited for wafer bumping applications without any pitch limitations. Especially 300" wafers, where the number of pads is usually much more than 100.000, can be easily processed. Furthermore the bumping process can be performed fluxless. The maximal operation temperature of the solder jet system is 600"C, so that all relevant solders (lead free) can be used for wafer bumping and advanced packaging.

Micromechanical chip

Fig. 10 Principle function of the droplet formation (patent pending)

Conclusions The material deposition by stencil printing was

presented, describing the process flow for solder printing and non-solder bumping. Results of Flip Chip and CSP bumping using eutectic, high lead and lead free solder

314 2003 Electronics Packaging Technology Conference

pastes were shown, as well as examples of depositing non conductive material on wafer level.

Automatic equipment for solder bumping was introduced, a cell concept with robot handling for the processing of wafers up to 300mm and an alignment accuracy of +I- 12,Spm @ 6 sigma. This tum-key system is based on a cluster tool concept similar to those found in front-end applications and is compatible wit 13001 design principles and SEMI standards. The advantages of a cluster tool in comparison with traditional in-line systems include greater configuration flexibility, more effective utilization of handling robots and minimal footprint.

Additionally a new solder jetting system was shown. This system uses a new developed drop on demand print head which produces only jetted solder spheres when triggered. An extremely high throughput can be achieved due to a maximum droplet rate of IO kHz. With a max. operating temperature of 600°C a large variety of solder materials can be deposited on the substrate. Another big advantage is that this solder placement method is done fluxless, so that no additional cleaning step is required what is for a number of applications in the Advanced Packaging business absolutely essential.

315 2003 Electronics Packaging Technology Conference