The 2014 International Power Electronics Conference

A Transformer Inrush Reduction Technique for

Low-Voltage Ride-Through Operation of Renewable

Converters Hsin-Chih Chen Ping-Heng Wu Po-Tai Cheng

Center for Advanced Power Technologies

Department of Electrical Engineering

National Tsing Hua University

Hsinchu 30013, TAIWAN.

Abstract-The low-voltage ride-through (LVRT) capability has become one of the most important issues since more renew­able and distributed energy resource are installed in the grid. The LVRT capability means the converter should remain grid­connected and inject required current to support gird voltage. On the other hand, the sudden reduction of grid voltage may result in magnetic flux deviation in the step-up transformer as grid voltage sag occurs. The deviation of magnetic decays very slowly due to the high efficiency transformer, and it would lead to inrush current as grid voltage restores to normal leveI. This paper proposes a method to mitigate the magnetic flux deviation and limit the peak current without excelling the current capability of semiconductor devices by using a close-loop current control during LVRT operation. The proposed method can manage the converter's output peak current and reduce the risk of inrush current as grid voltage restores.

Index Terms-Low-voltage ride-through, flux compensation, inrush current, distributed energy resources

I. INTRODUCTION

Renewable and distributed energy resources (DERs) systems becomes popular in these years since the petroleum energy expensive. More DERs systems are installed in the utility grid, their effect on the power system's stability become an important issue. Thus, the grid operators start laying down the specific requirements for the grid-connected DERs systems.

The Low-voltage ride-through (LVRT) capability is one of the most important issues in the grid codes [1], [2], [3], [4], [5]. In wind power system, the power converters should remain connected to the grid and inject the required current to support grid voltages. Several converter control strategies have been reported [6], [7], [8] for the LVRT functionalities.

In wind power generation system, the grid-side converter is connected to the utility through a step-up transformer [9], [10]. In LVRT operation, the sudden reduction of grid voltages often lead to the magnetic flux deviation in the step-up transformer. The magnetic flux deviation decays very slowly due to high efficiency nature of the transformer, and it easily leads to inrush current in grid side of the step-up transformer as grid voltages restore to the normal level [11], [12]. This inrush current results in unbalanced magnetomotive force (MMF) , which can exert significant axial forces on transformer windings and wreck its insulation [13]. In order to reduce the occurrence of this phenomenon, this paper proposes an inrush

current mItIgation method for the grid-connected converters during the LVRT operation.

The grid voltage becomes unbalanced in LVER operation, Hsu et al. [8 ] presented a peak current limit control (PCLC) to meet the grid requirement and manege the peak current. Based on PCLC method, this paper presents a flux compensation technique with peak current regulator to limit the peak current without excelling the current capacity of semiconductor de­vices. Thus, the stress of both the transformer and the converter can be managed appropriately.

II. FUNDAMENTAL ACTIVE AND REACTIVE CURRENT

STRATEGY

The overall system configuration of the converter and over­all control block diagram are shown in Fig. 1. A three-level neutral-poi nt-clamped (NPC) converter, which is typical for MW class wind power system, is connected to the grid through a delta-wye transformer.

A. Converter voltages and currents The voltages become unbalanced as voltage faults, the phase

voltages and currents can be expressed as Equation (1) and Equation (2) , where VP and vn are the positive- and negative­sequence components of the voltage. IP and In represent the positive- and negative-sequence currents. 81 and 82 are the phase angles of the positive- and negative-sequence voltages with respect to the reference axis. 8p and 8n are the phase angles of the positive- and negative-sequence currents in reference to their voltage components.

Va = VP cos(wt + 81) + vn cos( -wt + 82) 27r n 27r

Vb = VP cos(wt - ""3 + 8I) + V cos( -wt - ""3 + 82) (1)

27r 27r Vc = VP cos(wt + ""3 + 8I) + vn cos( -wt + ""3 + 82)

ia = IP cos(wt + 8p) + In cos( -wt + 8n) 27r 27r

ib = IP cos(wt - ""3 + 8p) + In cos( -wt - ""3 + 8n) (2)

27r 27r ic = IP cos(wt + ""3 + 8p) + In cos( -wt + ""3 + 8n)

978-1-4799-2705-0/14/$31.00 ©2014 IEEE 1261

1 p"

Fundamental active andf-O',,-I -,--' -r-t--I

llllax ig.::..;a ,�i",,-b;,...' i"'l", t----I Propos:d magnetic flux i e.a"

mltlg�tlon met�od wIth ""i"", b7. ------"-++�___t__,� '0' 'b, " virtual rom(or f-',""',,"o. ----"-+---{x)--t-;�

(Fig 7)

Fig. 1. Overall system configuration control block diagram.

Fig. 2. Block diagram of PCLC.

The transformation for the stationary reference frame, the positive- and negative-sequence synchronous reference frames are given as:

[�;] [g 1 -1

-y'3

[ ��] [ ��]

[cos(wt) sin(wt) [ cos(wt) - sin(wt)

(3)

These synchronous frame values (vg,v�,v�,v�) include 2w ripples due to the unbalanced voltages, thus low-pass filter (LPF) and band-reject filter (BRF) are employed to extract their DC components V:' VI, Vqn, Vdn respectively. The phase angles can be calculated as:

-1 VI e1 = - tan ( ii,P ) q IP*

ep = - tan-1( I�*) q

B. LVRT with peak current limit

(4)

Fig. 2 shows the control block diagram of the peak current limit control (PCLC) method. This method has been presented in [8], which can use to meet grid code and fully utilize the ampere capacity of grid-connected converter. The PCLC method can pre-define ampere capacity IpCLC which is allocated for fulfilling the LVRT requirement. The grid code

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v; Current Vh"

controller

Fig. 3. Three-phase circuit diagram.

n

requires the positive-sequence active current If and reactive

current If injection during sags, the PCLC method calculates the fundamental negative-sequence reactive current (r:f) to ensure the peak current of each phase are not higher than the budget of I PC LC, In* = ° q r:f

= -IP cos(ex + k 4;) + (JP)2[COS2(ex + k �)] + I�cLC {O' -7r/3 :s; ex < 7r/3

where k = 1, 7r /3 :s; ex < 7r -1,7r:S; ex < 57r/3

(5)

Note that the negative-sequence reactive current is inductive (ie: en = -�) which can reduce the negative-sequence component of grid voltage.

III. PROPOSED TRANSFORMER FLUX MITIGATION METHOD

Based upon the PCLC method, this paper proposed a trans­former magnetic flux compensation technique. The magnetic flux deviation is caused by sudden change of grid voltage as fault occurs, and the flux deviation decays very slowly. This paper proposed a state-feedback current control technique to mitigate the deviation quickly, and hence reduce the risk of inrush current when grid voltage recovers to normal level.

A. Transformer circuit model Fig. 3 shows the circuit diagram of delta-wye step-up trans­

former, where Va, Vb, Vc are output voltages of the converter, ia, ib, ic are output currents of the converter, VgDa, VgDb, VgDc

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Fig. 4. The single-phase equivalent circuit diagram of a-phase.

Fig. 5. Block diagram of transformer model in a-phase as voltage sags occur.

are grid voltages, and igDa, igDb, igDc are grid currents. The turns ratio of the transformer is y'3 for simplicity. The voltages and currents of the delta side and wye side are related as: [vgaj _ 1 [VgDa - V9Dbj

Vgb -y'3

VgDb - VgDc Vgc VgDc - VgDa [igDaj _ 1 riga - i9bj ZgDb - fCi Zgb - Zgc . v3 · · ZgDc Zgc - Zga

(6)

Fig. 4 shows the a-phase transformer equivalent circuit of Fig. 3, where L is the leakage inductance, R is the winding resistor, Lm means the magnetizing inductance, and Rc represents the core loss. The voltages and currents can also be expressed as block diagram in Fig. 5. As voltage sags occur, the sudden reduction grid voltage results in the magnetic flux deviation (Aoffset). TABLE I shows the parameters of transformer equivalent circuit, and Fig. 6 shows the response of the transformer flux linking Amk. assumes the step input disturbance AOffset = 0.5Wb occurs to the transformer. The response waveform shows that it takes more than 90 seconds for Amk to decay to 0.01 Wb. Thus, if the significant flux offset still remains in the transformer, it can easily lead to inrush current as grid voltage restores to normal level.

� 03 .;;! 0. � 02

01

Response of magnetic de flux offset

°0�--�20�--�40�-=�6�0���8� 0�--�100 Time(s)

Fig. 6. The natural response of the transformer DC flux linkage Amk.

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TABLE I TRANSFORMER PARAMETERS

Transformer parameters

Winding resistance (R) Core loss of the magnetic core material (Re)

Winding leakage inductance (L) Magnetizing inductance (Lm)

19a, 19b, 19c

0.30350

3083.370 294.43ftH

2.6691H

Fig. 7. Block diagram of proposed magnetic flux mitigation method.

Fig. 8. The equivalent circuit of a-phase with proposed flux mitigation method as voltage sags occur.

B. The proposed method to mitigate the magnetic DC flux deviation

This paper proposes a state-feedback current control tech­nique to accelerate the decay of transformer magnetic flux deviation. Fig. 7 shows the control block diagram of the proposed method. Fig. 8 shows the proposed method can be implemented as a current-controlled current-sources of DC component at converter side of the transformer to mitigate the flux deviation.

In Fig. 5, the magnetic flux deviation (Aof fset) results in current offset (lLma,dev, ILmb,dev, ILme,dev) in the trans­former's equivalent circuit. Thus, the converter side currents (ia, ib, ic) and grid side currents (iga, igb, igc) are taken for the offset current calculation. A low-pass filter (LPF) and a band­reject filter (BRF) are employed to filter out the fundamental components and smooth the output.

After the core current deviation (lea, lcb, Icc) has been known, a proportional controller is used to generate the compensating current command (i fe,a *, i fe,b *, i fe,e *) of each phase to reduce the flux deviation.

ife,a * = Pfe . (0 - (Ia - 19a))

ife,b* = Pfe' (0 - (h - 19b))

ife,c* = Pfe· (0 - (Ie - 1ge))

C. Peak current control

(7)

The proposed method generates compensating current to mitigate the magnetic flux offset of the step-up transformer. However, the compensating current may result in high peak current in converter side of the transformer.

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1 max ,� e

fe(peak) b /h(peak) ,---- a

+ �-K . K b Mtn� '" fa(peak) Ila(peak) l- la/e(max) N Ka

irc.c * N1 -

/ ifob Ix l

'" ifo.a lifo a *1 '--

Fig. 9. Block diagram of peak current regulator.

Fig. 9 shows control block diagram the peak current regula­tor. The proposed method employs the peak current regulator to scale the peak current without higher than Imax, which is designed based on the current capacity of semiconductor devices.

Because the fundamental injection current has negative­sequence component, the remaining current capacity of each phase are different. The peak currents of each phase (Ia(peak), h(peak), Ie(peak)) can be calculated as Equation (8 ) [8] and the maximum current capacity of proposed flux compensation can be calculated by Equation (9) .

Ia(peak) = J(Ip)2 + (In)2 + 2Ip In cos (0)

h(peak) = (Ip)2 + (In)2 + 2IP In cos (0 + �) Ie(peak) = (Ip)2 + (In)2 + 2Ip In cos (0-

4;) (8 )

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v abc Vb Va.,Vp Vc J

a Va. *

. * . * * Va.

la. , lp Va.

abc

a� Fig. 10. Block diagram of current controller.

TABLE II TRANSFORMER PARAMETERS

Vp

Filter and controller parameters

Cut-off frequency of LPF (WLPF) Cut-off frequency of BRF (WBRF)

Quality factor of BRF (Q)

* af3 J

abc

Proportional gain of proposed flux mitigation method (Ptc) Proportional gain of current controller (PI)

regulated as , * i fe, a = i fe,a * . K

i�e,b* = ife,b*' K

i�e,e * = ife,e * . K

* Va

* Vb

* Vc

40Hz

60Hz

0.5

10.7

70

(12)

After all the current commands have been decided, the current controller is employed to regulate the converter's output current and it's shown as Fig. 10.

I V. LABORATORY TEST RESULTS

Ia,Je(max) = Imax - Ia(peak) h,Je(max) = Imax - h(peak) Ie,Je(max) = Imax - Ie(peak)

The system configuration and overall control block diagram (9) are shown in Fig. 1, the parameters of the step-up transformer

has been shown in TABLE I, and TABLE II shows the

After the maximum current capacities of each phase have been calculated, the Ka , Kb , and Ke gains is used to scale the compensating current within the current limit (Imax).

Ia,Je(max) K a = -,-"'----'---.'---.

life,a *1

K _ h,Je(max) b - life,b *1

K _ Ie,Je(max) e - life,/I

(10)

In order to make sure all the peak currents without excelling than pre-defined value (Imax), the scaled gain (K) should be selected as the minimum. Moreover, the scaled gain (K) will be set at 1 as the highest current without higher than Imax, which means keep the original value.

K = min (Ka , Kb , Ke)

(if K "2 1, K = 1) (11)

Finally, the output compensating current commands will be

parameters of filters and controllers. The system parameters are shown as follows.

• The AC voltage is 220 Vrms (line-to-line) , and the fre­quency is 60 Hz. The DC bus voltage is 400V.

• The rated capacity is 1k VA, the rated current is 3.7 A. • The switching frequency of converter is 10kHz, sampling

frequency is 20kHz. • The output filter Lf = 4mH, Cf = 6.8f.1P. • The pre-defined peak value of PCLC method is set at

IpCLC = 1p.u. = 3.7 A, the pre-defined maximum peak current is set at Imax = 1 .4p.u. = 5. 2 A

• In LVRT operation, the reactive positive-sequence current commands are set at Ig* = 0 and Ir = 0.7p.u. = 2.6 A

The voltage sag has been defined in IEEE PI668 [14]. The type B (single phase 50% voltage reduction) and type E (two phases 50% voltage reduction) are tested in this paper, where the sags duration are 27. 5 times fundamental cycle.

Fig. II(a) shows the converter's phase voltages waveform as the voltage sag occurs under type B voltage sag test. The 50% voltage sag happens at the grid side of transformer, the response is like two phase voltage sag at the converter

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side. Fig. 11 (b) shows the current commands of PCLC, the method confines the peak current to pre-defined value (lPCLc) and the current waveform is unbalanced. Fig. 12(a) shows the converter's phase currents waveform without peak current regulator, and Fig. 12(b) shows the converter's phase current with proposed peak current regulator. Fig. 13(a) and Fig. 13(b) show the comparison between with proposed flux compensa­tion and without proposed flux compensation. In Fig. 13(a), the proposed flux compensation method reduces the inrush current as grid-voltage recovers to normal level.

Fig. 14(a) shows the converter's phase voltage waveform, Fig. 14(b) shows the converter's PCLC current command, and Fig. 14(c) shows the converter's current waveforms during LVRT operation under type E voltage sag. Fig. 14(c) shows the peak current regulator limits the peak current at Imax.

I I "--" LVRT ol1eration

: I

t- ",,",y 5V L-10 ms

(a) Converter's phase voltage waveform.

2.5AL 10 ms

(b) Converter's PCLC current command.

Fig. 1l. Circuit diagram of grid-connected step-up transformer.

V. DISCUSSION

The laboratory test result shows the proposed method injects the compensating current to reduce the inrush current. In the proposed method, a low-pass filter (LPF) and a band­reject filter (BRF) are employed to extract the core current deviation then using a proportional controller to generate the compensating current command. The cut-off frequency of low­pass filter (WLPF) and the proportional gain (Pic) are the parameters that can be regulator easily.

Fig. 15(a) and Fig. 15(b) show the root locus of the domi­nate pole which are variable Pic and WLPF. The parameters of this paper are shown as TABLE I and TABLE II, where the operation point of the laboratory test result is marked as red point in the Fig. 15.

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(a) The converter's current waveform without peak cur­rent regulator.

(b) The converter's current waveform with peak current regulator.

Fig. 12. The converter's current waveforms during LVRT operation.

......- Sag dection signal (end)

E.§iiBii"-(a) Grid's phase currents waveform with flux compen­sation.

i J::h current g/j

(b) Grid's phase currents waveform without flux com­pensation.

Fig. 13. Grid side current waveform as the voltage recovers to normal level.

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I I "--- LVRT operation I I

90 VL 10 ms

(a) Converter's phase voltage waveforms.

I � I---.lvRT o,."rta'on I I I

(b) Converter's PCLC current command.

(c) Converter's phase current waveforms.

Fig. 14. The waveforms during type E voltage sag.

In order to extract the magnetic flux mitigation exactly, the cut-off frequency of LPF should be selected as low as possible. However, Fig. 15(b) shows the compensating response become slow as the cut-off frequency of LPF is decreased. Fig. 16 shows the converter's current waveforms as the WLPF is set at 5Hz and the proportional gain PIc is set at 10. 7 under type B 50% voltage reduction. Fig. 16 and Fig. 14(c) verify the compensating response becomes slow as the cut-off frequency of LPF is decreased.

VI. CONCLUSION

As grid side voltage sag occurs, the sudden reduction of grid voltage usually results in magnetic flux deviation in the step-up transformer. The flux deviation decays very slowly since the high efficiency transformer and it would lead inrush current in grid side of the transformer as grid voltage restores to normal level. The inrush current would generate unbalanced magnetomotive force to damage the insulation of the transformer windings.

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(a) The diagram of dominate pole (vari­able of Pjc).

1$0 -- ---;--------�-------;--------�-------;--------,--

� ••• � ••••.•••... :�. �.-----+.------+JI ... ... .. .

(b) The diagram of dominate pole (vari­able of WLPF).

Fig. 15. The diagram of root locus.

Fig. 16. The converter's phase currents as the WLPF is set at 5Hz.

This paper presents an inrush current mltlgation method based on state-feedback current control. The proposed method injects compensating current to accelerate the decay of the flux deviation during LVRT operation. Moreover, the proposed method includes a peak current regulator to limit the peak current without higher than pre-defined value which is design by the current capacity of the semiconductor devices. The laboratory test result shows the inrush current is reduced by proposed method and the converter's current is limited.

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