Backside Device Physical Analysis for Yield and Reliability of Advanced Bulk-Si CMOS ICs

Yuanjing (Jane) Li and Howard Lee Marks Silicon Failure Analysis, nVidia Corporation

Santa Clara, CA USA 1- (408) 486-6217, janli@nvidia.com

Abstract—This paper presents an effective backside device physical analysis methodology for identification of defects and weaknesses from design or manufacturing in advanced flip-chip packaged bulk-Si CMOS ICs. Case studies demonstrate applications of the methodology and techniques in failure analysis and process evaluation of 28nm CMOS devices and beyond for yield and reliability enhancement.

Keywords-component; Bulk silicon backside de-process; SEM; FIB; EBAC; e-fuse; OPC end-result

I. INTRODUCTION As IC technology advanced, devices became smaller,

denser and more complex. A leading-edge IC graphics processing unit can contain billions of transistors with more than ten layers of interconnect and assembled in a flip-chip package. Defect localization and analysis in such a device using traditional front-side techniques have become ineffective and non-viable, especially for defects located at the transistor-level or lower interconnect metallization. An efficient and advantageous backside deprocessing technique was therefore developed to enable direct access to the transistors in a bulk-Si device.

Details of the backside deprocessing technique have been previously given [1]. It involves the use of a highly selective potassium hydroxide (KOH) chemical wet etch to remove all silicon from the die to expose transistor-level structures. Backside parallel polishing can be applied to access metal interconnects. This deprocessing technique allows defects and anomalies at any level of an IC device to be localized and analyzed from the backside of the die, without detaching the die from the package.

This paper presents backside device physical analysis methodology and techniques for defect localization and analysis at transistor-level and in the interconnect metallization. Case-studies taken from 28-nm IC debug during process development and yield ramping will be presented to illustrate the applications of the techniques for yield and reliability improvement. The first case study shows an application in e-fuse programming reliability evaluation. The second shows how the backside physical analysis helped isolate a yield limiting design issue in a MOS capacitor, while the third and fourth show how the technique was used to investigate fab Optical Proximity Correction (OPC) issues and a case with missing contacts.

Figure 1. Optical image showing a 28nm flip-chip SOC microprocessor before and after silicon removal from the die backside.

II. REMOVING SILICON FROM THE DIE BACKSIDE To root-cause a failure, test techniques such as scan based

diagnostics such as laser modulation mapping [2] and/or techniques such as backside photo emission microscopy is used first to locate the fault into within a suspect area. Without removing the die from the package, a mechanical grinding and polishing is then performed on the backside of the die using a milling machine to remove most of the silicon thickness until the underneath circuit is visible (<5μm thick). A potassium hydroxide (KOH) wet chemical etching at 120oC is then used to remove the remaining silicon. The high selectivity of the KOH wet etch (Si/SiO2 is >1000:1) leaves the gate level materials and the entire interconnect metallization intact. Fig. 1 shows a flip-chip packaged 28nm technology graphics processing unit before and after the backside Si removal.

III. SEM IMAGING OF IC STRUCTURES With IC structures fully exposed at the gate level,

unprecedented access is provided for SEM (scanning electron microscope) imaging and analysis of the transistor structures and defects. Fig. 2 shows high resolution SEM images of transistor gate-level structures from the die backside before and after Si etching. Fig. 2(a) shows the active silicon regions that are still covered by a diffusion of a thickness less than 200nm; Fig. 2(b-c) show SEM images of fully exposed gate dielectric and source/drain silicide in active regions after diffusion is completely removed. N-MOSFETs with visible W-plugs and P-MOSFETs with Si-Ge stressors underneath the source-drain silicide are clearly imaged.

(a) flip-chip device (b) after Si etching

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Figure 2. SEM images showing transistor-level structures in active regions

and avove the STI from backside of a 28nm device in the logic area. (a) Backside view of device active regions after Si substrate removal and partial

diffusion removal; (b-c) Backside views showing MOSFET gate-level structures in active regions after complete removal of silicon diffusion; (d)

Backside view of diffusion silicon in active regions and gate, contacts and M1 structures between active regions after STI oxide removal.

Fig. 2(d) shows exposed gate material, W-plugs and M1 between active regions after STI removal using PAD oxide etch. To expose active regions without completely remove the diffusion, it is recommended that the device is removed from the etchant immediately after the circuit is visible to naked eyes. Over-etching will result in a complete removal of the diffusion. A simple calibration using SEM may be necessary to help gain experience.

To expose defects in interconnect metallization, a mechanical parallel polishing can be performed easily after Si etching. Because of the material removing selectivity during mechanical polishing, parallel polishing from the die backside after Si removal is much easier than from the die front side. Contacts, vias, or any metal layers can be uniformly exposed over a very large area or even the entire die. Fig. 3 shows SEM images of device structures exposed at various levels after backside parallel polishing. Fig. 3(a) shows SEM image of gate-level structures, including gate, source/drain silicide and a thin layer of diffusion, viewing from the die backside. Fig. 3(b-c) shows exposed contacts and buried M1 underneath a thin layer of oxide imaged with backscattered electron (BSE) and secondary electron (SE) detecting modes.

Because the active silicon regions are removed from the backside, all signal nodes in the die become electrically floating whereas the power and ground planes are still connected and grounded through the flip chip package. This is shown in the charged up M1 shown in Fig. 3(c) when SE mode is used for imaging.

Diff.

STI

(a) Actives of die backside after Si substrate and partial diffusion

STIPMOS

NMOS

(c) Close-up SEM image of exposed active regions

diffusion

(d) Exposed structures above the STI

(b) SEM image of active regions after all diffusion is removed

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Figure 3. (a) SEM image showing gate-level structures from die backside after Si etching followed by a mechanical parallel polishing. (b) SEM imaging

operated at BE mode shows W-plugs and M1 behind; and (c) SEM imaging operated at SE mode showing the floating contacts and M1 underneath the

oxide after backside Si etching and mechanical parallel polishing.

Taking advantage of the high sensitivity of BSE imaging mode in SEM, it is possible to examine gate anomalies or any defects with good atomic contrast with respect to their surroundings, such as high k gate materials, NiSi of the source-drain contacts, W plugs, or Cu with Ta/TaN buried below the surface of the low Z dielectric or polysilicon layer [4]. Fig. 4 illustrates 28nm gate-level IC structures on the same device area imaged in SE mode and BSE mode in the SEM, respectively, with SE highlighting the IC close to the surface and BSE underneath the surface.

Figure 4. (a) High resolution SEM image showing backside of MOSFET gate

structures in a 28nm process GPU after silicon removal; (b-c) SE and BSE images of the gate level structures on the same area of the device.

(b) BSE image of exposed W-plugs and buried M1 after polishing

(c) SE image showing electrically floating contacts and M1

NMOSPMOS

(a) SEM image showing gate-level structures from die backside

1µm

(a) 28nm gate-level structures imaged in SE mode

1µm

(b) 28nm gate-level structures imaged in SE mode

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IV. PROCESS EVALUATIONS

A. e-Fuse Characterization Backside de-processing provides an excellent opportunity

to examine electrically programmable fuses (eFuses) for reliability assessment and fuse failure analysis.

Using traditional front-side hand-polishing methods, it is difficult to maintain a leveled polishing over a large chip area. As a result, the oxide cover over the eFuses will vary in thickness, with the effect that no two fuses will look the same, even under identical SEM imaging conditions. This makes it difficult to physically compare and evaluate fuses blown under different conditions. The backside de-processing, on the other hand, makes it possible for a large number of e-fuses to be examined under the same sample condition and SEM operation condition without distortions from artifacts introduced from the traditional front-side sample preparation.

Figure 5. Poly fuses of 40nm technology node blown with various programming conditions imaged from backside of the die through a thin layer of dielectric. The fuse blowing mechanism is Joule-heating and gap formation

in the middle of the fuse stem. (a) Optical image of many fuses from a fuse bank; (b) SEM image using BSE detection mode; (c) Cross section STEM image showing details of the microstructural change in a blown poly fuse.

Figure 6. SEM images showing second type of poly fuse. SE mode (a) and BSE mode (b) in SEM were used to image the polysilicon at the bottom and

the silicide on top of the fuse body, respectively. The redistribution of the silicide is a result of the electro-migration during programming. Note the poly

fuse consists two layers of materials: silicide on top of polysilicon.

Figure 7. SEM image showing 28nm technology M2 fuses imaged from backside of the die through a thin layer of oxide. Fuse material changes in the blown fuses conrrespond to various programming conditions. An additional oxide etch was used to thin the extra thickness of the dielectric for M2 fuses.

To image eFuses in a SEM, a chemical etching of dielectrics is performed following the backside Si removal until only a thin layer of dielectric is left. As long as the thickness of the dielectric above fuses is thinner than the secondary electron escape depth, the fuses can be clearly imaged in SEM without artifacts.

Fig. 5-7 show SEM images of three different kinds of eFuses programmed at various conditions (voltages, pulse widths and temperatures). Different blow mechanisms are made use of to achieve the resistance increase in the link that alters the fuse logic state from low to high. The planar-view images were taken from the backside of the die through a thin

Poly

M1

Silicide

300nm

(c) Cross section STEM image of a blown poly fuse

Redistributed silicide

+_

200nm (b) BSE image showing redistributed silicide behind polysilicon

Polysilicon

(a) SE image showing backside surface of the poly fuse

Overblown Just right Underblown

1µm

(b) BSE photo of poly fuses imaged from backside of the die

(a) Optical image of poly fuses taken from backside of the die

1µm2.5V/12us

1.8V/12us1.8V/12us

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layer of dielectric. Fig. 5 shows poly fuses of 40nm technology node blown with three various programming conditions. The fuse resistance increase is resulted from the Joule-heating and gap formation in the middle of the fuse stem. BSE detection mode was used in planar SEM image to reveal the NiSi redistribution behind the polysilicon as a result of fuse programming. Cross section STEM image shows detailed microstructural change in a blown poly fuse.

Fig. 6 shows SEM images of a second type of poly fuse. The bottom polysilicon layer of the fuse body was imaged using SE detection mode since it is near the surface. The top silicide layer in the fuse body was imaged using BSE mode through the polysilicon. The resistance increase in this type of the fuses is resulted from the redistribution of the silicide as a result of electro-migration of the silicide layer. Fig. 7 shows a SEM image of 28nm technology M2 fuses blown with various programming conditions. The blow mechanism of the metal fuses is Joule-heating and gap formation in the middle of the fuse link.

Reliable fuse blowing requires a programming condition that can deliver a constant resistance increase accompanied by a consistent material redistribution or structural change. Neither over-blow nor under-blow can produce reliable fuse state alterations.

The backside fuse SEM imaging method has proven invaluable in e-fuse programming optimization, reliability assessment and failure analysis.

B. OPC End-Result Examination Optical proximity effects cause features to be printed

differently than intended. Optical Proximity Correction (OPC) is increasingly being used to try to correct for these discrepancies. However, even with the most rigorous OPC, the weaknesses can still occur due to the dense patterning and the tight process window.

Figure 8. SEM images showing OPC end-results from backside of a 28nm

device after Si and transistor materials removal using Si etching and a parallel polishing. (a) contacts in front of M1; (b) M1 in front of via 1 in front of M2.

The backside electron microscopic imaging technique provides a means to directly examine the end results. To image the OPC at contact-M1 level or M1-via1 level, backside parallel polishing was performed following the KOH Si etching until gate materials of the transistors are all removed. Fig. 8(a) shows SEM images of the OPC end results at contact-M1 level in a dense logic area of a 28nm flip-chip packaged device. Fig. 8(b) shows OPC at M1-via1 and via1–M2 levels after a further polishing. Using this method, weakness OPC locations were identified. The information was relayed back to the fab for process improvement.

V. FAILURE ANALYSIS CASE STUDIES

A. MOS Capacitor Yield Loss Analysis A MOS decoupling capacitor in a GPU was suffering from

an abnormally high yield loss. A photon emission spot was found on the backside of the fail units on the MOS capacitor area. To root-cause the defect, the part was de-processed and SEM analysis performed to investigate the emission “hot spot”.

To determine whether the emission is originated from the MOS capacitor’s dielectric or from the underlying metal, SEM imaging was operated at SE and BSE imaging modes with proper accelerating voltages. Fig. 9 shows the backside SEM images on the area of interest. Fig. 9(a) and (b) show the MOS dielectric on the surface and the M1 behind the dielectric in the emission area highlighted using SE mode and BSE mode, respectively. Using this method, it was determined that the anomaly was located underneath the MOS dielectric. FIB cross section performed across the damage area confirmed that the failure is originated from the metal behind the MOS capacitor. The information was fed back to the designer who implemented a design change, along with a new DFM rule, that resulted in a significant yield improvement.

M1

Contact

(a) Close-up backside planar SE image of contacts in front of M1

M1M2Via1

(b) Backside planar BSE image of M1, Via1 and M2

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Figure 9. SEM images showing the MOS capacitor dielectric from the backside of the die after Si removal highlighted at 5kV e-beam voltage using SE imaging (a); the MOM capacitor behind the MOS dielectric on the same

area imaged at 10kV using BSE imaging (b); and FIB cross-section across the emission spot (c). A breakdown damage was revealed in the MOM capacitor

underneath the MOS capacitor.

B. Missing Contacts This is a case of missing contacts due to a fab process error.

SEM inspection was performed from the die backside. The die backside Si etching was used followed by a parallel polishing until the gate is exposed. SEM image in Fig. 10 reveals that two gate contacts are missing in the logic cell isolated by backside the laser modulation mapping technique (LVx).

Figure 10. (a) CAD layout of the region of interest; (b) SEM image revealing missing of the two gate contacts after backside Si etching followed by a

parallel polishing.

VI. DEFECT LOCALIZATION IN METALLIZATION The preservation of the entire IC metallization after

backside silicon etching opens an excellent opportunity for defect localization in a failing net using backside Electron Beam Absorbed Current (EBAC) technique [3]. The defect mapping technique allows for landing a nanoprobe on any net that connects to source/drain or gate regions and mapping the current flow in that net, including any other nets connected by a defect. Shorts and electrical opens or resistive defects can be effectively identified, if they exist anywhere along that net. Fig.11 shows a clock net mapped using backside EBAC from a 28nm flip chip bulk Si device. A single nanoprobe needle was landed on a source-drain silicide contact with a 10kV e-beam acceleration voltage.

Once the defect is located in a SEM/FIB dual-beam system, FIB cross section can be performed easily. Since the exposed active regions matches the diffusion CAD layout, the assistance of CAD navigation is unnecessary.

MOS Capacitor

STI 1µm

(a) SE image of MOS showing cap dielectric after Si removal

STI

M1

M2M3M4

Gate MetalSTI

500nm

(c) Cross section SEM image showing damage in MOM cap

MOM Capacitor

1µm

(b) BSE image showing MOM cap structure behind the MOS cap dielectric

(a) CAD layout showing area of interest

Gate

M1 500nm

(b) Planar backside BES image showing two contacts are missing

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Figure 11. (a) SEM image showing backside de-processed 28nm bulk Si device with nanoprobes; (b) a clock net mapped in a 28nm GPU chip using

EBAC technique (Image courtesy of Bob Newton at DCG Systems); and (c) A FIB cross section analysis performed at failure site located by EBAC.

VII. ADDITIONAL COMMENTS 1) Backside chip physical analysis method has been shown

to be applicable to 20nm technology and 16nm 3D FinFET devices. It is expected to play an even more important role for process development and yield and reliability improvement.

2) Different types of silicon etchers can also be used for backside silicon etching, particularly TMAH (Tetramethylammonium hydroxide) which seems to be quite tolerant to the thickness variations of the remaining silicon, except that it tends to lift the package solder mask material during silicon etching.

VIII. CONCLUSIONS Backside IC physical analysis methods and the techniques

were presented for physical analysis of flip-chip packaged bulk Si CMOS ICs. Case studies illustrated how the methods can be used to help root-cause device defects and identify process and design weaknesses. The invaluable design and process information thus obtained helped contribute to significant yield and quality improvement of product ICs.

ACKNOWLEDGMENT The authors wish to thank Steven Scott and John Aguada

for helping in sample preparations and William Lo for technical inputs and helping improving the paper.

REFERENCES [1] Y. Li, S. Scott, and H. Marks, “Advanced Physical Analysis

Methodology for Yield and Reliability of 28-nm, Bulk-Si, Flip-Chip ICs Using SEM and Backside Deprocessing,” Proc 38th ISTFA, pp. 197-202, November 2012.

[2] S. Kasapi et. al., “Advanced Scan Chain Failure Analysis Using Laser Modulation Mapping and Continuous Wave Probing”. Proc 37th ISTFA, pp. 12-17, November 2011.

[3] K. Dickson, G. Lange, K. Erington and J. Ybarra, , “Electron Beam Absorbed Current as a Means of Locating Metal Defectivity on 45nm SOI Technology,” Proc 36th ISTFA, pp. 413-422, November 2010.

[4] Z. G. Son et. al., “Backscattered Electron Imaging for Embedded Subtle Defects in 32nm Processes”. Proc 36th ISTFA, pp. 108-112, November 2010

(a) Backside deprocessed 28nm device with nano-probers

(c) FIB cross section performed from die backside at defect location

(b) A clock net mapped in 28nm GPU with EBAC

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