978-1-4799-1205-6/13/$31.00 ©2013 IEEE

Performance Improvement of PFSCL gates through Capacitive Coupling

Kirti Gupta1#, Neeta Pandey2#, Maneesha Gupta3*

# Electronics and Communication Division, Delhi Technological University, New Delhi 1kirtigupta_22@yahoo.com, 2n66pandey@rediffmail.com

* Electronics and Communication Division, Netaji Subhas Institute of Technology, New Delhi

3maneeshapub@gmail.com

Abstract— In this paper, a new positive feedback source-coupled logic (PFSCL) style with higher speed than the existing PFSCL style is proposed. The proposed logic style replaces the load in existing PFSCL with a new load which exhibits capacitive coupling that enhances the switching speed of the circuits. The mechanism of capacitive coupling is modeled and its effect on the propagation delay is described. SPICE simulations to validate the proposed theory have been carried out with TSMC 0.18 µm CMOS technology parameters. Several PFSCL logic gates such as inverter, NAND2, NOR2, NOR3 based on the proposed logic style are implemented and their performance is compared with the existing PFSCL logic gates. It is found that the logic gates based on the proposed PFSCL style lowers the propagation delay by 31 percent.

Keywords: Source-coupled logic, PFSCL, positive feedback, capacitive coupling

I. INTRODUCTION The proliferation of mixed-signal applications at

radio frequencies has profound impact on the design of high speed digital circuits. At these frequencies, positive feedback source-coupled logic (PFSCL) style show better performance than traditional source-coupled logic (SCL) style [1-4] which can be attributed to the positive feedback that eliminates the voltage reference source used in the traditional one. The presence of the feedback results in significant reduction in the sizes of the transistors in contrast to the traditional counterparts, thus improves its speed by lowering the parasitic capacitances for a given power consumption [1]. Further, the increase in the speed can also be traded off with the power to achieve the speed requirement.

The performance of PFSCL gates referred hereafter

as traditional PFSCL (T-PFSCL) can be improved by using a load that exhibits capacitive coupling. Its

application in the traditional differential SCL gates has resulted in the speed improvement of 23 percent [6]. In this paper, a new PFSCL style with capacitive coupling that increases the switching speed of the circuits is proposed. These circuits may be abbreviated as PFSCL-CC circuits.

The paper first presents an overview of the T-

PFSCL style in section II. Thereafter, the architecture of the proposed PFSCL-CC style is described in section III. A variety of digital circuits is implemented and is compared with the T-PFSCL counterparts through simulations using 0.18 µm TSMC CMOS technology parameters in section IV. Finally section V concludes the paper.

II. TRADITIONAL PFSCL (T-PFSCL) STYLE A T-PFSCL circuit consists of three main parts: a

pull-down network (PDN), a constant current source and a load circuit. A generic n-input T-PFSCL gate is shown in Fig. 1a. Its PDN comprise of n NMOS transistors which shares a common source and a drain terminal driven by as many inputs and are source coupled to a feedback transistor Mf whose gate is connected to the output node Q. The constant current source Ms generates the bias current ISS while the load transistor Mp determines the voltage swing.

The circuit of a PFSCL inverter with input A is

shown in Fig. 1b. It works on the principle of current steering. When the voltage at input A is high, the bias current ISS is steered to transistor M1 and a low voltage (VOL = VDD – VP) is obtained at the output where VP is the voltage drop across the load transistor [1]. Similarly, for low value of input A, the transistor M1 is turned OFF and a high voltage (VOH = VDD) is obtained at the output.

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Figure 1 (a) Basic n-input T-PFSCL circuit (b

III. PFSCL WITH CAPACITIVE COUCC) STYLE

The speed of T-PFSCL circuits cthrough the technique of capacitive couarchitecture of the proposed PFSCL-CCPDN similar to the one in T-PFSCL, asource and a load that exhibits capaciPFSCL-CC inverter is shown in Fconsists of a source-coupled transistorimplement the logic function and a currgenerate the bias current ISS. The loNMOS and one PMOS transistors MCin Fig. 2. The reference voltage VBIAS voltage above the supply voltage to allMC1 operate in linear region. The circprinciple of current steering.

When the voltage at input A is

current ISS is steered to transistor M1 a

b) PFSCL inverter

UPLING (PFSCL-

can be improved upling. The basic C style includes a a constant current itive coupling. A ig. 2. Its PDN r pair M1-Mf to rent source Ms to oad includes one 1-MC2 as shown is one threshold

low the transistor cuit works on the

s high, the bias and a low voltage

(VOL = VDD – VP) is obtained at thethe voltage drop across the load tfor low value of input A, the transishigh voltage (VOH = VDD) is obtaine

The mechanism of capacitiv

proposed circuit is analyzed by ccircuit of the inverter (Fig. 2) capacitances at different nodes in thThe capacitances are shown in Figand Cgsci represents the gate-drainbulk capacitance and gate-source ctransistor in the load. The capacitacan be represented by the coupling node Q and the intermediate node XCgdc2) whereas Cgdc1 and Cdbc2 abetween node X and ground as CX Initially, let the voltage at input Aequal to high so that the voltage at QFor a high to low transition at the M1 turns OFF and the voltage at Qfrom VOL to VOH. This change in thecoupled to node X through CC.

Figure 2 Proposed PFSCL

Figure 3 Parasitic capacitances of the t

in the load circuit.

e output where VP is transistor. Similarly, stor M1 is OFF and a ed at the output.

ve coupling in the considering the half and identifying the

he load (MC1-MC2). . 3 where Cgdci, Cdbci

n capacitance, drain-capacitance of the ith ances Cgsc1 and Cgdc2 capacitance between

X as CC (CC = Cgsc1 + are the capacitance (CX = Cgdc1 + Cdbc2). A is assumed to be Q is low (VQ = VOL). input, the transistor

Q (VQ begins to rise e output voltage gets

L-CC inverter

transistors MC1 and MC2

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Let iCC and iCX be the transient currents flowing through CC and CX respectively. By applying the KCL, the current equation at node X can be written as iCC iCX 0 (1)

where it is assumed that negligible current flows in

transistor MC2. Substituting the current values, CX VX CC VQ VX (2) which can be rearranged as VX CCCC CX VQ (3) It can be observe that an increase in the output

voltage results in an increase in the voltage of the node X. In other words a larger gate source voltage is produced at node X than if the gate was connected to a fixed potential. Thus, more current flows through transistor MC1 and the charging process of the output node get accelerated.

IV. SIMULATION RESULTS This section first demonstrates the phenomenon of

capacitive coupling in the proposed PFSCL-CC inverter (Fig. 2) and verifies the theoretical analysis presented in section III. Thereafter, the performance of the proposed PFSCL-CC logic style is compared with the T-PFSCL logic style by simulating different logic gates. All the simulations are performed by using 0.18 µm TSMC CMOS technology parameters and with a supply voltage and load capacitance of 1.8 V and 50 fF

respectively. The bias current of all the circuits is taken as 100 µA uniformly. A. Proposed PFSCL-CC Inverter The proposed PFSCL-CC inverter (Fig. 2) is simulated with a voltage swing of 0.4V to demonstrate the phenomenon of capacitive coupling. The aspect ratios of the transistors are: (W/L)MS = 0.9/0.18, (W/L)M1,Mf = 1.73/0.18, (W/L)MC1 = 0.52/0.18, (W/L)MC2 = 0.47/1.18. The waveforms at the input, output, and intermediate X nodes are shown in Fig. 4. It can be observed that the rising output voltage increases the voltage of node X which confirms to the theoretical analysis presented in section III. B. Performance Comparison Several logic gates such as inverter, NOR2, NOR3 and NAND2 based on the proposed PFSCL-CC style and T-PFSCL style are implemented for purpose of comparison. The circuits of the PFSCL-CC NOR2, NOR3 and NAND2 gates are shown in Fig. 5. It may be noted that since all the circuits are implemented with the same supply voltage and bias current therefore they will consume same static power which is computed as the product of the supply voltage and bias current [4]. The delay of the gates based on both the logic styles is listed in Table I. It can be observed that a maximum delay improvement of 31 percent can be obtained by using the proposed PFSCL-CC style.

Figure 4 Voltages at different nodes of the proposed PFSCL-CC inverter

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Figure 5 Proposed PFSCL-CC gates a) 2-input NOR (NOR2), b) 3-input NOR (NOR3), c) 2-input NAND (NAND2)

TABLE I. DELAY (PS) COMPARISON OF LOGIC GATES Logic Gate T-PFSCL gate PFSCL-CC gate Percentage

reduction Inverter 252 192 23 % NAND2 221 173 21 % NOR2 371 271 27 % NOR3 646 442 31%

V. CONCLUSIONS

In this paper, a new PFSCL-CC style to increase the speed of the digital circuits in comparison to the T-PFSCL style is proposed. The proposed style replaces the PMOS load used in T-PFSCL with a new load that exhibits capacitive coupling. The capacitive coupling phenomenon has been modeled and validated through SPICE simulations using TSMC 0.18 µm CMOS technology parameters. Several PFSCL-CC logic gates are implemented and their performance is compared with the T-PFSCL logic gates. It is found that 31 percent delay reduction can be achieved by employing proposed PFSC-CC style in the design of logic circuits.

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Evaluation of Positive-Feedback Source-Coupled Logic, IEEE Transactions on Circuits and Systems—I: Regular Papers 51 (12), 2004, pp. 2345-2355.

[2] H. Hassan, M. Anis and M. Elmasry, “MOS Current Mode Circuits: Analysis, Design, and Variability,” IEEE Ttransactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 8, pp. 885-898, 2005.

[3] K. Gupta, R. Sridhar, J. Chaudhary, N. Pandey, M. Gupta, Performance comparison of MCML and PFSCL gates in 0.18μm CMOS Technology, in proceedings of IEEE International Conference on Computer and Communication Technology, pp1-4, 2011.

[4] M. Alioto, L. Pancioni, S. Rocchi, and V. Vignoli, Power-Delay-Area-Noise Margin Tradeoffs in Positive-Feedback MOS Current Mode Logic, IEEE transactions on Circuits and Systems -I, 54 (9) (2007) pp.1916-1928.

[5] M. Alioto, A. Fort, L. Pancioni, S. Rocchi, and V. Vignoli, An approach to the design of PFSCL gates, in Proceedings of ISCAS’05, pp. 2437–2440, 2005.

[6] K. Gupta, N. Pandey, M. Gupta, “MOS Current Mode Logic with Capacitive Coupling,” ISRN Electronics, vol. 2012, Article ID 473257, 7 pages, 2012. doi:10.5402/2012/473257.

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