IMPACT-2013

978-1-4799-1205-6/13/$31.00 ©2013 IEEE

A Novel High SpSelect Adder f

Kirti Gupta#1

#Electronics and Commun1kirtigupta_22@yahoo.com, 2

*Electronics and Com4

Abstract— This paper presents a MOS cu

(MCML) square root carry select adder (SQbe used as an alternative to MCML ripple cawhen the number of bits in the input worproposed 16-bit MCML SQ-CSA has been simulated in PSPICE using TSMC 1technology parameters. Its performance hawith 16-bit RCAs based on CMOS and MCMbit CMOS SQ-CSA. It is found that the MCML SQ-CSA reduces the worst case dela72.49% in comparison to the MCML and CMrespectively. Also, the proposed 16-bit Madder results in 26.55% reduction in delay CMOS SQ-CSA. In terms of power cproposed MCML SQ-CSA shows a reducticomparison to CMOS SQ-CSA.

Keywords— MCML, RCA, Square Root CaHigh Speed

I. INTRODUCTION

The increasing demands for high-speed anmixed-signal integrated circuits dictates tcurrent mode logic (MCML) style in the circuits in contrast to traditional CMOS MCML style is characterized by low switcpower consumption independent of frcharacteristics makes MCML style more CMOS logic style for providing an environment suited for mixed-signal applicat

Addition is a fundamental arithmetic ope

base of many other commonly used arithwidely used in VLSI systems. The overall psystem can be improved by using efficiedesign. Different implementations of a MCadder (RCA) have been suggested in [7]. Inadder cell is required to wait for the incominprevious stage before generating an outgoi

peed MCML Square Rofor Mixed-Signal Appli

1, Radhika#2, Neeta Pandey#3, Maneesha Gupta*4 nication Department, Delhi Technological University, New2radhikatanwar90@gmail.com, 3n66pandey@r

mmunication Department, NSIT, Delhi University, New De4maneesha_gupta60@yahoo.com

urrent mode logic Q-CSA) which can

arry adder (RCA) rds is large. The implemented and

180 nm CMOS as been compared ML styles and 16-

proposed 16-bit ay by 67.50% and MOS based RCAs MCML SQ-CSA in comparison to

consumption, the ion of 58.97% in

arry Select Adder,

nd high resolution the use of MOS design of digital logic style [1].

ching noise, static requency. These suitable than the analog friendly

tions [2-6].

eration and is the hmetic operations erformance of the ent adder in the CML ripple carry n RCA, every full ng carry from the ing carry. In this

paper, MCML implementation of aselect adder (SQ-CSA) with improvRCA is presented.

The paper first presents a briefstyle in section II. Thereafter, SectioMCML RCA and presents the propoproposed circuit is implemented, simdiscussed in section IV. All the simPSPICE using TSMC 180 nm CMOFinally, the conclusions are drawn in

II. MCML CIRA MCML circuit consists of three includes a pull-down network (PDsource, and a load circuit. The cMCML inverter is shown in Fig. source-coupled transistor pair M1constant current source generates tthe load resistor RL determines the o The circuit works on the princwherein the bias current ISS is steebranches depending on the input vol

Figure. 1 MCML In

oot Carry cationsw Delhi rediffmail.com

elhi

a square-root linear carry-ved performance than the

f introduction to MCML on III covers the review of osed SQ-CSA circuit. The mulated and the results are

mulations are performed in OS technology parameters. n section V.

RCUITS main components which

DN), a constant current circuit of a conventional 1. Its PDN consists of a -M2 with input A. The he bias current ISS while utput voltage swing [8]. ciple of current steering, ered to one of the circuit tage. When the voltage at

nverter

194

IMPACT-2013

978-1-4799-1205-6/13/$31.00 ©2013 IEEE

input A is low, the bias current ISS is steeredand results in a high output voltage (VOH = Vwhere VR is the voltage drop across the loadwhen the input A is high, the bias current ISand a low output voltage (VOL = Vout1 - Vout2

III. MCML ADDERS

A. Ripple Carry Adder (RCA) A N-bit RCA is an iterative combinationaconstructed by cascading N full addersconnecting carry output of each full adder tof the next most significant full adder . The a 4-bit ripple-carry adder with two 4-bit inpucarry signal, c_in is shown in Fig. 2. The cbit sum and a carry bit, c_out as the output. Fig. 2, the carry bit ‘‘ripples’’ one stage to th

The same scheme can be applied to imRCA. In general, for aN-bit RCA, the wodefined when a carry generated from leapositions propagates to the most significantworst-case delay is then proportional to the nin the input word. Thus, when the number oword is large, then the use of RCA is unsuita

B. Square-Root Carry-Select adder (SQ-CSA

A Square-root carry-select adder (SQ-CSform of adder is used whenever the numberinput word is large. It is a derivative of liadder (CSA) in which variable sized inputs RCA adder block. The variable sizing of the in avoiding the mismatch that occurs in difference between the arrival time of sum an

The block diagram of a 16-bit square-rooinputs A and B is shown in Fig. 3. It consisadders with sizes of 2-2-3-4-5. A RCA is usfor LSBs (two in number) followed by CSAsize input.

d to transistor M2 Vout1 - Vout2 = VR) d [8]. Conversely, S is steered to M1 = -VR).

al circuit which is s in series and to the carry input block diagram of

uts A and B and a circuit provides 4-It can be noted in

he other. mplement an N-bit orst-case delay is ast significant bit t bit position. The number of the bits of bits in the input able.

A)

SA) an improved r of the bits in the inear carry select are given to each RCA block helps CSA due to the nd carry signals. ot adder with two sts of 5 blocks of

sed as adder block As having variable

Figure. 2 Block Diagram o

Each N-bit CSA consists of operating in parallel wherein onaddition by anticipating input carrcomputes the results with input carvalue of the incoming carry signal isis selected by a 2:1 multiplexer stagin Fig. 4.

A N-bit RCA block is implemenadders stages as shown in Fig. 2. Tfor the sum and carry function impin Fig. 5a and b. The circuits are regating approach [8]. The sum and employs a three input exclusive OR(two out of three) respectively. The is a binary tree-like, three-level MCinput at the bottom, the signal B in tthe top level. This topology lowersthe first stage [7]. The MCML carrcarry (c_in) connected to the botwhich minimizes the delay during circuit for a MCML 2:1 multiplexerI1) and select line SEL is shown in the two RCA blocks are connectedmultiplexer while the actual input cline.

The total carry propagation delayfull adder delays, and four multiplethe 16 full adder delays of the RCinputs say N, RCA delay is linwhereas delay of SQ-CSA is propothis topology is faster than linear ocan be utilized for high speed circuit

Figure. 3 A 16-bit SQ-CSA

of 4-bit RCA

two N-bit RCA blocks e RCA block performs ry as 0 while the other rry as 1. Once the actual s known, the correct result ge. A 4-bit CSA is shown

nted by cascading N full The MCML based circuits

lementations are reported ealized by using the series

carry generation circuits R (XOR) and a majority PDN of the sum (Fig. 5a) CML circuit with a carry the middle and signal A at s the load capacitance on ry circuit in Fig. 5b has a ttom transistors in PDN worst-case analysis. The r with input lines (I0 and Fig. 5c. The outputs from

d to the inputs line of the carry behave as the select

y for the SQ-CSA is two exer delays in contrast to CA. For large number of early proportional to N rtional to √ [9]. Hence,

organization and therefore t design.

195

IMPACT-2013

978-1-4799-1205-6/13/$31.00 ©2013 IEEE

(a)

(b)

Figure 4. Basic Carry Select Adder block

(cFigure.5 MCML based full adder (a

generation circuit (c)

IV. SIMULATIA 16-bit MCML SQ-CSA (Fig

using CMOS TSMC 180 nm tevoltage swing of 400 mV. The isimulation of the circuits are show

The waveforms for the final oubit for the worst case conditionB=00000000000000 and c_in=1 iwaveforms confirm to the functio

TABLE I. SIMULAT

Technology Temperature

Supply Voltage Output Load Capacito

Bias Current Frequency of input

Load Resistance the proposed 16-bit MCML squ

compared with the 16-bit MCM

) a) sum generation circuit (b) carry 2:1 MUX circuit

ION RESULTS g. 3) is simulated in PSPICE

echnology parameters with a input parameters taken in the wn in Table I. utput carry and the MSB sum n are A=1111111111111111 is shown in Fig. 6. The above

onality. The performance of

TION ENVIRONMENT

180 nm 27 ºC 1.8V

or 10 fF 50 µA

250 MHz 4 KΩ

uare root carry select adder is L and CMOS RCA to show

196

IMPACT-2013

978-1-4799-1205-6/13/$31.00 ©2013 IEEE

the improvement in the delay with the use of the proposed circuit. Additionally, a CMOS 16-bit square root carry select adder is also simulated for the sake of completeness.

From Table II, it can be observed that the proposed 16-bit MCML SQ-CSA reduces the delay by 26.55% reduction in delay in comparison to CMOS SQ-CSA. Further, the proposed 16-bit MCML SQ-CSA reduces the worst case delay by 67.50% and 72.49% in comparison to the MCML and CMOS based RCAs respectively. Thus it can be inferred that the proposed 16-bit MCML SQ-CSA adder is a fast adder and can be preferred for high speed applications.

The circuits have also been compared in terms of power consumption. For CMOS based and MCML based circuits, the values of dynamic and static power consumption have been reported in Table III. It can be seen that a power reduction of 59.97 % is achieved for the proposed 16-bit MCML SQ-CSA in comparison with CMOS SQ-CSA.

TABLE II. WORST CASE DELAY (NS) OF ADDERS

Adder Output Carry CMOS RCA 3.23

CMOS Square root CSA 1.30 MCML RCA 2.97

MCML Square root CSA 0.96 .

(a)

(b)

Figure. 6 Output waveforms of the 16-bit MCML Square Root CSA a) final output carry b) MSB of the sum

TABLE III. . POWER DISSIPATION (MW) OF ADDERS

Adder Power(mW)

CMOS RCA 13.730 CMOS Square root CSA 35.529

MCML RCA 7.780 MCML Square root CSA 16.039

V. CONCLUSION

In this paper a MCML square root carry select adder (SQ-

CSA) for addition of large number of bits in the input words is presented. The proposed 16-bit MCML SQ-CSA has been implemented and its performance is compared with 16-bit RCAs based on CMOS and MCML styles and 16-bit CMOS based SQ-CSA. It is found that the proposed 16-bit MCML SQ-CSA reduces the worst case delay significantly in comparison to the MCML and CMOS based RCAs. Also, the proposed 16-bit MCML SQ-CSA is faster by 26.55% in comparison to CMOS based 16-bit SQ-CSA. Further, it is found that the proposed MCML based 16 bit SQ-CSA is power efficient than the others.

REFERENCES [1] M. Yamashina and H. Yamada, An MOS current mode logic (MCML)

circuit for low-power sub-GHz processors, IEICE Trans. Electron., vol.E75-C, pp. 1181---1187, Oct. 1992

[2] M. Mizuno, M. Yamashina, K. Furuta, H. Igura, H. Abiko, K. Okabe, A. Ono, H. Yamada, A GHz MOS, Adaptive Pipeline Technique using MOS Current-Mode Logic, IEEE J. Solid-state Circuits, Vol. 31, pp. 784-791, No. 6, June 1996..

[3] T. K. Agarwal, A. Sawhney, A. K. Kureshi,M. Hasan, Performance Comparison of Static CMOS and MCML gates in sub- threshold region of operation for 32nm CMOS Technology, Proceedings of the International Conference on Computer and Communication Engineering, Malaysia pp. 284-287, 2008.

[4] J. M. Musicer, J. Rabaey, MOS Current Mode Logic for Low Power, Low Noise, CORDIC Computation in Mixed-Signal Environments, Proc. ISLPED, pp.102-107, July 2000.

[5] S. Bruma, Impact of on-chip process variations on MCML performance, Proceedings of IEEE Conference on Systems-on-Chip, 2003, pp. 135–140.

[6] Tajalli, Armin, Leblebici, Yusuf, “Extreme Low- Power Mixed Signal IC Design,”Springer Science,US, 2010

[7] K. Gupta, N. Pandey, M. Gupta, ‘‘A Novel Active Shunt-Peaked MCML-based High Speed Four-Bit Ripple-Carry Adder,’’ in proceedings of IEEE International Conference on Computer and Communication Technology, pp:285-289, 2010.

[8] M. Alioto and G. Palumbo, Model and Design of Bipolar and MOS Current-Mode logic (CML, ECL and SCL Digital Circuits), Springer, New York,2005.

[9] J. Rabaey, and N. Chandrakaran,” Digital Integrated Circuits: A Design Perspective”, Prentice Hall, 2003.

197