Challenges in 3D Me

Micron Techno

Abstract Memory industry transition from plana

and the introduction of several new emdevices into manufacturing over the next dedrive several new and unique manufacturiintegration challenges. The inflection poinwith is a new paradigm where advancemescience, non-litho equipment technologycharacterization methods, and control metlead the way for scaling cadence.

Introduction

Role of memory devices is transcommodity components to advanced solutions enabling new applications. Sucdemand higher level of quality and reliabito higher density and lower cost. NANDwhich have led the industry in terms of scare showing a slowing down faced with meeting higher quality at lower cost (Figu

Figure 1: DRAM and NAND scaling tren

Traditional memory scaling has beenlithography advancements. Every 3-5 yeaadvanced in its imaging and alignment cashrink cadence. Other processing technologplanarization, materials, etc.) evolved aroucadence. While lithography continues tcapability into EUV space, improvements inmultiplication technology and associated coof film deposition and etch tools over the enabled the memory industry to patterngeometries without the need for significant iadvancements (Figure 2).

emory Manufacturing and Process InteNaga Chandrasekaran

ology, 8000 S. Federal Way, Boise, Idaho, USA 83707

ar to 3D scaling merging memory ecade is going to ing and process nt we are faced ents in materials y, testing and thodologies will

sitioning from system level

ch applications ility in addition D and DRAM, caling cadence, the conflict of

ure 1).

nds over time

n dependent on ars, lithography apability driving gies (films, etch, und lithography to advance its n complex pitch ontrol capability last 5 years has n sub 1X nm image resolution

Figure 2: Lithography transitio

Figure 3: DRAM capacitor

Continued longevity of scalindevice reliability challenges, equchallenges, and physical limitationcapacitor challenges get increasinghigher aspect ratio and dielectri(Figure 3). Planar NAND is not challenges as it approaches atomicalso faced with high electric fieldsdisturb issues, and the requiremeelectrons to maintain good device p

Figure 4: Transition of Planar Ndimensions from (a) 4X nm to (b

egration

on over the last decade

scaling challenges

ng cadence is limited by uipment challenges, cost ns. For example, DRAM gly difficult to solve with ic constant requirements only faced with physical

c scale (Figure 4), but it is s (Figure 5), interference, nt to control only a few performance (Figure 6).

NAND scaling to atomic b) 2X nm to (c) 1X nm

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Figure 5: Correlation between WL-WL eaproaching breakdown limits as WL half p

Figure 6: Correlation between feature size electrons for a 100mV Vt shift

Inflection Point: Alternatives to Conven

The critical scaling limitations facedmemories are being overcome by two para(1) Transition from 2-D to 3-D structuresemerging memory technologies. Theapproaches are driving new and uniqchallenges in memory development and With these new development approaches, mand technology development is going throupoint (Figure 7). Today, we are seeing a flatcadence, multiple divergent new memortransition to 3D memory development, requirements, and higher demands placed onand planarization areas relative to lithogramemory architectures also demand new ctesting, and failure analysis requirementunderstanding of electrical and devicrequirements. These new and unique discussed in subsequent sections.

electric fields itch is reduced

and number of (1)

ntional Scaling

d by traditional allel approaches: s and (2) novel ese innovative que technology

manufacturing. memory scaling

ugh an inflection ttening of shrink ry technologies, unique process

n dry etch, films, aphy. Such new characterization, s and a better

ce performance challenges are

Figure 7: Memory techno

A. 3D Memory: The term 3Dbe used to reference several approused in two contexts: (1) Front endthe storage bits are now placed in v8 a and b) and (2) back end stackhigh speed logic layer to increlatency, and reduce footprint (FigNAND structures incorporate tall film layers, and high aspect ratPackaging (MCP) technologiestechnology development includin(TSV), interconnects, bonding, packaging requirements.

(a)

(c )

Figure 8: Schematics and actualvertical NAND (a & b) and 3D

ology inflection point

D memory integration can oaches. In this article, it is d Si 3D integration where vertical direction (Figures

king of memory chips and ease bandwidth, improve gures 8 c & d). Vertical thick stacks, several thin io channels. Multi Chip s has driven unique ng Through Silicon Via

dicing, and advanced

(b)

(d)

l cross-section showing D integration (c & d)

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B. Emerging Memory: A large numbmemory technologies are being evaluated bcommunity (2). Most of these devices arenature targeting storage class applications. Trelative performance comparison between memory technologies. As can be seen from tno one single emerging memory technologthe key performance requirements to rconventional memory technologies. Ovememory technologies might improve in perfable to penetrate a segment of the memory mbe a long time before they are able to compewith conventional DRAM or NAND applicat

Table 1: Qualitative performance assessmemerging memory technologie

Phase Change Memory (PCM) is currentbut is mostly directed towards a NOR memor to be used in system level solutions witstill consumes significant energy per bit andwith bit density. For a filamentary Resisactive region of the cell (filament) is in theven though the overall cell dimension is expor 3X nm. This results in very low power pthe involvement of very few atoms. At thecell is stochastic in nature and the distributiocontrol due to the involvement of few atoms.also suffer with higher power per bit drivefficiency, damping, and thermal agitation. reduce the current but it involves optimizastack parameters simultaneously leading to c

While significant improvements are beimaterials side and equipment performamemory technologies still need significant the design, sensing schemes, interface deadvanced controller development to make thenter main stream memory market. Foremerging memory technologies, the medilooks good but the tail bits are difficult to cbits can be managed with different error corbut will lead to increased cost and imperformance.

ber of emerging by the scientific

e non-volatile in Table 1 shows a these emerging

the table there is gy that meets all replace existing er time, these formance and be market but it will ete head-to-head tion space.

ment of several es

tly in production mory replacement

th NAND. PCM d has challenges stive RAM, the he range of 5nm plained to be 2X er bit but due to

e same time, the on is difficult to . STTRAM cells en by tunneling It is possible to ation of several

complications.

ing made in the ance, emerging development in

evelopment, and ese technologies r many of the an bit typically control. The tail rrection schemes mpact to speed

Many of the elements used eitha combinatorial material in emergTe, Sb, to name a few) are exotcommonly used in semiconDepositing such materials using A(ALD) or sputtering techniquesprecursor, target, and deposition These unique materials presenchallenges as well (wet cleans, drydisposal, to name a few). In additsignificant thermal processing conprocessing temperatures (<300 deposition. For example, with STthe thin stack of multiple materialstunnel oxide, etch impact to theslimitations are constraints that still

3D Front End Technolo

Transition from planar NANintroduced unique structural charchitecture, different 3D NAND alternating layers of thick oxide conductor layers to form the verti2μm high and continuing to scale deposition results in high stress, deissues (Figure 9).

Figure 9: Cross-section image shratio gap fill structure and an ex

Figure 10 is a schematic of the

the channel formed in the array as wthe periphery to access the wordcomplex etches are required to pratio structures with tight within dibottom), and within wafer uniformtimes and unique hardware develthese tall gaps between structureplanarized. Within these etchedconformal thin films need to bememory elements (sub 10nm) in thfloating gate. Control of these thcritical requirement.

her in elemental form or as ing memory devices (Ge, tic materials and are not nductor manufacturing. Atomic Layer Deposition s still needs significant

technique development. nt additional processing y etch, segregation, waste tion, such materials place nstraints limiting allowed

C) during and post TRAM, understanding of s, behavior of MgO based se materials, and thermal need to be understood.

ogy Challenges

ND to 3D NAND has allenges. Based on the device manufacturers use and nitride or oxide and ical NAND structures (1-thicker). Such thick film

elamination, and cracking

howing wide high aspect xample of stress crack

tier stack and also shows well as contacts formed in d lines. As can be seen, pattern these high aspect ie, within structure (top to

mity resulting in long etch lopment. Post patterning, es have to be filled and d structures (channels), e deposited to form the he form of charge trap or

hin film uniformities is a

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Figure 10: Schematic of a vertical NANDshowing etch, cleans, gap fill, thin film de

planarization challenges

3D Backend Integration Challe

Some of the recent 3D integration technbuilding stacks of DRAM and logic mThrough Silicon Via (TSV) and complepackaging techniques (Figure 11). 3technology faces several equipment antechnology challenges. On the equipment dicing, and packaging equipments have notsame level of control capabilities as the frontechnology. On the fundamental technolintegration is challenged by wafer handling,management, and stress constraints (Figure 1

Figure 11: 3D die stacking with memory

attached using advanced packaging te

Figure 12: Thin wafer warpage post thinninhandling, processing, and testing of su

While TSV etch, plating, and via reveal prcritical gating elements in 3D integration, several reliability and quality challenges. Timpacts plating dimensions resulting in platiwhen exposed during subsequent steps can challenges. In addition, voids along interconnect is an industry wide challengmaterials and bonding process development.

D architecture eposition, and

enges

nologies involve memories using ex bonding and 3D integration nd fundamental

front, bonding, t evolved to the

nt end equipment logy front, 3D , thermal budget 12).

and logic die echniques

ng challenging uch wafers

rocesses are not they do present

TSV etch profile ing voids, which create reliability the bond and

ge that requires

Manufacturing C

Manufacturing activities in a seintroduction of a new technologfocused on yield improvementimprovements, and cost improvMost of these activities at best werprocess flow conditions and evimprovement activities with eqfuture, more innovative hands on dbe required not only in the R&Dmanufacturing phase as these newevolve over the next couple of gemodes will require additional learnachieved.

Figure 13 shows compariso

complexity evolution for DRAM stransition. There is an increased films, and CMP. Even though frperspective, Metrology does not shthe complexity in this area has charea complexities impacts fab layoof transition between technologiesWith 3D transition, additional fronthe areas of dry etch and films. Invertical NAND equipment sets are a learning curve among manufparallel, back end equipmeimprovement, process control, analso need to improve and align with

Several of the new materials u

devices are exotic materials. Procthe facility requires new safety proand implemented. Films, etch, anmore exotic precursors and corrosithe cell materials. Handling of thprocessing conditions, and post palso need to be studied and underst

Characterization and Failure

3D memory and emerging mplacing significant structural and mchallenges. Most of the techniqumaterials and their performance (Xdata) still lack the ability to perfohigh throughput to use such tecmeasurements. In addition, manytechniques still induce some amounleading to ambiguity in interprcharacterizing emerging memMeasuring CDs at the bottom of himeasuring thin layers, stress, strgenerating profile measurements

hallenges

emiconductor facility post gy node has traditionally t, equipment efficiency

vement related activities. re incremental changes to valuation of continuous

quipment technology. In development efforts might D phase but also in the

w devices will continue to enerations and the failure ning till mature yields are

on of relative process shrink and vertical NAND

complexity in dry etch, from a raw process time how a significant increase, hanged. These changes in out, space trade ratio, cost s, and talent management. nt end talent is needed in n addition, several of the new and unique requiring

facturing technicians. In nt engineering, yield d manufacturing systems h front end capabilities.

used in emerging memory cessing such materials in ocedures to be understood nd cleans are also using ive chemistries to process

hese chemicals, materials, processing waste disposal tood.

e Analysis Challenges

memory technologies are materials characterization ues used to characterize X-ray techniques or TEM orm elemental analysis at chniques as line control y of the characterization nt of material state change reting failure states and

mory technologies (3). igh aspect ratio structures, ructural registration, and s for high aspect ratio

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structures is a constant challenge. Complex pitch multiplication technologies drive the need for advanced control methodologies. As we approach 1x and sub 1x nm geometries or 3D integration with complex techniques, managing variability in the line becomes even more critical.

Figure 13: Relative increase in processing time for device transition for DRAM and planar to vertical NAND

In addition to characterization challenges noted above, there are significant issues with correlating probe failures to physical defects in line. In the case of vertical NAND, we are faced with embedded defects that are not visible inline. Identifying and locating defects in vertical NAND is a big challenge. There is an increased drive towards using E-beam inspect technologies to identify structural defects. In the case of 2.5D/3D structures we have several buried interconnects and TSV structures that are not easy to isolate. Also, cost of target preparation in the case of package failure analysis can be significantly high. Techniques such as lock-in thermography can provide advantages in effective localization for 3D integrated devices. FIB target preparation for 3D devices to understand defects can be extremely time consuming (due to amount of material to be removed) and the precision required (4).

Testing Challenges

Testing 3D IC devices involves detecting and understanding failure modes not only at the component level but also at an increasingly complex package level. As Semiconductor industry enters the 3D scaling paradigm, testing requirements are also evolving. In a multi die product, one must consider the accumulated yield of all die and processing steps. As we increase number of components and processing steps in a multi die package, final cumulative yield loss can be significant even if the contribution of individual steps is <1%. Each interim product step must have Known Good Die (KGD) and KGD is critical to improving cost structure with 3D integration.

New techniques will be required to test the silicon interposers with TSV and 3D devices but at the same time an increasing need to keep test costs lower. Ability of probe technology to handle finer pitch TSV tips, eliminate probe created scrub mark defects, and handling of thinned wafers are all significant challenges in the new 3D paradigm (5). 3D stacking also introduces intra die defects due to several processing steps, which needs to be detected and understood. Thinned die and multiple materials with different thermal expansion coefficients also create thermo-mechanical problems that can lead to test and probe issues.

Summary

Memory industry transition from planar to 3D scaling and introduction of emerging memory devices into manufacturing over the next decade is going to drive several new and unique challenges. The inflection point that we are faced with is a new paradigm where advancements in materials science, equipment technology, and control methodologies are critical for scaling cadence. While the economics value of transition from 300mm to 450mm continues to be a debate, there is no doubt that the vertical scaling challenges will increase by an order of magnitude for 450mm. It is critical that the industry resolve vertical scaling challenges on 300mm before 450mm transition.

Acknowledgements

Author would like to acknowledge the efforts of various engineering and integration teams in Micron Technology. In particular, author acknowledges guidance from Kirk Prall, Chuck Dennison, Greg Atwood, Keith Cook, and Gurtej Sandhu in preparation of this manuscript.

References [1] G. Atwood, “Current and Emerging Memory Technology Landscape”, 2011, Flash Summit 2011, CA [2] K. Prall, N. Ramaswamy, W. Kinney, K. Holtzclaw, X. Chen, J. Strand, and R. Bez, “An Update on Emerging Memory: Progress to 2Xnm”, Memory Workshop (IMW), 2012 4th IEEE International, Milan, May 2012 [3] N. Chandrasekaran, S. Hues, S. Lu, D. Li, C. Bishop, “Characterization and Metrology Challenges for Emerging Memory Technology Landscape”, Frontiers of Characterization and Metrology for Nanoelectronics, NIST, Gaithesburg, p. 24, 2013 [4] J. Beyersdorfer, F. Altmann, C. Grobe, S. Hubner, M. Simon-Najasek, A. Graff, “Preparation on 3D Interconnects”, EFUG Meeting, 2011, Bordeaux [5] G. Fleeman, “3D and 2.5D Challenges”, GSA/Sematech Memory Conference, Tokyo, Japan, Apr 2012

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